[NFC][RISCV] Move getSEWLMULRatio function to header

[asi-sc]

Summary

More uses of getSEWLMULRatio will be added in D130895.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

191

Is the namespace qualifier on decodeVLMUL still needed?

[asi-sc]

Addressed review comments

[frasercrmck]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

191

I don't know if this is something that benefits from a structured binding.

[asi-sc]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

191

Honestly, exactly here I don't see any reason to use structured binding as the current solution has better readability (imo) and there is no need for extra optimizations. Though, if anybody has concerns regarding to this, let's use structured bindings.

[craig.topper]

LGTM

[asi-sc]

Thanks for the review.
@frasercrmck, could you please submit the patch on my behalf? Author: Anton Sidorenko <[e-mail]>

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 }
 
 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
 
 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
 
 void printVType(unsigned VType, raw_ostream &OS);
 
+unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
+
 } // namespace RISCVVType
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

else
     OS << ", tu";
 
   if (isMaskAgnostic(VType))
     OS << ", ma";
   else
     OS << ", mu";
 }
 
+unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
+  unsigned LMul;
+  bool Fractional;
+  std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
+
+  // Convert LMul to a fixed point value with 3 fractional bits.
+  LMul = Fractional ? (8 / LMul) : (LMul * 8);
+
+  assert(SEW >= 8 && "Unexpected SEW value");
+  return (SEW * 8) / LMul;
+}
+
 } // namespace llvm

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

 static bool isMaskRegOp(const MachineInstr &MI) {
   if (!RISCVII::hasSEWOp(MI.getDesc().TSFlags))
     return false;
   const unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm();
   // A Log2SEW of 0 is an operation on mask registers only.
   return Log2SEW == 0;
 }
 
-static unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
-  unsigned LMul;
-  bool Fractional;
-  std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(VLMul);
-
-  // Convert LMul to a fixed point value with 3 fractional bits.
-  LMul = Fractional ? (8 / LMul) : (LMul * 8);
-
-  assert(SEW >= 8 && "Unexpected SEW value");
-  return (SEW * 8) / LMul;
-}
-
 /// Which subfields of VL or VTYPE have values we need to preserve?
 struct DemandedFields {
   bool VL = false;
   bool SEW = false;
   bool LMUL = false;
   bool SEWLMULRatio = false;
   bool TailPolicy = false;
   bool MaskPolicy = false;
if (Used.SEW &&
       RISCVVType::getSEW(VType1) != RISCVVType::getSEW(VType2))
     return false;
 
   if (Used.LMUL &&
       RISCVVType::getVLMUL(VType1) != RISCVVType::getVLMUL(VType2))
     return false;
 
   if (Used.SEWLMULRatio) {
-    auto Ratio1 = getSEWLMULRatio(RISCVVType::getSEW(VType1),
+    auto Ratio1 = RISCVVType::getSEWLMULRatio(RISCVVType::getSEW(VType1),
                                               RISCVVType::getVLMUL(VType1));
-    auto Ratio2 = getSEWLMULRatio(RISCVVType::getSEW(VType2),
+    auto Ratio2 = RISCVVType::getSEWLMULRatio(RISCVVType::getSEW(VType2),
                                               RISCVVType::getVLMUL(VType2));
     if (Ratio1 != Ratio2)
       return false;
   }
 
   if (Used.TailPolicy &&
       RISCVVType::isTailAgnostic(VType1) != RISCVVType::isTailAgnostic(VType2))
     return false;
   if (Used.MaskPolicy &&
bool hasSameVTYPE(const VSETVLIInfo &Other) const {
     return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
            std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic,
                     Other.MaskAgnostic);
   }
 
   unsigned getSEWLMULRatio() const {
     assert(isValid() && !isUnknown() &&
            "Can't use VTYPE for uninitialized or unknown");
-    return ::getSEWLMULRatio(SEW, VLMul);
+    return RISCVVType::getSEWLMULRatio(SEW, VLMul);
   }
 
   // Check if the VTYPE for these two VSETVLIInfos produce the same VLMAX.
   // Note that having the same VLMAX ensures that both share the same
   // function from AVL to VL; that is, they must produce the same VL value
   // for any given AVL value.
   bool hasSameVLMAX(const VSETVLIInfo &Other) const {
     assert(isValid() && Other.isValid() &&