[RISCV] Make VL choosing for a splat-like VMV based on its users

[asi-sc]

Summary

In some cases VL of VMV/VFMV instructions exceeds required value, e.g. when we
convert SPLAT_VECTOR to vector move. It may cause insertion of extra/too wide
vsetvli instructions. We can look for common VL of the users to choose the
optimal VL value.

PR#55615

[craig.topper]

What if the user is the merge operand of a tail undisturbed instruction. The VL of the using instruction would not apply to it then.

[asi-sc]

In D130895#3691031, @craig.topper wrote:

What if the user is the merge operand of a tail undisturbed instruction. The VL of the using instruction would not apply to it then.

Thanks for catching that! I've looked at how to fix this problem and while we can easily check the policy, it seems not possible for now to figure out whether intrinsic has merge operand. We can extend intrinsics markup explicitly saying the position of the merge operand similar to VLOperand and ScalarOperand. What do you think? The fix should not be hard if the position of merge operands is known.

[asi-sc]

A gentle ping on the question about adding a markup of merge operands for intrinsics.

[craig.topper]

In D130895#3718978, @asi-sc wrote:

A gentle ping on the question about adding a markup of merge operands for intrinsics.

Sounds fine to me. But the more important case to fix is RISCVISD::*_VL nodes. I'm not sure how common it is to have splats combined with intrinsics. intrinsics come from C code where the splats should have been done with a vmv.v.x initrinsic that would already have the correct VL.

[asi-sc]

Make VL choosing for a splat-like VMV based on its users

In some cases VL of VMV/VFMV instructions exceeds required value, e.g. when we
convert SPLAT_VECTOR to vector move. It may cause insertion of extra/too wide
vsetvli instructions. We can look for common VL of the users to choose the
optimal VL value.

[asi-sc]

A gentle ping

In D130895#3719413, @craig.topper wrote:

Sounds fine to me. But the more important case to fix is RISCVISD::*_VL nodes. I'm not sure how common it is to have splats combined with intrinsics. intrinsics come from C code where the splats should have been done with a vmv.v.x initrinsic that would already have the correct VL.

New patch generalized implementation to support RISCVISD::*_VL nodes.

Also, attaching statistics showing the number of VL shinks

                  test-suite :: External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r.test 167.00
                 test-suite :: External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s.test 167.00
     test-suite :: External/SPEC/CINT2017speed/623.xalancbmk_s/623.xalancbmk_s.test 164.00
      test-suite :: External/SPEC/CINT2017rate/523.xalancbmk_r/523.xalancbmk_r.test 164.00
             test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test  75.00
                     test-suite :: MultiSource/Benchmarks/mafft/pairlocalalign.test  70.00
           test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test  47.00
               test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test  31.00
                test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test  31.00
                      test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test  27.00
                          test-suite :: MultiSource/Applications/oggenc/oggenc.test  22.00
            test-suite :: MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg.test  19.00
      test-suite :: MultiSource/Benchmarks/MiBench/consumer-jpeg/consumer-jpeg.test  19.00
                       test-suite :: MultiSource/Applications/JM/lencod/lencod.test  16.00
           test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test  15.00
          test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test  15.00
             test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test  13.00
          test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C++/miniFE/miniFE.test  12.00
test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C++/HACCKernels/HACCKernels.test  12.00
                        test-suite :: MultiSource/Applications/ClamAV/clamscan.test  12.00
         test-suite :: External/SPEC/CINT2017speed/620.omnetpp_s/620.omnetpp_s.test  11.00
          test-suite :: External/SPEC/CINT2017rate/520.omnetpp_r/520.omnetpp_r.test  11.00
                        test-suite :: MultiSource/Applications/sqlite3/sqlite3.test  11.00
                       test-suite :: MultiSource/Applications/JM/ldecod/ldecod.test  10.00
            test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C++/CLAMR/CLAMR.test  10.00
     test-suite :: External/SPEC/CINT2017speed/600.perlbench_s/600.perlbench_s.test   9.00
      test-suite :: External/SPEC/CINT2017rate/500.perlbench_r/500.perlbench_r.test   9.00
                 test-suite :: MultiSource/Benchmarks/Prolangs-C/bison/mybison.test   7.00
   test-suite :: MicroBenchmarks/LoopVectorization/LoopVectorizationBenchmarks.test   7.00
                  test-suite :: MultiSource/Benchmarks/FreeBench/neural/neural.test   6.00
        test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test   6.00
                 test-suite :: External/SPEC/CINT2017speed/605.mcf_s/605.mcf_s.test   6.00
                    test-suite :: MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4.test   6.00
   ...

[reames]

I've looked at a few ideas in this area, and there's an interaction I want to point out that I don't have a good answer for.

While reducing the VL of a splat to match the demanded lanes can remove vsetv toggles, it can also add them. Specifically, if the splat happens to be scheduled in a region which uses the original wider VL, then reducing the VL actually pessimizes the code. This actually shows up in mixed VL code, particularly when combined with LICM for splats which can't be folded (profitably) into their users.

We can patch part of this by extending InsertVSETVLI to allow increasing VL on splats if the splat is TA. However, there's still a scheduling interaction here which is a bit hard to account for.

I generally do believe that having VL reduction for all computation (not just splats) is generally a good idea; I'm just trying to figure out how to slice the pieces so that we can get there incrementally without nasty regressions along the way.

[asi-sc]

In D130895#3787035, @reames wrote:

I've looked at a few ideas in this area, and there's an interaction I want to point out that I don't have a good answer for.

While reducing the VL of a splat to match the demanded lanes can remove vsetv toggles, it can also add them. Specifically, if the splat happens to be scheduled in a region which uses the original wider VL, then reducing the VL actually pessimizes the code. This actually shows up in mixed VL code, particularly when combined with LICM for splats which can't be folded (profitably) into their users.

We can patch part of this by extending InsertVSETVLI to allow increasing VL on splats if the splat is TA. However, there's still a scheduling interaction here which is a bit hard to account for.

I generally do believe that having VL reduction for all computation (not just splats) is generally a good idea; I'm just trying to figure out how to slice the pieces so that we can get there incrementally without nasty regressions along the way.

@reames, thanks for raising such an important question here. This change only works on splats with TA policy. So, we shouldn't get any regression for TU splats. At the same time combining this patch with modification of InsertVSETVLI you suggested should give only positive effect from my point of view:

1. at DAG to DAG stage minimal VL for vector move is chosen;
2. After modification of InsertVSETVLI we can skip unnecessary vsetv instructions for TA vector moves.

Such order of vector move transformations seems to me pretty reasonable. Let me know if you want me to look into InsertVSETVLI.

[reames]

Spent some time looking at this today. Wrote up my initial investigation as a bug (https://github.com/llvm/llvm-project/issues/57767), mostly because phab doesn't make long format comments easy.

The good news is that the scheduling interaction case I was most worried about doesn't appear to be relevant for this patch. We already have that problem in generic IR; this code is basically only relevant for intrinsics. We have a difference in lowering strategy between fixed length vectors and intrinsics which sends us down two different codepaths.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2546

VL shrinking would not be legal for vs2 of a vrgather.vv or vrgatherei16.vv. The indices can select elements above VL.

I think it's also not legal for vs2 of vslidedown.vi and vslidedown.vx.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2510

I think this would be cleaner as two named variables.

2590

UpdateNodeOperands potentially returns a different pointer than Node if it triggered CSE internally. In that case you need to Replace all uses of Node with the value returned and not run any of the code in caller. See the UpdateNodeOperands call in X86DAGToDAGISel::tryShiftAmountMod for a similar case.

[reames]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

191 ↗

(On Diff #458148)

If you rebase, these have landed through other patches which needed them.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2498

JFYI, this looks suspicious. The node operands of the SDNode and the MI are not guaranteed by construction to be the same. Or at least if they are, we haven't adjusted other code under that assumption and asserted appropriately.

2565

I request that you separate this patch into one which is one-use restricted, and then a second which adds the use walk. The former patch would parallel what we do for e.g. insert_vector folds.

2772

This change is intended to be NFC right? If so, please separate it for review. As mentioned above, the correspondence of SDNode operands and MI operands is non-trivial.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2498

JFYI, this looks suspicious. The node operands of the SDNode and the MI are not guaranteed by construction to be the same.

Then can we guarantee that

• policy operand is the last operand of the node (skipping glue and chain)
• VL operand is just before the policy operand if there is policy, or the last
• merge operand is the first operand after defs?

Of course, only if the corresponding RISCVII:has*Op checker is true.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2565

@reames, do you think that use walk approach will introduce some regressions while one-use approach won't? I'll split the patch, it's not a problem, I'm just trying to understand what issue we are trying to solve by that.

[asi-sc]

Addressed review comments

[asi-sc]

Depends on D134179

[asi-sc]

Rebase

[reames]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1816

We will need to extend this for splats of constants eventually.

2512

This loop is redundant under one-use restriction.

2552

Pull this block out as a helper called: canReadyPastVL.

2573

It's not clear to me why merge ops have anything to do with the legality here.

2576

Policy is implicit for instructions without policy, it is safer to return false here.

Otherwise, look at the tied operand handling in RISCVInsertVSETVLI.cpp for what we'd need to factor out and reuse.

2579

Macro comment: The legality here has me nervous. Might be good to start with a whitelist approach. We can come back and loosen it, but starting with a known good set would make the change less risky.

2592

This loop is redundant under one-use restriction.

2597

This call should become a single retrieval of VL from the single user under the one-use restriction.

2600

getVLOperand

2602

Extract a helper. e.g. isVLLessThan(VL, VL)

Since this runs after selection, I think you need to special case RISCV::VLMaxSentinel.

2616

getVLOpIdx

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2573

The policy applies to how the merge operand is merged. If it doesn't have a merge operand or the use isn't the merge operand then the splat is an input to the arithmetic portion of the instruction which usually obeys VL. Except for the special case instructions above.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1816

Aren't splats already processed in RISCVDAGToDAGISel::PreprocessISelDAG ? Honestly, I thought that ISD:SPLAT_VECTOR here is a legacy that we can remove.

2579

One more idea is that we can forbid changing of VL for the instruction if its result is used as a merge operand. And add support for merge operands in the next patch as a separate feature.
Which option do you want me to follow?

2592

Isn't one-use restriction a temporary thing? I've added it in a way that we can easily drop this restriction and try use-walk (see if above). Is it a real issue that the code obtaining new VL is more generic than it's required for one-use approach? If you think we might eventually end up with one-use approach, then I agree we must completely remove use-walk support from this patch.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1816

I wonder if @reames was noticing that it said V_X_VL and did not include V_I_VL which doesn't exist. Before isel all integer scalar use V_X_VL. Isel checks the size of the immediate and uses vmv.v.i or li+vmv.v.x.

[asi-sc]

Addressed review comments except for a few which have questions from my side.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2576

Thanks for noticing. I changed to return false and added FIXME comment.

2600

We cannot use getVLOperands here (and getVLOpIdx a few lines below) as Node is RISCVISD. At the same time we know that it's VMV/VFMV, so we can be pretty sure in the positioning of operands.

2602

Actually, VLMaxSentinel was handled implicitly (as it is -1ULL and we did zero extension). But I agree we must check it explicitly and do not rely on the exact value of it

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2497

Can we use SDValue() for consistency with the vast majority of SelectionDAG code

2555

I don't think you can assume the using instruction VL is relative to the same SEW/LMUL as the splat. There could have been a bitcast between them that changed the element size. Bitcasts don't generate code. I think insert_subvector/extract_subvector can also change the type without creating any code. Mainly for fractional LMULs.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2555

You'll need to extract the SEW and LMUL from both instructions and make sure they are in the same ratio so they would have the same VLMax.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2555

I tried to write a test that shows the behavior our described. And I have to say it is tricky for me.
Bitcasts preserve SEW/LMUL ratio, llvm.vector.extract intrinsic results in additional COPY at DAG to DAG stage, shufflevector instructions do not support indexes other than zeroinitializer for scalable vectors.
Is it in general correct if the result of VMV is used in the instruction with another SEW/LMUL ratio? It seems to me as something illegal at DAG to DAG stage.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2555

Bitcasts don't preserve the SEW/LMUL ratio. They have a constant LMUL and change the SEW. So an LMUL=4 SEW=32 can become an LMUL=4 SEW=64.

[asi-sc]

Apply VL shrinking only when SEW/LMUL ratio is unmodified. This change depends on D135086

[asi-sc]

Rebase to fetch merged dependency

[asi-sc]

A gentle ping.

I addressed all comments except a few that I'd like to discuss additionally.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2579

This is still unresolved. A whitelist approach worries me. What should be the rule to distinguish good and bad candidates for the whitelist? @reames, could you please share your thoughts?

Is the testing comprehensive enough to follow my suggestion: split the patch, commit parts separately and check the impact on tests?

2592

@reames, do you insist on simplifying all generic code to process only one-use nodes? Original issue #55615 requires multiple uses support, so eventually it must be introduced anyway. Currently, use-walk is disabled in a way that we can enable it back by removing two lines on the code.

[reames]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2579

How do you propose to split the patch?

One way would be to introduce a narrow whitelist, land that version, and then relax it with dedicated testing and review. Was that what you had in mind? Or something else?

2592

Yes, I do.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2579

I dumped all opcodes of the vmv uses that reach this point in the code for llvm-test-suite and SPEC2017. Just to remind: at this point we know that vmv has a single use, and this use is a merge operand in a TA instruction. List of the opcodes:

• PseudoVLUXEI64_V_M1_M1_MASK
• PseudoVLUXEI64_V_M1_MF2_MASK
• PseudoVLSE16_V_M1_MASK
• PseudoVLSE32_V_M1_MASK
• PseudoVLSE32_V_MF2_MASK
• PseudoVFMADD_VF64_M1

So, I think we should add basic arithmetic and load instructions to the whitelist. However, it won't be so narrow as @reames suggests.

2592

OK, thanks for your reply. It'll be done in the next patch.

[asi-sc]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2579

OK, I'll add only load instructions, otherwise the list is too big.

[asi-sc]

Add a whitelist for merge operands, remove use-walk support

[asi-sc]

A gentle ping

[asi-sc]

Ping

[reames]

I spent some time this morning creating a minimal version of this patch. This change is still too complicated, and I'm unconvinced of it's correctness. Please see https://reviews.llvm.org/D137856.

While doing this, I realize this change is definitely incorrect. Consider the following test case:
setvli x1, 5, <fixed lmul, flags>
vmv.v.i v8, -1
setvli x1, 1, <fixed lmul, flags>
vle8 v8, (a5) // memory contains an -1 vector
setvli x1, 5, <fixed lmul, flags>
vmseq v9, v8, -1

In this case, vle8 stands in for any instruction with a merge operand. The fact it's a load is not meant to be important.

The required semantics of this program is to produce a mask with five ones - regardless of the TA/TU status of the vle8. TA allows either the original value or -1, and in this case, both choices result in the same result.

However, this patch would produce the following:
setvli x1, 1, <fixed lmul, flags>
vmv.v.i v8, -1
setvli x1, 1, <fixed lmul, flags>
vle8 v8, (a5) // memory contains an -1 vector
setvli x1, 5, <fixed lmul, flags>
vmseq v9, v8, -1

In this case, lanes 1 through 4 (inclusive) are undefined, and may result in a mask without those lanes set. As such, the transform is unsound as currently implemented.

[asi-sc]

In D130895#3922106, @reames wrote:

I spent some time this morning creating a minimal version of this patch. This change is still too complicated, and I'm unconvinced of it's correctness. Please see https://reviews.llvm.org/D137856.

While doing this, I realize this change is definitely incorrect. Consider the following test case:
setvli x1, 5, <fixed lmul, flags>
vmv.v.i v8, -1
setvli x1, 1, <fixed lmul, flags>
vle8 v8, (a5) // memory contains an -1 vector
setvli x1, 5, <fixed lmul, flags>
vmseq v9, v8, -1

In this case, vle8 stands in for any instruction with a merge operand. The fact it's a load is not meant to be important.

The required semantics of this program is to produce a mask with five ones - regardless of the TA/TU status of the vle8. TA allows either the original value or -1, and in this case, both choices result in the same result.

However, this patch would produce the following:
setvli x1, 1, <fixed lmul, flags>
vmv.v.i v8, -1
setvli x1, 1, <fixed lmul, flags>
vle8 v8, (a5) // memory contains an -1 vector
setvli x1, 5, <fixed lmul, flags>
vmseq v9, v8, -1

In this case, lanes 1 through 4 (inclusive) are undefined, and may result in a mask without those lanes set. As such, the transform is unsound as currently implemented.

@reames , thanks for reviewing it so thoroughly! However, the test case you provided doesn't convince me in the incorrectness of this change.
(1) If the instruction with a merge operand (vle) has TU policy, we won't shrink VL and the code remains untouched.
(2) The instruction has TA policy. In this case, I don't think we can rely on the values written to the tail. According to the spec:

The value of all 1s instead of all 0s was chosen for the overwrite value to discourage software developers from depending on the value written.

For me it means "you must never rely on the concrete value written to the tail if TA policy is used". Am I wrong? Do we really expect to see some concrete values in the tail of TA instruction when doing compiler transformations? If so, we should just reject shrinking VL for any merge operands.

[asi-sc]

Ping.

@reames , could you please take a look at my previous comment? If you still think we should proceed with the minimized version you made, will you drive the review process? I don't see any progress there for three weeks.

[reames]

I don't think there's much to say here. My prior point still stands. I find your proposed reading of the specification unconvincing. The optimization as proposed is unsound.

I am not particularly interested in this optimization. Unless you have a strong motivation to pursue this - in which case, please explain why - I'd suggest we abandon this patch and move on with our lives.

[asi-sc]

Thanks for your feedback, Philip. I'll made some experiments with this change at my free time, so not abandoning it right now. However, I mark it as "plan changes" to remove it from review queues.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

 #include "RISCVGenDAGISel.inc"
 
 private:
   bool doPeepholeSExtW(SDNode *Node);
   bool doPeepholeMaskedRVV(SDNode *Node);
   bool doPeepholeMergeVVMFold();
   bool performVMergeToVAdd(SDNode *N);
   bool performCombineVMergeAndVOps(SDNode *N, bool IsTA);
+  SDNode *tryShrinkVLForVMV(SDNode *Node);
 };
 
 namespace RISCV {
 struct VLSEGPseudo {
   uint16_t NF : 4;
   uint16_t Masked : 1;
   uint16_t IsTU : 1;
   uint16_t Strided : 1;

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 }
 
 static unsigned getVecPolicyOpIdx(const SDNode *Node, const MCInstrDesc &MCID) {
   assert(RISCVII::hasVecPolicyOp(MCID.TSFlags));
   (void)MCID;
   return getLastNonGlueOrChainOpIdx(Node);
 }
 
+static unsigned getSEWOpIdx(const SDNode *Node, const MCInstrDesc &MCID) {
+  assert(RISCVII::hasSEWOp(MCID.TSFlags));
+  unsigned SEWOpIdx = getLastNonGlueOrChainOpIdx(Node);
+  if (RISCVII::hasVecPolicyOp(MCID.TSFlags))
+    --SEWOpIdx;
+  return SEWOpIdx;
+}
+
+static unsigned getVLOpIdx(const SDNode *Node, const MCInstrDesc &MCID) {
+  assert(RISCVII::hasVLOp(MCID.TSFlags) && RISCVII::hasSEWOp(MCID.TSFlags));
+  // Instruction with VL operand also has SEW that is right after it.
+  return getSEWOpIdx(Node, MCID) - 1;
+}
+
+static unsigned getMergeOpIdx(const SDNode *Node, const MCInstrDesc &MCID) {
+  assert(RISCVII::hasMergeOp(MCID.TSFlags));
+  (void)MCID;
+  // Merge operand is the first one.
+  return 0;
+}
+
 void RISCVDAGToDAGISel::PreprocessISelDAG() {
   SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
 
   bool MadeChange = false;
   while (Position != CurDAG->allnodes_begin()) {
     SDNode *N = &*--Position;
     if (N->use_empty())
       continue;
case ISD::EXTRACT_SUBVECTOR: {
     ReplaceNode(Node, Extract.getNode());
     return;
   }
   case ISD::SPLAT_VECTOR:
   case RISCVISD::VMV_S_X_VL:
   case RISCVISD::VFMV_S_F_VL:
   case RISCVISD::VMV_V_X_VL:
   case RISCVISD::VFMV_V_F_VL: {
+    // Try to shrink VL for a splat-like move.
+    if (Opcode == RISCVISD::VMV_V_X_VL || Opcode == RISCVISD::VFMV_V_F_VL) {
+      SDNode *UpdatedNode = tryShrinkVLForVMV(Node);
+      if (UpdatedNode != Node) {
+        ReplaceNode(Node, UpdatedNode);
+        return;
+      }
+    }
+
     // Try to match splat of a scalar load to a strided load with stride of x0.
     bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
                         Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
     bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
     if (HasPassthruOperand && !Node->getOperand(0).isUndef())
       break;
     SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
     auto *Ld = dyn_cast<LoadSDNode>(Src);
if (auto *C = dyn_cast<ConstantSDNode>(N)) {
 
     Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT());
     return true;
   }
 
   return false;
 }
 
+static SDValue getVLOperand(const SDNode *Node, const RISCVInstrInfo &TII) {
+  if (!Node->isMachineOpcode())
+    return SDValue();
+  const MCInstrDesc &MCID = TII.get(Node->getMachineOpcode());
+  if (!RISCVII::hasVLOp(MCID.TSFlags))
+    return SDValue();
+  return Node->getOperand(getVLOpIdx(Node, MCID));
+}
+
+static bool isVLMax(SDValue VL) {
+  if (auto *Constant = dyn_cast<ConstantSDNode>(VL))
+    return Constant->getSExtValue() == RISCV::VLMaxSentinel;
+  auto *RegVL = dyn_cast<RegisterSDNode>(VL);
+  return RegVL && RegVL->getReg() == RISCV::X0;
+}
+
+static bool isVLLessThan(SDValue VL1, SDValue VL2) {
+  assert(VL1 && VL2);
+  if (isVLMax(VL1))
+    return false;
+  if (isVLMax(VL2))
+    return true;
+  auto *ConstantVL1 = dyn_cast<ConstantSDNode>(VL1);
+  auto *ConstantVL2 = dyn_cast<ConstantSDNode>(VL2);
+  if (!ConstantVL1 || !ConstantVL2)
+    // Cannot compare reg-reg/constant-reg/reg-constant cases apart from X0
+    // and VLMaxSentinel that are handled above.
+    return false;
+  return ConstantVL1->getSExtValue() < ConstantVL2->getSExtValue();
+}
+
+static bool canReadPastVL(unsigned MachineOpcode, unsigned OpIdx) {
+  const RISCVVPseudosTable::PseudoInfo *RVV =
+      RISCVVPseudosTable::getPseudoInfo(MachineOpcode);
+  if (!RVV)
+    return false;
+  switch (RVV->BaseInstr) {
+  default:
+    break;
+  case RISCV::VRGATHEREI16_VV:
+  case RISCV::VRGATHER_VI:
+  case RISCV::VRGATHER_VV:
+  case RISCV::VRGATHER_VX:
+  case RISCV::VSLIDEDOWN_VI:
+  case RISCV::VSLIDEDOWN_VX:
+    // vs2 is accessed indirectly (e.g. vs2[vs1[i]] for vrgather).
+    if (OpIdx == 1)
+      return true;
+    break;
+  }
+  return false;
+}
+
+static bool isInWhitelistForShrinking(unsigned Opcode) {
+  const RISCVVPseudosTable::PseudoInfo *RVV =
+      RISCVVPseudosTable::getPseudoInfo(Opcode);
+  if (!RVV)
+    return false;
+  switch (RVV->BaseInstr) {
+  default:
+    return false;
+  // FIXME: It's a small list of frequently encountered instruction and can be
+  // extended with arithmetic and some other instructions. Ideally, we want to
+  // get rid of this whitelist at all.
+  case RISCV::VLE16FF_V:
+  case RISCV::VLE16_V:
+  case RISCV::VLE32FF_V:
+  case RISCV::VLE32_V:
+  case RISCV::VLE64FF_V:
+  case RISCV::VLE64_V:
+  case RISCV::VLE8FF_V:
+  case RISCV::VLE8_V:
+  case RISCV::VLUXEI16_V:
+  case RISCV::VLUXEI32_V:
+  case RISCV::VLUXEI64_V:
+  case RISCV::VLUXEI8_V:
+  case RISCV::VLSE16_V:
+  case RISCV::VLSE32_V:
+  case RISCV::VLSE64_V:
+  case RISCV::VLSE8_V:
+  case RISCV::VLOXEI16_V:
+  case RISCV::VLOXEI32_V:
+  case RISCV::VLOXEI64_V:
+  case RISCV::VLOXEI8_V:
+    return true;
+  }
+}
+
+// Checks that the user is not the merge operand of a TU instruction.
+static bool allowsVLShrinking(SDNode::use_iterator UI,
+                              const RISCVInstrInfo &TII) {
+  if (!UI->isMachineOpcode())
+    return false;
+
+  if (canReadPastVL(UI->getMachineOpcode(), UI.getOperandNo()))
+    return false;
+
+  const MCInstrDesc &MCID = TII.get(UI->getMachineOpcode());
+  // Cannot shrink if the user does not have VL operand.
+  if (!RISCVII::hasVLOp(MCID.TSFlags))
+    return false;
+  if (!RISCVII::hasMergeOp(MCID.TSFlags) ||
+      getMergeOpIdx(*UI, MCID) != UI.getOperandNo())
+    return true;
+  if (!RISCVII::hasVecPolicyOp(MCID.TSFlags))
+    // Policy is implicit for instructions without policy. Return false by
+    // default.
+    // FIXME: returning always false disables some of the cases to optimize. We
+    // should check tied operand instead (see RISCVInsertVSETVLI).
+    return false;
+  unsigned PolicyOp = getVecPolicyOpIdx(*UI, MCID);
+  return (UI->getConstantOperandVal(PolicyOp) & RISCVII::TAIL_AGNOSTIC) &&
+         isInWhitelistForShrinking(UI->getMachineOpcode());
+}
+
+static unsigned getSEWLMULRatio(SDNode *Node, const RISCVInstrInfo &TII) {
+  assert(Node->isMachineOpcode());
+  const MCInstrDesc &MCID = TII.get(Node->getMachineOpcode());
+  assert(RISCVII::hasVLOp(MCID.TSFlags));
+  assert(RISCVII::hasSEWOp(MCID.TSFlags));
+  unsigned Log2SEW = Node->getConstantOperandVal(getSEWOpIdx(Node, MCID));
+  unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
+  RISCVII::VLMUL LMUL = RISCVII::getLMul(MCID.TSFlags);
+  return RISCVVType::getSEWLMULRatio(SEW, LMUL);
+}
+
+// Analyzes users of a splat-like VMV/VFMV instruction and chooses the minimal
+// possible VL.
+SDNode *RISCVDAGToDAGISel::tryShrinkVLForVMV(SDNode *Node) {
+  // Leave VMV/VFMV with TU unmodified.
+  if (!Node->getOperand(0).isUndef())
+    return Node;
+  // FIXME: this can be profitable for the moves with multiple uses as well.
+  if (!Node->hasOneUse())
+    return Node;
+
+  const RISCVInstrInfo &TII = *Subtarget->getInstrInfo();
+  auto UI = Node->use_begin();
+  if (!allowsVLShrinking(UI, TII))
+    return Node;
+
+  MVT VT = Node->getSimpleValueType(0);
+  unsigned SEW = VT.getScalarSizeInBits();
+  RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+  unsigned SEWLMULRatio = RISCVVType::getSEWLMULRatio(SEW, LMUL);
+  if (SEWLMULRatio != getSEWLMULRatio(*UI, TII))
+    return Node;
+
+  SDValue VL = getVLOperand(*UI, TII);
+  SDValue OldVL = Node->getOperand(Node->getNumOperands() - 1);
+  if (!VL || !isVLLessThan(VL, OldVL))
+    return Node;
+
+  // MergeOp, Src, VL.
+  SmallVector<SDValue, 3> Ops(Node->op_begin(), Node->op_end());
+  Ops[Node->getNumOperands() - 1] = VL;
+  return CurDAG->UpdateNodeOperands(Node, Ops);
+}
+
 // Try to remove sext.w if the input is a W instruction or can be made into
 // a W instruction cheaply.
 bool RISCVDAGToDAGISel::doPeepholeSExtW(SDNode *N) {
   // Look for the sext.w pattern, addiw rd, rs1, 0.
   if (N->getMachineOpcode() != RISCV::ADDIW ||
       !isNullConstant(N->getOperand(1)))
     return false;
 
bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(SDNode *N) {
 
   // Retrieve the tail policy operand index, if any.
   Optional<unsigned> TailPolicyOpIdx;
   const RISCVInstrInfo &TII = *Subtarget->getInstrInfo();
   const MCInstrDesc &MaskedMCID = TII.get(N->getMachineOpcode());
 
   bool IsTA = true;
   if (RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags)) {
     TailPolicyOpIdx = getVecPolicyOpIdx(N, MaskedMCID);
     if (!(N->getConstantOperandVal(*TailPolicyOpIdx) &
           RISCVII::TAIL_AGNOSTIC)) {
       // Keep the true-masked instruction when there is no unmasked TU
       // instruction
       if (I->UnmaskedTUPseudo == I->MaskedPseudo && !N->getOperand(0).isUndef())
         return false;
       // We can't use TA if the tie-operand is not IMPLICIT_DEF
       if (!N->getOperand(0).isUndef())

llvm/test/CodeGen/RISCV/rvv/pr55615.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
 
+; Requires use-walk support
 define void @vector_splat_toggle_const_eq(double* %a, double* %b) {
 ; CHECK-LABEL: vector_splat_toggle_const_eq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a0)
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %addr = bitcast double* %a to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 4)
   %addr2 = bitcast double* %b to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr2, i64 4)
   ret void
 }
 
+; Requires use-walk support
 define void @vector_splat_toggle_const_ne(double* %a, double* %b) {
 ; CHECK-LABEL: vector_splat_toggle_const_ne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a0)
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %addr = bitcast double* %a to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 2)
   %addr2 = bitcast double* %b to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr2, i64 4)
   ret void
 }
 
+; Requires use-walk support
 define void @vector_splat_toggle_nonconst_eq(double* %a, double* %b, i64 %n) {
 ; CHECK-LABEL: vector_splat_toggle_nonconst_eq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, a2, e64, m1, ta, mu
 ; CHECK-NEXT:    vsetvli a3, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a0)
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %vl = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 3, i64 0)
   %addr = bitcast double* %a to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 %vl)
   %addr2 = bitcast double* %b to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr2, i64 %vl)
   ret void
 }
 
+; Negative test
 define void @vector_splat_toggle_nonconst_ne(double* %a, double* %b, i64 %n1, i64 %n2) {
 ; CHECK-LABEL: vector_splat_toggle_nonconst_ne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, a2, e64, m1, ta, mu
 ; CHECK-NEXT:    vsetvli a3, a3, e64, m1, ta, mu
 ; CHECK-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a0)
 ; CHECK-NEXT:    vsetvli zero, a3, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %vl1 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n1, i64 3, i64 0)
   %vl2 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n2, i64 3, i64 0)
   %addr = bitcast double* %a to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 %vl1)
   %addr2 = bitcast double* %b to <vscale x 1 x double>*
   tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr2, i64 %vl2)
   ret void
 }
 
+; Requires use-walk support
 define <vscale x 1 x double> @vector_splat_toggle_mergeop_inst(double* %a, <vscale x 1 x double> %b, <vscale x 1 x double> %maskedoff, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: vector_splat_toggle_mergeop_inst:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, %hi(.LCPI4_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v10, (a1), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, mu
%res = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(
     <vscale x 1 x double> %b,
     <vscale x 1 x double> %val,
     <vscale x 1 x i1> %mask,
     i64 4, i64 1)
 
   ret <vscale x 1 x double> %res
 }
 
+; Requires use-walk support
 define <vscale x 1 x double> @vector_splat_toggle_mergeop_TA(double* %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: vector_splat_toggle_mergeop_TA:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, %hi(.LCPI5_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI5_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v10, (a1), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, mu
%res = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(
     <vscale x 1 x double> %b,
     <vscale x 1 x double> %c,
     <vscale x 1 x i1> %mask,
     i64 4, i64 1)
 
   ret <vscale x 1 x double> %res
 }
 
+; Negative test
 define <vscale x 1 x double> @vector_splat_toggle_mergeop_TU(double* %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: vector_splat_toggle_mergeop_TU:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, %hi(.LCPI6_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI6_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v10, (a1), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, tu, mu
%res = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(
     <vscale x 1 x double> %b,
     <vscale x 1 x double> %c,
     <vscale x 1 x i1> %mask,
     i64 4, i64 0)
 
   ret <vscale x 1 x double> %res
 }
 
+; Negative test
 define <vscale x 1 x double> @vector_splat_toggle_unknown_vl(double* %a, <vscale x 1 x double> %maskedoff, <vscale x 1 x double> %b, <vscale x 1 x i1> %mask, i64 %avl) {
 ; CHECK-LABEL: vector_splat_toggle_unknown_vl:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a2, %hi(.LCPI7_0)
 ; CHECK-NEXT:    addi a2, a2, %lo(.LCPI7_0)
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v10, (a2), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, mu
%res = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(
     <vscale x 1 x double> %b,
     <vscale x 1 x double> %val,
     <vscale x 1 x i1> %mask,
     i64 4, i64 1)
 
   ret <vscale x 1 x double> %res
 }
 
+; Requires use-walk support
 define <vscale x 1 x double> @vector_splat_toggle_notmerge_TU(double* %a, <vscale x 1 x double> %maskedoff, <vscale x 1 x double> %c, <vscale x 1 x i1> %mask) {
 ; CHECK-LABEL: vector_splat_toggle_notmerge_TU:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, %hi(.LCPI8_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI8_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v10, (a1), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, tu, mu
%res = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(
     <vscale x 1 x double> %c,
     <vscale x 1 x double> %val,
     <vscale x 1 x i1> %mask,
     i64 4, i64 0)
 
   ret <vscale x 1 x double> %res
 }
 
+; Negative test
 define <vscale x 1 x double> @check_vslidedown_vx(<vscale x 1 x double> %maskedoff, i64 %b) {
 ; CHECK-LABEL: check_vslidedown_vx:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a1, %hi(.LCPI9_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI9_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v9, (a1), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
 ; CHECK-NEXT:    vslidedown.vx v8, v9, a0
 ; CHECK-NEXT:    ret
 entry:
   %val = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double> undef, double 1.000000e+00, i64 8)
   %res = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
     <vscale x 1 x double> %maskedoff,
     <vscale x 1 x double> %val,
     i64 %b, i64 4, i64 1)
   ret <vscale x 1 x double> %res
 }
 
+; Negative test
 define <vscale x 1 x double> @check_vslidedown_vi(<vscale x 1 x double> %maskedoff) {
 ; CHECK-LABEL: check_vslidedown_vi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a0, %hi(.LCPI10_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI10_0)
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vlse64.v v9, (a0), zero
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, tu, ma
 ; CHECK-NEXT:    vslidedown.vi v8, v9, 9
 ; CHECK-NEXT:    ret
 entry:
   %val = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(<vscale x 1 x double> undef, double 1.000000e+00, i64 8)
   %res = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
     <vscale x 1 x double> %maskedoff,
     <vscale x 1 x double> %val,
     i64 9, i64 4, i64 0)
   ret <vscale x 1 x double> %res
 }
 
+; Negative test
 define <vscale x 1 x i64> @check_vrgather_vv(<vscale x 1 x i64> %a, <vscale x 1 x i64> %maskedoff) {
 ; CHECK-LABEL: check_vrgather_vv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v10, 1
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m1, tu, ma
 ; CHECK-NEXT:    vrgather.vv v9, v10, v8
 ; CHECK-NEXT:    vmv1r.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %val = tail call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(<vscale x 1 x i64> undef, i64 1, i64 8)
   %res = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(
     <vscale x 1 x i64> %maskedoff,
     <vscale x 1 x i64> %val,
     <vscale x 1 x i64> %a,
     i64 4)
   ret <vscale x 1 x i64> %res
 }
 
 define <vscale x 1 x i64> @check_vrgather_vv2(<vscale x 1 x i64> %a, <vscale x 1 x i64> %maskedoff) {
 ; CHECK-LABEL: check_vrgather_vv2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 8, e64, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v10, 1
-; CHECK-NEXT:    vsetivli zero, 4, e64, m1, tu, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
 ; CHECK-NEXT:    vrgather.vv v9, v8, v10
 ; CHECK-NEXT:    vmv1r.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %val = tail call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(<vscale x 1 x i64> undef, i64 1, i64 8)
   %res = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(
     <vscale x 1 x i64> %maskedoff,
     <vscale x 1 x i64> %a,
     <vscale x 1 x i64> %val,
     i64 4)
   ret <vscale x 1 x i64> %res
 }
 
+; Negative test
 define <vscale x 8 x i32> @change_SEW_single(<vscale x 8 x i32> %a) {
 ; CHECK-LABEL: change_SEW_single:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m4, ta, ma
 ; CHECK-NEXT:    vmv.v.i v12, 1
 ; CHECK-NEXT:    vsetivli zero, 2, e32, m4, tu, ma
 ; CHECK-NEXT:    vadd.vv v8, v12, v8
 ; CHECK-NEXT:    ret
   %b = tail call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(<vscale x 4 x i64> undef, i64 1, i64 4)
   %bc = bitcast <vscale x 4 x i64> %b to <vscale x 8 x i32>
   %res = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %bc, <vscale x 8 x i32> %a, i64 2)
   ret <vscale x 8 x i32> %res
 }
 
+; Negative test
 define <vscale x 4 x i64> @change_SEW_multiple( <vscale x 4 x i64> %a, <vscale x 8 x i32> %b) {
 ; CHECK-LABEL: change_SEW_multiple:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m4, ta, ma
 ; CHECK-NEXT:    vmv.v.i v16, 1
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m4, tu, ma
 ; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    vsetivli zero, 2, e32, m4, tu, ma

llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfeq.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmand.mm v0, v8, v9
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfeq.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmand.mm v0, v9, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfne.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmor.mm v0, v8, v9
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfne.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmor.mm v0, v9, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT:    vmfeq.vf v12, v10, fa0, v0.t
-; CHECK-NEXT:    vmfeq.vv v10, v8, v8, v0.t
-; CHECK-NEXT:    vmand.mm v0, v10, v12
+; CHECK-NEXT:    vfmv.v.f v10, fa0
+; CHECK-NEXT:    vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v8, v10, fa0, v0.t
+; CHECK-NEXT:    vmand.mm v0, v12, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT:    vmfeq.vf v12, v10, fa0, v0.t
-; CHECK-NEXT:    vmfeq.vv v10, v8, v8, v0.t
-; CHECK-NEXT:    vmand.mm v0, v12, v10
+; CHECK-NEXT:    vfmv.v.f v10, fa0
+; CHECK-NEXT:    vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v8, v10, fa0, v0.t
+; CHECK-NEXT:    vmand.mm v0, v8, v12
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT:    vmfne.vf v12, v10, fa0, v0.t
-; CHECK-NEXT:    vmfne.vv v10, v8, v8, v0.t
-; CHECK-NEXT:    vmor.mm v0, v10, v12
+; CHECK-NEXT:    vfmv.v.f v10, fa0
+; CHECK-NEXT:    vmfne.vv v12, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v8, v10, fa0, v0.t
+; CHECK-NEXT:    vmor.mm v0, v12, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v10, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT:    vmfne.vf v12, v10, fa0, v0.t
-; CHECK-NEXT:    vmfne.vv v10, v8, v8, v0.t
-; CHECK-NEXT:    vmor.mm v0, v12, v10
+; CHECK-NEXT:    vfmv.v.f v10, fa0
+; CHECK-NEXT:    vmfne.vv v12, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v8, v10, fa0, v0.t
+; CHECK-NEXT:    vmor.mm v0, v8, v12
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
   %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 declare <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half>, <vscale x 64 x half>, metadata, <vscale x 64 x i1>, i32)

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_nxv1f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfeq.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmand.mm v0, v8, v9
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfeq.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmand.mm v0, v9, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_nxv1f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfne.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmor.mm v0, v8, v9
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vmfne.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v9, v9, fa0, v0.t
 ; CHECK-NEXT:    vmor.mm v0, v9, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_nxv8f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT:    vfmv.v.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT:    vmfeq.vf v24, v16, fa0, v0.t
-; CHECK-NEXT:    vmfeq.vv v16, v8, v8, v0.t
-; CHECK-NEXT:    vmand.mm v0, v16, v24
+; CHECK-NEXT:    vfmv.v.f v16, fa0
+; CHECK-NEXT:    vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v8, v16, fa0, v0.t
+; CHECK-NEXT:    vmand.mm v0, v24, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT:    vfmv.v.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT:    vmfeq.vf v24, v16, fa0, v0.t
-; CHECK-NEXT:    vmfeq.vv v16, v8, v8, v0.t
-; CHECK-NEXT:    vmand.mm v0, v24, v16
+; CHECK-NEXT:    vfmv.v.f v16, fa0
+; CHECK-NEXT:    vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT:    vmfeq.vf v8, v16, fa0, v0.t
+; CHECK-NEXT:    vmand.mm v0, v8, v24
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_nxv8f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT:    vfmv.v.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT:    vmfne.vf v24, v16, fa0, v0.t
-; CHECK-NEXT:    vmfne.vv v16, v8, v8, v0.t
-; CHECK-NEXT:    vmor.mm v0, v16, v24
+; CHECK-NEXT:    vfmv.v.f v16, fa0
+; CHECK-NEXT:    vmfne.vv v24, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v8, v16, fa0, v0.t
+; CHECK-NEXT:    vmor.mm v0, v24, v8
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT:    vfmv.v.f v16, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT:    vmfne.vf v24, v16, fa0, v0.t
-; CHECK-NEXT:    vmfne.vv v16, v8, v8, v0.t
-; CHECK-NEXT:    vmor.mm v0, v24, v16
+; CHECK-NEXT:    vfmv.v.f v16, fa0
+; CHECK-NEXT:    vmfne.vv v24, v8, v8, v0.t
+; CHECK-NEXT:    vmfne.vf v8, v16, fa0, v0.t
+; CHECK-NEXT:    vmor.mm v0, v8, v24
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
   %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 declare <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double>, <vscale x 32 x double>, metadata, <vscale x 32 x i1>, i32)

llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @icmp_uge_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_uge_vx_nxv1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsleu.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
   %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, metadata !"sge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @icmp_sge_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sge_vx_nxv1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
   %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, metadata !"sge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
; CHECK-NEXT:    ret
   %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @icmp_sle_vx_swap_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sle_vx_swap_nxv1i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
   %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_uge_vx_nxv8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsleu.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, metadata !"sge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sge_vx_nxv8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, metadata !"sge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
; CHECK-NEXT:    ret
   %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, metadata !"sle", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @icmp_sle_vx_swap_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sle_vx_swap_nxv8i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
   %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i8(<vscale x 8 x i8> %vb, <vscale x 8 x i8> %va, metadata !"sle", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @icmp_uge_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_uge_vx_nxv1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsleu.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, metadata !"sge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @icmp_sge_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sge_vx_nxv1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, metadata !"sge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
; CHECK-NEXT:    ret
   %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 
 define <vscale x 1 x i1> @icmp_sle_vx_swap_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sle_vx_swap_nxv1i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v9, a0
 ; CHECK-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
   %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i32(<vscale x 1 x i32> %vb, <vscale x 1 x i32> %va, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_uge_vx_nxv8i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
-; CHECK-NEXT:    vmv.v.x v16, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
 ; CHECK-NEXT:    vmsleu.vv v12, v16, v8, v0.t
 ; CHECK-NEXT:    vmv1r.v v0, v12
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }

 ; CHECK-NEXT:    ret
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, metadata !"sge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sge_vx_nxv8i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
-; CHECK-NEXT:    vmv.v.x v16, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
 ; CHECK-NEXT:    vmsle.vv v12, v16, v8, v0.t
 ; CHECK-NEXT:    vmv1r.v v0, v12
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, metadata !"sge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
; CHECK-NEXT:    ret
   %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, metadata !"sle", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }
 
 define <vscale x 8 x i1> @icmp_sle_vx_swap_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: icmp_sle_vx_swap_nxv8i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
-; CHECK-NEXT:    vmv.v.x v16, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT:    vmv.v.x v16, a0
 ; CHECK-NEXT:    vmsle.vv v12, v16, v8, v0.t
 ; CHECK-NEXT:    vmv1r.v v0, v12
 ; CHECK-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
   %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i32(<vscale x 8 x i32> %vb, <vscale x 8 x i32> %va, metadata !"sle", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }

 ; RV32-NEXT:    vlse64.v v9, (a0), zero
 ; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; RV32-NEXT:    vmsleu.vv v0, v9, v8, v0.t
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_uge_vx_nxv1i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; RV64-NEXT:    vmv.v.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT:    vmv.v.x v9, a0
 ; RV64-NEXT:    vmsleu.vv v0, v9, v8, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; RV32-NEXT:    vlse64.v v9, (a0), zero
 ; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; RV32-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_sge_vx_nxv1i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; RV64-NEXT:    vmv.v.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT:    vmv.v.x v9, a0
 ; RV64-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"sge", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; RV32-NEXT:    vlse64.v v9, (a0), zero
 ; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; RV32-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_sle_vx_swap_nxv1i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; RV64-NEXT:    vmv.v.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT:    vmv.v.x v9, a0
 ; RV64-NEXT:    vmsle.vv v0, v9, v8, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
   %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %vb, <vscale x 1 x i64> %va, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i1> %v
 }
 

 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
 ; RV32-NEXT:    vmsleu.vv v16, v24, v8, v0.t
 ; RV32-NEXT:    vmv1r.v v0, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_uge_vx_nxv8i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
-; RV64-NEXT:    vmv.v.x v24, a0
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT:    vmv.v.x v24, a0
 ; RV64-NEXT:    vmsleu.vv v16, v24, v8, v0.t
 ; RV64-NEXT:    vmv1r.v v0, v16
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }

 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
 ; RV32-NEXT:    vmsle.vv v16, v24, v8, v0.t
 ; RV32-NEXT:    vmv1r.v v0, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_sge_vx_nxv8i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
-; RV64-NEXT:    vmv.v.x v24, a0
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT:    vmv.v.x v24, a0
 ; RV64-NEXT:    vmsle.vv v16, v24, v8, v0.t
 ; RV64-NEXT:    vmv1r.v v0, v16
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, metadata !"sge", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }

 ; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
 ; RV32-NEXT:    vmsle.vv v16, v24, v8, v0.t
 ; RV32-NEXT:    vmv1r.v v0, v16
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: icmp_sle_vx_swap_nxv8i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
-; RV64-NEXT:    vmv.v.x v24, a0
 ; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT:    vmv.v.x v24, a0
 ; RV64-NEXT:    vmsle.vv v16, v24, v8, v0.t
 ; RV64-NEXT:    vmv1r.v v0, v16
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i1> @llvm.vp.icmp.nxv8i64(<vscale x 8 x i64> %vb, <vscale x 8 x i64> %va, metadata !"sle", <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i1> %v
 }

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 3
 ; CHECK-NEXT:    slli a1, a0, 1
 ; CHECK-NEXT:    add a1, a1, a0
 ; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
 ; CHECK-NEXT:    vfmv.v.f v9, ft0
-; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vx v8, v9, a1
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.nxv6f16(half, <vscale x 6 x half>)
 
 define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv6f16:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    add a1, a0, a0
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v10, ft0
-; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma
-; CHECK-NEXT:    vslideup.vx v9, v10, a0
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.s.f v10, fa0
+; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT:    vfmv.v.f v11, ft0
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma
+; CHECK-NEXT:    vslideup.vx v9, v11, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vfredosum.vs v8, v8, v10
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
   ret half %red
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 3
 ; CHECK-NEXT:    slli a1, a0, 1
 ; CHECK-NEXT:    add a1, a1, a0
 ; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
 ; CHECK-NEXT:    vfmv.v.f v9, ft0
-; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vx v8, v9, a1
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v9
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv6f16:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT:    vfmv.s.f v10, fa0
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 2
 ; CHECK-NEXT:    add a1, a0, a0
 ; CHECK-NEXT:    fmv.h.x ft0, zero
 ; CHECK-NEXT:    fneg.h ft0, ft0
-; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v10, ft0
-; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma
-; CHECK-NEXT:    vslideup.vx v9, v10, a0
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.s.f v10, fa0
+; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT:    vfmv.v.f v11, ft0
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma
+; CHECK-NEXT:    vslideup.vx v9, v11, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
 ; CHECK-NEXT:    vfredusum.vs v8, v8, v10
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
   ret half %red
 }
 

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix NOSUBREG
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -riscv-enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG
 
 ; This test checks that vrgatherei16 instructions are correctly
 ; register-allocated. The LMUL=1 destination register groups may not overlap
 ; with the EMUL=2 source vector register groups.
 
 ; FIXME: enabling subregister liveness results in incorrect register
 ; allocation!
 
 define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) {
 ; NOSUBREG-LABEL: foo:
 ; NOSUBREG:       # %bb.0: # %loopIR.preheader.i.i
 ; NOSUBREG-NEXT:    # kill: def $v10 killed $v10 def $v10m2
-; NOSUBREG-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; NOSUBREG-NEXT:    vsetivli zero, 4, e16, m2, ta, ma
 ; NOSUBREG-NEXT:    vmv.v.i v14, 0
-; NOSUBREG-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
+; NOSUBREG-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
 ; NOSUBREG-NEXT:    vmv.v.i v9, 0
 ; NOSUBREG-NEXT:    vsetivli zero, 4, e8, m1, tu, ma
 ; NOSUBREG-NEXT:    vmv1r.v v8, v9
 ; NOSUBREG-NEXT:    vrgatherei16.vv v8, v9, v14
 ; NOSUBREG-NEXT:  .LBB0_1: # %loopIR3.i.i
 ; NOSUBREG-NEXT:    # =>This Inner Loop Header: Depth=1
 ; NOSUBREG-NEXT:    vl1r.v v9, (zero)
 ; NOSUBREG-NEXT:    vsetivli zero, 4, e8, m1, tu, ma
 ; NOSUBREG-NEXT:    vmv1r.v v13, v12
 ; NOSUBREG-NEXT:    vrgatherei16.vv v13, v9, v10
 ; NOSUBREG-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
 ; NOSUBREG-NEXT:    vand.vv v9, v8, v13
 ; NOSUBREG-NEXT:    vs1r.v v9, (zero)
 ; NOSUBREG-NEXT:    j .LBB0_1
 ;
 ; SUBREG-LABEL: foo:
 ; SUBREG:       # %bb.0: # %loopIR.preheader.i.i
-; SUBREG-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; SUBREG-NEXT:    vsetivli zero, 4, e16, m2, ta, ma
 ; SUBREG-NEXT:    vmv.v.i v14, 0
-; SUBREG-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
+; SUBREG-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
 ; SUBREG-NEXT:    vmv.v.i v9, 0
 ; SUBREG-NEXT:    vsetivli zero, 4, e8, m1, tu, ma
 ; SUBREG-NEXT:    vmv1r.v v8, v9
 ; SUBREG-NEXT:    vrgatherei16.vv v8, v9, v14
 ; SUBREG-NEXT:  .LBB0_1: # %loopIR3.i.i
 ; SUBREG-NEXT:    # =>This Inner Loop Header: Depth=1
 ; SUBREG-NEXT:    vl1r.v v9, (zero)
 ; SUBREG-NEXT:    vsetivli zero, 4, e8, m1, tu, ma

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

 define void @vector_init_vsetvli_N(i64 %N, double* %c) {
 ; CHECK-LABEL: vector_init_vsetvli_N:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a2, a0, e64, m1, ta, mu
 ; CHECK-NEXT:    blez a0, .LBB13_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    slli a4, a2, 3
-; CHECK-NEXT:    vsetvli a5, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:  .LBB13_2: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    add a3, a3, a2
 ; CHECK-NEXT:    add a1, a1, a4
 ; CHECK-NEXT:    blt a3, a0, .LBB13_2

 
 ; Same as above, but VL is a hard coded constant (in the preheader)
 define void @vector_init_vsetvli_fv(i64 %N, double* %c) {
 ; CHECK-LABEL: vector_init_vsetvli_fv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li a2, 0
 ; CHECK-NEXT:    vsetivli a3, 4, e64, m1, ta, mu
 ; CHECK-NEXT:    slli a4, a3, 3
-; CHECK-NEXT:    vsetvli a5, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:  .LBB14_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    add a2, a2, a3
 ; CHECK-NEXT:    add a1, a1, a4
 ; CHECK-NEXT:    blt a2, a0, .LBB14_1
 ; CHECK-NEXT:  # %bb.2: # %for.end
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.riscv.vsetvli(i64 4, i64 3, i64 0)

 }
 
 ; Same as above, but result of vsetvli in preheader isn't used, and
 ; constant is repeated in loop
 define void @vector_init_vsetvli_fv2(i64 %N, double* %c) {
 ; CHECK-LABEL: vector_init_vsetvli_fv2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li a2, 0
-; CHECK-NEXT:    vsetvli a3, zero, e64, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, mu
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:  .LBB15_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    addi a2, a2, 4
 ; CHECK-NEXT:    addi a1, a1, 32
 ; CHECK-NEXT:    blt a2, a0, .LBB15_1
 ; CHECK-NEXT:  # %bb.2: # %for.end
 ; CHECK-NEXT:    ret
 entry:
   tail call i64 @llvm.riscv.vsetvli(i64 4, i64 3, i64 0)

 }
 
 ; Same as above, but AVL is only specified on the store intrinsic
 ; This case will require some form of hoisting or PRE
 define void @vector_init_vsetvli_fv3(i64 %N, double* %c) {
 ; CHECK-LABEL: vector_init_vsetvli_fv3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li a2, 0
-; CHECK-NEXT:    vsetvli a3, zero, e64, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:  .LBB16_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vsetivli zero, 4, e64, m1, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    addi a2, a2, 4
 ; CHECK-NEXT:    addi a1, a1, 32
 ; CHECK-NEXT:    blt a2, a0, .LBB16_1
 ; CHECK-NEXT:  # %bb.2: # %for.end
 ; CHECK-NEXT:    ret
 entry:
   br label %for.body

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

 
 
 @gdouble = external global double
 
 define <vscale x 1 x double> @test16(i64 %avl, double %a, <vscale x 1 x double> %b) nounwind {
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a0, a0, e64, mf2, ta, mu
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT:    vfmv.v.f v9, fa0
 ; CHECK-NEXT:    vfadd.vv v8, v9, v8
 ; CHECK-NEXT:    ret
 entry:
   %vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)
 
   %head = insertelement <vscale x 1 x double> poison, double %a, i32 0
   %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
   %f2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(