[RISCV] Lower BUILD_VECTOR to RISCVISD::VID_VL if it is floating-point type.

[reames]

High level question - why approach this as checking to see if the float is representable as an integer instead of just using the bit-pattern of the float? Using the bit-pattern would seem to match the vid sequence with a large base offset. If so, we could either emit the base as a constant, or leverage the float to int conversion if within the sequence is in the representable range.

[craig.topper]

In D133688#3784547, @reames wrote:

High level question - why approach this as checking to see if the float is representable as an integer instead of just using the bit-pattern of the float? Using the bit-pattern would seem to match the vid sequence with a large base offset. If so, we could either emit the base as a constant, or leverage the float to int conversion if within the sequence is in the representable range.

I didn't follow this. Doesn't normalization of the mantissa make the exponents varied so they wouldn't be linear?

llvm/test/CodeGen/RISCV/rvv/vle_vid-vfwcvt.ll

1 ↗

(On Diff #459430)

The title of this test says vfwcvt, but there are no vfwcvt instructions generated.

[reames]

In D133688#3784585, @craig.topper wrote:

In D133688#3784547, @reames wrote:

High level question - why approach this as checking to see if the float is representable as an integer instead of just using the bit-pattern of the float? Using the bit-pattern would seem to match the vid sequence with a large base offset. If so, we could either emit the base as a constant, or leverage the float to int conversion if within the sequence is in the representable range.

I didn't follow this. Doesn't normalization of the mantissa make the exponents varied so they wouldn't be linear?

It might be this is the answer to my question. Is there a range of float values where the step is non-constant as integer, but constant as a float?

1.0 = 0x3f800000
2.0 = 0x40000000
3.0 = 0x40400000

The delta here is 0x00400000. At least in this range, using a step of 0x00400000 and base of 0x3f800000 would seem to give the right result.

[craig.topper]

In D133688#3784603, @reames wrote:

In D133688#3784585, @craig.topper wrote:

In D133688#3784547, @reames wrote:

High level question - why approach this as checking to see if the float is representable as an integer instead of just using the bit-pattern of the float? Using the bit-pattern would seem to match the vid sequence with a large base offset. If so, we could either emit the base as a constant, or leverage the float to int conversion if within the sequence is in the representable range.

I didn't follow this. Doesn't normalization of the mantissa make the exponents varied so they wouldn't be linear?

It might be this is the answer to my question. Is there a range of float values where the step is non-constant as integer, but constant as a float?

1.0 = 0x3f800000
2.0 = 0x40000000
3.0 = 0x40400000

The delta here is 0x00400000. At least in this range, using a step of 0x00400000 and base of 0x3f800000 would seem to give the right result.

Doesn't the pattern break when you hit 5.0
4.0 = 0x40800000
5.0 = 0x40a00000 <- this is only 0x00200000 away from 4.0

[reames]

In D133688#3784618, @craig.topper wrote:

In D133688#3784603, @reames wrote:

In D133688#3784585, @craig.topper wrote:

In D133688#3784547, @reames wrote:

High level question - why approach this as checking to see if the float is representable as an integer instead of just using the bit-pattern of the float? Using the bit-pattern would seem to match the vid sequence with a large base offset. If so, we could either emit the base as a constant, or leverage the float to int conversion if within the sequence is in the representable range.

I didn't follow this. Doesn't normalization of the mantissa make the exponents varied so they wouldn't be linear?

It might be this is the answer to my question. Is there a range of float values where the step is non-constant as integer, but constant as a float?

1.0 = 0x3f800000
2.0 = 0x40000000
3.0 = 0x40400000

The delta here is 0x00400000. At least in this range, using a step of 0x00400000 and base of 0x3f800000 would seem to give the right result.

Doesn't the pattern break when you hit 5.0
4.0 = 0x40800000
5.0 = 0x40a00000 <- this is only 0x00200000 away from 4.0

It does. Consider my question answered. :)

[craig.topper]

Does this create -0.0 when it is supposed to?

[HanKuanChen]

In D133688#3784653, @craig.topper wrote:

Does this create -0.0 when it is supposed to?

No. If input contain -0.0, we should skip it.

[HanKuanChen]

1. Rename vle_vid-vfwcvt.ll to vle_vid-vfcvt.ll.

2. isPosZero() is used to check +0.0. Use !isNegative() instead.

[HanKuanChen]

In D133688#3784653, @craig.topper wrote:

Does this create -0.0 when it is supposed to?

-0.0 will be detected by IsExact.

[craig.topper]

In D133688#3785471, @HanKuanChen wrote:

In D133688#3784653, @craig.topper wrote:

Does this create -0.0 when it is supposed to?

-0.0 will be detected by IsExact.

Can we have a test case for that?

[HanKuanChen]

Add tests for -0.0 behavior.

[craig.topper]

LGTM

[HanKuanChen]

1. Fix Invalid rounding mode found.
2. Refactor and add getExactInteger.

[craig.topper]

Moving to Request Changes to cancel approval. Need to re-review.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 }
 
 struct VIDSequence {
   int64_t StepNumerator;
   unsigned StepDenominator;
   int64_t Addend;
 };
 
+static Optional<uint64_t> getExactInteger(const APFloat &APF,
+                                          uint32_t BitWidth) {
+  APSInt ValInt(BitWidth, !APF.isNegative());
+  // We use an arbitrary rounding mode here. If a floating-point is an exact
+  // integer (e.g., 1.0), the rounding mode does not affect the output value. If
+  // the rounding mode changes the output value, then it is not an exact
+  // integer.
+  RoundingMode ArbitraryRM = RoundingMode::TowardZero;
+  bool IsExact;
+  // If it is out of signed integer range, it will return an invalid operation.
+  // If it is not an exact integer, IsExact is false.
+  if ((APF.convertToInteger(ValInt, ArbitraryRM, &IsExact) ==
+       APFloatBase::opInvalidOp) ||
+      !IsExact)
+    return None;
+  return ValInt.extractBitsAsZExtValue(BitWidth, 0);
+}
+
 // Try to match an arithmetic-sequence BUILD_VECTOR [X,X+S,X+2*S,...,X+(N-1)*S]
 // to the (non-zero) step S and start value X. This can be then lowered as the
 // RVV sequence (VID * S) + X, for example.
 // The step S is represented as an integer numerator divided by a positive
 // denominator. Note that the implementation currently only identifies
 // sequences in which either the numerator is +/- 1 or the denominator is 1. It
 // cannot detect 2/3, for example.
 // Note that this method will also match potentially unappealing index
 // sequences, like <i32 0, i32 50939494>, however it is left to the caller to
 // determine whether this is worth generating code for.
 static Optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
   unsigned NumElts = Op.getNumOperands();
   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unexpected BUILD_VECTOR");
-  if (!Op.getValueType().isInteger())
-    return None;
+  bool IsInteger = Op.getValueType().isInteger();
 
   Optional<unsigned> SeqStepDenom;
   Optional<int64_t> SeqStepNum, SeqAddend;
   Optional<std::pair<uint64_t, unsigned>> PrevElt;
   unsigned EltSizeInBits = Op.getValueType().getScalarSizeInBits();
   for (unsigned Idx = 0; Idx < NumElts; Idx++) {
     // Assume undef elements match the sequence; we just have to be careful
     // when interpolating across them.
     if (Op.getOperand(Idx).isUndef())
       continue;
+
+    uint64_t Val;
+    if (IsInteger) {
       // The BUILD_VECTOR must be all constants.
       if (!isa<ConstantSDNode>(Op.getOperand(Idx)))
         return None;
-
-    uint64_t Val = Op.getConstantOperandVal(Idx) &
-                   maskTrailingOnes<uint64_t>(EltSizeInBits);
+      Val = Op.getConstantOperandVal(Idx) &
+    } else {
+      // The BUILD_VECTOR must be all constants.
+      if (!isa<ConstantFPSDNode>(Op.getOperand(Idx)))
+        return None;
+      if (auto ExactInteger = getExactInteger(
+              cast<ConstantFPSDNode>(Op.getOperand(Idx))->getValueAPF(),
+              EltSizeInBits))
+        Val = *ExactInteger;
+      else
+        return None;
+    }
 
     if (PrevElt) {
       // Calculate the step since the last non-undef element, and ensure
       // it's consistent across the entire sequence.
       unsigned IdxDiff = Idx - PrevElt->second;
       int64_t ValDiff = SignExtend64(Val - PrevElt->first, EltSizeInBits);
 
       // A zero-value value difference means that we're somewhere in the middle
static Optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
   if (!SeqStepNum || !SeqStepDenom)
     return None;
 
   // Loop back through the sequence and validate elements we might have skipped
   // while waiting for a valid step. While doing this, log any sequence addend.
   for (unsigned Idx = 0; Idx < NumElts; Idx++) {
     if (Op.getOperand(Idx).isUndef())
       continue;
-    uint64_t Val = Op.getConstantOperandVal(Idx) &
-                   maskTrailingOnes<uint64_t>(EltSizeInBits);
+    uint64_t Val;
+    if (IsInteger) {
+      Val = Op.getConstantOperandVal(Idx) &
+    } else {
+      Val = *getExactInteger(
+          cast<ConstantFPSDNode>(Op.getOperand(Idx))->getValueAPF(),
+          EltSizeInBits);
+    }
     uint64_t ExpectedVal =
         (int64_t)(Idx * (uint64_t)*SeqStepNum) / *SeqStepDenom;
     int64_t Addend = SignExtend64(Val - ExpectedVal, EltSizeInBits);
     if (!SeqAddend)
       SeqAddend = Addend;
     else if (Addend != SeqAddend)
       return None;
   }
if (auto SimpleVID = isSimpleVIDSequence(Op)) {
     // Only emit VIDs with suitably-small steps/addends. We use imm5 is a
     // threshold since it's the immediate value many RVV instructions accept.
     // There is no vmul.vi instruction so ensure multiply constant can fit in
     // a single addi instruction.
     if (((StepOpcode == ISD::MUL && isInt<12>(SplatStepVal)) ||
          (StepOpcode == ISD::SHL && isUInt<5>(SplatStepVal))) &&
         isPowerOf2_32(StepDenominator) &&
         (SplatStepVal >= 0 || StepDenominator == 1) && isInt<5>(Addend)) {
-      SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, ContainerVT, Mask, VL);
+      MVT VIDVT =
+          VT.isFloatingPoint() ? VT.changeVectorElementTypeToInteger() : VT;
+      MVT VIDContainerVT =
+          getContainerForFixedLengthVector(DAG, VIDVT, Subtarget);
+      SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VIDContainerVT, Mask, VL);
       // Convert right out of the scalable type so we can use standard ISD
       // nodes for the rest of the computation. If we used scalable types with
       // these, we'd lose the fixed-length vector info and generate worse
       // vsetvli code.
-      VID = convertFromScalableVector(VT, VID, DAG, Subtarget);
+      VID = convertFromScalableVector(VIDVT, VID, DAG, Subtarget);
       if ((StepOpcode == ISD::MUL && SplatStepVal != 1) ||
           (StepOpcode == ISD::SHL && SplatStepVal != 0)) {
         SDValue SplatStep = DAG.getSplatBuildVector(
-            VT, DL, DAG.getConstant(SplatStepVal, DL, XLenVT));
-        VID = DAG.getNode(StepOpcode, DL, VT, VID, SplatStep);
+            VIDVT, DL, DAG.getConstant(SplatStepVal, DL, XLenVT));
+        VID = DAG.getNode(StepOpcode, DL, VIDVT, VID, SplatStep);
       }
       if (StepDenominator != 1) {
         SDValue SplatStep = DAG.getSplatBuildVector(
-            VT, DL, DAG.getConstant(Log2_64(StepDenominator), DL, XLenVT));
-        VID = DAG.getNode(ISD::SRL, DL, VT, VID, SplatStep);
+            VIDVT, DL, DAG.getConstant(Log2_64(StepDenominator), DL, XLenVT));
+        VID = DAG.getNode(ISD::SRL, DL, VIDVT, VID, SplatStep);
       }
       if (Addend != 0 || Negate) {
         SDValue SplatAddend = DAG.getSplatBuildVector(
-            VT, DL, DAG.getConstant(Addend, DL, XLenVT));
-        VID = DAG.getNode(Negate ? ISD::SUB : ISD::ADD, DL, VT, SplatAddend, VID);
+            VIDVT, DL, DAG.getConstant(Addend, DL, XLenVT));
+        VID = DAG.getNode(Negate ? ISD::SUB : ISD::ADD, DL, VIDVT, SplatAddend,
+                          VID);
+      }
+      if (VT.isFloatingPoint()) {
+        // TODO: Use vfwcvt to reduce register pressure.
+        VID = DAG.getNode(ISD::SINT_TO_FP, DL, VT, VID);
       }
       return VID;
     }
   }
 
   // Attempt to detect "hidden" splats, which only reveal themselves as splats
   // when re-interpreted as a vector with a larger element type. For example,
   //   v4i16 = build_vector i16 0, i16 1, i16 0, i16 1

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

 ; LMULMAX2-NEXT:    ret
   %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>
   ret <4 x float> %z
 }
 
 define void @buildvec_dominant0_v2f32(<2 x float>* %x) {
 ; CHECK-LABEL: buildvec_dominant0_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a1, %hi(.LCPI2_0)
-; CHECK-NEXT:    addi a1, a1, %lo(.LCPI2_0)
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT:    vlse32.v v8, (a1), zero
-; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT:    vmv.s.x v8, zero
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
 ; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <2 x float> <float 0.0, float 1.0>, <2 x float>* %x
   ret void
 }
 
 ; We don't want to lower this to the insertion of two scalar elements as above,
 ; as each would require their own load from the constant pool.
 
 define void @buildvec_dominant1_v2f32(<2 x float>* %x) {
 ; CHECK-LABEL: buildvec_dominant1_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a1, %hi(.LCPI3_0)
-; CHECK-NEXT:    addi a1, a1, %lo(.LCPI3_0)
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vadd.vi v8, v8, 1
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
 ; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <2 x float> <float 1.0, float 2.0>, <2 x float>* %x
   ret void
 }
 
 define void @buildvec_dominant0_v4f32(<4 x float>* %x) {
 ; CHECK-LABEL: buildvec_dominant0_v4f32:

llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
+
+define void @foo_1(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    addi a1, a1, %lo(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float -2147483648.0, float -2147483520.0, float -2147483392.0, float -2147483264.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_2(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, %hi(.LCPI1_0)
+; CHECK-NEXT:    addi a1, a1, %lo(.LCPI1_0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float 2147483136.0, float 2147483264.0, float 2147483392.0, float 2147483520.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_3(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vadd.vi v8, v8, -1
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float -1.0, float 0.0, float 1.0, float 2.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_4(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vsll.vi v8, v8, 10
+; CHECK-NEXT:    vadd.vi v8, v8, -16
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float -16.0, float 1008.0, float 2032.0, float 3056.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_5(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float 0.0, float 1.0, float 2.0, float 3.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_6(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, %hi(.LCPI5_0)
+; CHECK-NEXT:    addi a1, a1, %lo(.LCPI5_0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float -0.0, float 1.0, float 2.0, float 3.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_7(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, %hi(.LCPI6_0)
+; CHECK-NEXT:    addi a1, a1, %lo(.LCPI6_0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float -3.0, float -2.0, float -1.0, float -0.0>, ptr %t, align 16
+  ret void
+}
+
+define void @foo_8(ptr nocapture noundef writeonly %t) {
+; CHECK-LABEL: foo_8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, %hi(.LCPI7_0)
+; CHECK-NEXT:    addi a1, a1, %lo(.LCPI7_0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  store <4 x float> <float 1.5, float 2.5, float 3.5, float 4.5>, ptr %t, align 16
+  ret void
+}