[RISCV] Fold fp_to_int(ftrunc (X)) -> fp_to_int(X) for vector.

[jacquesguan]

Summary

This revision adds vector support for performFP_TO_INTCombine. Because we only have static rtz for rvv convert instruction, so only fold ftrunc. I leave performFP_TO_INT_SATCombine not modified, if this way was reviewed as a right one, I would change performFP_TO_INT_SATCombine then.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8862

I'm not sure we should do this. There is a slight semantic difference. If this was legal to replace (fp_to_int (ftrunc V)) with fp_to_int (V) we'd just do that in generic DAGCombine or InstCombine for all targets.

I need to think through exactly what bad thing can happen.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8862

According to llvm langref:
'The fptoui instruction converts its floating-point operand into the nearest (rounding towards zero) unsigned integer value.'
And the llvm.trunc.* intrinsics is same with trunc of libm, which is descripted as : 'If no errors occur, the nearest integer value not greater in magnitude than arg (in other words, arg rounded towards zero), is returned.'

So I think they both are strict rounding towards zero.

I tried common DAGCombiner at first, it would affect some other targets' test, so I switch to RISCV target specificed DAG combiner.

[jacquesguan]

ping.

[jacquesguan]

ping.

[jacquesguan]

ping.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8830

A different vector implementation was implemented in D141599

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue performFP_TO_INTCombine(SDNode *N,
                                        const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   MVT XLenVT = Subtarget.getXLenVT();
 
   // Only handle XLen or i32 types. Other types narrower than XLen will
   // eventually be legalized to XLenVT.
   EVT VT = N->getValueType(0);
-  if (VT != MVT::i32 && VT != XLenVT)
+  bool IsVector = VT.isVector();
+
+  if (VT != MVT::i32 && VT != XLenVT && !IsVector)
+    return SDValue();
+
+  // For vector, ensure the result type is legal.
+  if (IsVector && !TLI.isTypeLegal(VT))
     return SDValue();
 
   SDValue Src = N->getOperand(0);
 
   // Ensure the FP type is also legal.
   if (!TLI.isTypeLegal(Src.getValueType()))
     return SDValue();
 
   // Don't do this for f16 with Zfhmin and not Zfh.
   if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())
     return SDValue();
 
   RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Src);
   if (FRM == RISCVFPRndMode::Invalid)
     return SDValue();
 
+  // We only have static rtz in RVV.
+  if (IsVector && FRM != RISCVFPRndMode::RTZ)
+    return SDValue();
+
   bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
 
   unsigned Opc;
-  if (VT == XLenVT)
+  SDLoc DL(N);
+  if (IsVector)
+    // (fp_to_int (ftrunc V))     -> fp_to_int (V)
+    // Keep fp_to_int for RVV, let it do custom lowerring.
+    return DAG.getNode(N->getOpcode(), DL, VT, Src.getOperand(0));
+  else if (VT == XLenVT)
     Opc = IsSigned ? RISCVISD::FCVT_X : RISCVISD::FCVT_XU;
   else
     Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64;
 
-  SDLoc DL(N);
   SDValue FpToInt = DAG.getNode(Opc, DL, XLenVT, Src.getOperand(0),
                                 DAG.getTargetConstant(FRM, DL, XLenVT));
   return DAG.getNode(ISD::TRUNCATE, DL, VT, FpToInt);
 }
 
 // Fold
 //   (fp_to_int_sat (froundeven X)) -> (select X == nan, 0, (fcvt X, rne))
 //   (fp_to_int_sat (ftrunc X))     -> (select X == nan, 0, (fcvt X, rtz))

llvm/test/CodeGen/RISCV/rvv/vftrunc-conv.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 8 x i1> @vftrunc_tosi_nxv8f64_nxv8i1(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_tosi_nxv8f64_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptosi <vscale x 8 x double> %vb to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
+define <vscale x 8 x i1> @vftrunc_toui_nxv8f64_nxv8i1(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_toui_nxv8f64_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptoui <vscale x 8 x double> %vb to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
+define <vscale x 8 x i8> @vftrunc_tosi_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_tosi_nxv8f64_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v10, v16, 0
+; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v10, 0
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptosi <vscale x 8 x double> %vb to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %evec
+}
+
+define <vscale x 8 x i8> @vftrunc_toui_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_toui_nxv8f64_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v10, v16, 0
+; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v10, 0
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptoui <vscale x 8 x double> %vb to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %evec
+}
+
+define <vscale x 8 x i16> @vftrunc_tosi_nxv8f64_nxv8i16(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_tosi_nxv8f64_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v16, 0
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptosi <vscale x 8 x double> %vb to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %evec
+}
+
+define <vscale x 8 x i16> @vftrunc_toui_nxv8f64_nxv8i16(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_toui_nxv8f64_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vnsrl.wi v8, v16, 0
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptoui <vscale x 8 x double> %vb to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %evec
+}
+
+define <vscale x 8 x i32> @vftrunc_tosi_nxv8f64_nxv8i32(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_tosi_nxv8f64_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptosi <vscale x 8 x double> %vb to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %evec
+}
+
+define <vscale x 8 x i32> @vftrunc_toui_nxv8f64_nxv8i32(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_toui_nxv8f64_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptoui <vscale x 8 x double> %vb to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %evec
+}
+
+define <vscale x 8 x i64> @vftrunc_tosi_nxv8f64_nxv8i64(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_tosi_nxv8f64_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vfcvt.rtz.x.f.v v8, v8
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptosi <vscale x 8 x double> %vb to <vscale x 8 x i64>
+  ret <vscale x 8 x i64> %evec
+}
+
+define <vscale x 8 x i64> @vftrunc_toui_nxv8f64_nxv8i64(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vftrunc_toui_nxv8f64_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
+; CHECK-NEXT:    ret
+  %vb = call <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double> %va)
+  %evec = fptoui <vscale x 8 x double> %vb to <vscale x 8 x i64>
+  ret <vscale x 8 x i64> %evec
+}
+
+declare <vscale x 8 x double> @llvm.trunc.nxv8f64(<vscale x 8 x double>)