[RISCV] Copy SDNodeFlags in lowerToScalableOp.

[arcbbb]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG,
   SDValue Mask, VL;
   std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
   if (HasMergeOp)
     Ops.push_back(DAG.getUNDEF(ContainerVT));
   if (HasMask)
     Ops.push_back(Mask);
   Ops.push_back(VL);
 
-  SDValue ScalableRes = DAG.getNode(NewOpc, DL, ContainerVT, Ops);
+  SDValue ScalableRes =
+      DAG.getNode(NewOpc, DL, ContainerVT, Ops, Op->getFlags());
   return convertFromScalableVector(VT, ScalableRes, DAG, Subtarget);
 }
 
 // Lower a VP_* ISD node to the corresponding RISCVISD::*_VL node:
 // * Operands of each node are assumed to be in the same order.
 // * The EVL operand is promoted from i32 to i64 on RV64.
 // * Fixed-length vectors are converted to their scalable-vector container
 //   types.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=-1 -stop-after=finalize-isel | FileCheck %s
+
+
+define <2 x double> @foo(<2 x double> %x, <2 x double> %y) {
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v8, $v9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr = COPY $v9
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr = COPY $v8
+  ; CHECK-NEXT:   %2:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 [[COPY1]], [[COPY]], 2, 6 /* e64 */, implicit $frm
+  ; CHECK-NEXT:   $v8 = COPY %2
+  ; CHECK-NEXT:   PseudoRET implicit $v8
+  %1 = fadd fast <2 x double> %x, %y
+  ret <2 x double> %1
+}