[RISCV] Add MC support of RISCV Zca Extension

[VincentWu]

Summary

This patch adds support for part of Zc extension which will be frozen soon.

This extension is designed to continue reducing the binary size of RISC-V programs.
In this patch:
Zca is a subset of C extension instructions that are compatible with the Zc extension.

The spec of Zc ext is Here

[jrtc27]

Initial shallow comments:

• They're not ratified, they passed arch review 5 days ago and can be frozen. I don't know if the specs have even been updated to say frozen yet.

• I see a bunch of style violations (missing indentation, missing spaces around tokens, newlines around curly braces where there shouldn't be, bad camel case, missing newlines at ends of files).

• Please keep MC, codegen and optimisation pass patches separate, it makes it much easier to review.

• Are these mnemonics, especially for push/pop's operands, accepted by the GNU community or just dreamt up by the authors of the spec?

[craig.topper]

Where is it documented that these extensions are ratified?

Putting 3 extensions in one patch is a guaranteed way to make it take longer to approved. The smaller you can make patches the quicker individual pieces can be reviewed and approved. I would also recommend putting new optimization passes in separate patches. MC layer and CodeGen should be separate patches.

Please run clang-format on patches.

llvm/lib/Object/ELFObjectFile.cpp

305 ↗

(On Diff #446029)

Capitalize variable names

343 ↗

(On Diff #446029)

Space after if. Space before curly brace

344 ↗

(On Diff #446029)

Space before false

347 ↗

(On Diff #446029)

Extra blank line

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2109 ↗

(On Diff #446029)

Memonic -> Mnemonic

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

194 ↗

(On Diff #446029)

Capitalize variable names

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

416 ↗

(On Diff #446029)

Space after '<'

llvm/lib/Target/RISCV/RISCVMoveOptimizer.cpp

1 ↗

(On Diff #446029)

Header banner should be exactly 80 characters long

20 ↗

(On Diff #446029)

This says Zce but Zce is not mentioned in your patch description.

225 ↗

(On Diff #446029)

Use the template version of getSubtarget that does this cast.

230 ↗

(On Diff #446029)

getInstrInfo() on RISCVSubtarget* returns RISCVInstrInfo * this case shouldn't be needed.

llvm/lib/Target/RISCV/RISCVOptimizePushPop.cpp

1 ↗

(On Diff #446029)

80 columns

23 ↗

(On Diff #446029)

too many blank lines

27 ↗

(On Diff #446029)

This is overly indented

44 ↗

(On Diff #446029)

Capitalize variable names.

Can this a be a DenseMap? std::map is an ordered map which doesn't make much sense for pointers.

73 ↗

(On Diff #446029)

Capitalize variable names

[VincentWu]

In D130141#3664612, @jrtc27 wrote:

• They're not ratified, they passed arch review 5 days ago and can be frozen. I don't know if the specs have even been updated to say frozen yet.

Apologies for my misrepresentation, I have corrected my description

• I see a bunch of style violations (missing indentation, missing spaces around tokens, newlines around curly braces where there shouldn't be, bad camel case, missing newlines at ends of files).

• Please keep MC, codegen and optimisation pass patches separate, it makes it much easier to review.

I will split the patch and update them soon.

• Are these mnemonics, especially for push/pop's operands, accepted by the GNU community or just dreamt up by the authors of the spec?

[VincentWu]

In D130141#3664635, @craig.topper wrote:

Where is it documented that these extensions are ratified?

sorry for my wrong statements, I have corrected my description

Putting 3 extensions in one patch is a guaranteed way to make it take longer to approved. The smaller you can make patches the quicker individual pieces can be reviewed and approved. I would also recommend putting new optimization passes in separate patches. MC layer and CodeGen should be separate patches.

Please run clang-format on patches.

I will split this patch as much as passable soon.

[VincentWu]

Split this patch, which now contains only Zca's modifications.

format the patch

address comments

[frasercrmck]

llvm/lib/Object/ELFObjectFile.cpp

317 ↗

(On Diff #446135)

This doesn't seem right to me. Why is zca treated this way but no other z* extensions are?

llvm/lib/Target/RISCV/RISCVFrameLowering.h

48 ↗

(On Diff #446135)

Pushable with a capital P

EDIT: but this function isn't used?

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

937 ↗

(On Diff #446135)

Should we have Subtarget.hasStdExtCOrStdExtZca?

In certain contexts, would even a Subtarget.hasCInstructions make sense, like we have Subtarget.hasVInstructions?

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

61 ↗

(On Diff #446135)

Do we need to resort to checking feature bits in RISCVInstrInfo? Can't we use STI.hasStdExtC and friends?

1246 ↗

(On Diff #446135)

I'd rather the fetching of the subtarget was taken out into a variable rather than repeating it twice.

Also can we cast this to a RISCVSubtarget and use hasStdExtC and friends instead of prodding feature bits?

[jrtc27]

This is still doing both MC and codegen. Please separate them as I said.

[VincentWu]

address some comments and split the patch into MC & CodeGen

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

332

16-bit in this is potentially confusing as it could also be read as the size of the data being loaded/stored. "compressed" might be more clear?

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

408

Is adding Predicates here fixing a bug? Or was it getting the one on line 284 making this change redundant?

495

Doesn't C_LWSP need to be updated? It's sharing with C_FLDSP

555

C_SWSP needs to be updated

702

There's no predicate in effect for c.lw. This is a bug already in tree. I'll fix it.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

495

Ignore this I misread it.

555

Ignore this I misread it.

[VincentWu]

address comments

[VincentWu]

Fixed failed testcase

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

698

Please rebase, I changed this section to fix c.lw, c.sw, c.lwsp, c.swsp to have predicates

[VincentWu]

rebase

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

112

Can we alphabetize this?

llvm/test/MC/RISCV/rv32zca-invalid.s

2

Can this command line be added to rv32c-invalid.s? Test content appears to be the same

llvm/test/MC/RISCV/rv32zca-valid.s

2

Can this be merged with rv32c-valid.s?

llvm/test/MC/RISCV/rv64zca-valid.s

20

Should these error mesages mention Zca?

[jrtc27]

llvm/lib/Target/RISCV/RISCVSubtarget.h

170

Alphabetise

llvm/test/MC/RISCV/rv32c-only-valid.s

20

This needs or 'Zca' ... adding otherwise you're not checking what you think you are. Are there cases of this in other files too?

[craig.topper]

llvm/test/MC/RISCV/rv32c-only-valid.s

20

I've added {{$}} to the end of all of these lines in https://reviews.llvm.org/D131436 so we'll require all extensions to be listed.

[VincentWu]

address comment
rebase
merge testcase for C and Zca

[craig.topper]

LGTM

[VincentWu]

In D130141#3726751, @craig.topper wrote:

LGTM

Thanks )

llvm/lib/Support/RISCVISAInfo.cpp

 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zbe", RISCVExtensionVersion{0, 93}},
     {"zbf", RISCVExtensionVersion{0, 93}},
     {"zbm", RISCVExtensionVersion{0, 93}},
     {"zbp", RISCVExtensionVersion{0, 93}},
     {"zbr", RISCVExtensionVersion{0, 93}},
     {"zbt", RISCVExtensionVersion{0, 93}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
+    {"zca", RISCVExtensionVersion{0, 70}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
 
 // This function finds the first character that doesn't belong to a version
 // (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureStdExtZk
     : SubtargetFeature<"zk", "HasStdExtZk", "true",
                        "'Zk' (Standard scalar cryptography extension)",
                        [FeatureStdExtZkn,
                         FeatureStdExtZkr,
                         FeatureStdExtZkt]>;
 
+def FeatureExtZca
+    : SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
+                       "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+def HasStdExtZca : Predicate<"Subtarget->hasStdExtZca()">,
+                           AssemblerPredicate<(all_of FeatureExtZca),
+                           "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+
+def HasStdExtCOrZca
+    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
+                AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
+                                   "'C' (Compressed Instructions) or "
+                                   "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

class CS_ALU<bits<6> funct6, bits<2> funct2, string OpcodeStr,
   let Constraints = "$rd = $rd_wb";
   let Inst{9-7} = rd;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [X2] in
 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
                              (ins SP:$rs1, uimm10_lsb00nonzero:$imm),
                              "c.addi4spn", "$rd, $rs1, $imm">,
                              Sched<[WriteIALU, ReadIALU]> {
   bits<5> rs1;
   let Inst{12-11} = imm{5-4};

 def C_FLW  : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
              Sched<[WriteFLD32, ReadMemBase]> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
            Sched<[WriteLDD, ReadMemBase]> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
 }
 
 let Predicates = [HasStdExtC, HasStdExtD] in

 def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
              Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
            Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
 }
 
 let rd = 0, imm = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
                  Sched<[WriteIALU, ReadIALU]> {
   let Constraints = "$rd = $rd_wb";
   let Inst{6-2} = 0;
   let isAsmParserOnly = 1;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
     DecoderNamespace = "RISCV32Only_", Defs = [X1],
-    Predicates = [HasStdExtC, IsRV32]  in
+    Predicates = [HasStdExtCOrZca, IsRV32]  in
 def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
                        "c.jal", "$offset">, Sched<[WriteJal]>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
-    Predicates = [HasStdExtC, IsRV64] in
+    Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
                          (ins GPRNoX0:$rd, simm6:$imm),
                          "c.addiw", "$rd, $imm">,
               Sched<[WriteIALU32, ReadIALU32]> {
   let Constraints = "$rd = $rd_wb";
   let Inst{6-2} = imm{4-0};
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
                       "c.li", "$rd, $imm">,
            Sched<[WriteIALU]> {
   let Inst{6-2} = imm{4-0};
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
def C_SUB  : CS_ALU<0b100011, 0b00, "c.sub", GPRC>,
              Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 def C_XOR  : CS_ALU<0b100011, 0b01, "c.xor", GPRC>,
              Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 def C_OR   : CS_ALU<0b100011, 0b10, "c.or" , GPRC>,
              Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 def C_AND  : CS_ALU<0b100011, 0b11, "c.and", GPRC>,
              Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
 def C_SUBW : CS_ALU<0b100111, 0b00, "c.subw", GPRC>,
              Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
 def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>,
              Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),

 
 let Predicates = [HasStdExtC, HasStdExtD] in
 def C_FLDSP  : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
                Sched<[WriteFLD64, ReadMemBase]> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
 
 def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,
              Sched<[WriteLDW, ReadMemBase]> {
   let Inst{6-4} = imm{4-2};
   let Inst{3-2} = imm{7-6};
 }
 
 let DecoderNamespace = "RISCV32Only_",
     Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
 def C_FLWSP  : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
                Sched<[WriteFLD32, ReadMemBase]> {
   let Inst{6-4} = imm{4-2};
   let Inst{3-2} = imm{7-6};
 }
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
              Sched<[WriteLDD, ReadMemBase]> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),

 
 let Predicates = [HasStdExtC, HasStdExtD] in
 def C_FSDSP  : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
                Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
   let Inst{12-10} = imm{5-3};
   let Inst{9-7}   = imm{8-6};
 }
 
 def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,
              Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
   let Inst{12-9} = imm{5-2};
   let Inst{8-7}  = imm{7-6};
 }
 
 let DecoderNamespace = "RISCV32Only_",
     Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
 def C_FSWSP  : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
                Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
   let Inst{12-9} = imm{5-2};
   let Inst{8-7}  = imm{7-6};
 }
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,
              Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
   let Inst{12-10} = imm{5-3};
   let Inst{9-7}   = imm{8-6};
 }
 
 // The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU
 // binutils as 16-bit instruction known to be unimplemented (i.e., trapping).
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
               Sched<[]> {
   let Inst{15-0} = 0;
 }
 
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
 
 //===----------------------------------------------------------------------===//
 // HINT Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
     mayStore = 0 in
 {
 
 let rd = 0 in
 def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
                             "c.nop", "$imm">, Sched<[WriteNop]> {
   let Inst{6-2} = imm{4-0};
   let DecoderMethod = "decodeRVCInstrSImm";
def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
                                "c.srai64", "$rd">,
                     Sched<[WriteShiftImm, ReadShiftImm]> {
   let Constraints = "$rd = $rd_wb";
   let Inst{6-2} = 0;
   let Inst{11-10} = 1;
   let Inst{12} = 0;
 }
 
-} // Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+} // Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
   // mayStore = 0
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 let EmitPriority = 0 in {
 let Predicates = [HasStdExtC, HasStdExtD] in
 def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>;
 
 def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
 def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRC:$rs1, 0)>;
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRC:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtD] in
 def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRC:$rs1, 0)>;
 
 def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRC:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
 def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRC:$rs1, 0)>;
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRC:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtD] in
 def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SP:$rs1, 0)>;
 
 def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SP:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
 def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SP:$rs1, 0)>;
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SP:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtD] in
 def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SP:$rs1, 0)>;
 
 def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SP:$rs1, 0)>;
 
 let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
 def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SP:$rs1, 0)>;
 
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
 def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SP:$rs1, 0)>;
 }
 
 //===----------------------------------------------------------------------===//
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
 // Patterns are defined in the same order the compressed instructions appear

llvm/lib/Target/RISCV/RISCVSubtarget.h

private:
   bool HasStdExtZbc = false;
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
+  bool HasStdExtZca = false;
   bool HasStdExtV = false;
   bool HasStdExtZve32x = false;
   bool HasStdExtZve32f = false;
   bool HasStdExtZve64x = false;
   bool HasStdExtZve64f = false;
   bool HasStdExtZve64d = false;
   bool HasStdExtZvfh = false;
   bool HasStdExtZfhmin = false;
public:
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtZvfh() const { return HasStdExtZvfh; }
+  bool hasStdExtZca() const { return HasStdExtZca; }
   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool hasStdExtZfinx() const { return HasStdExtZfinx; }
   bool hasStdExtZdinx() const { return HasStdExtZdinx; }
   bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
   bool hasStdExtZhinx() const { return HasStdExtZhinx; }
   bool hasStdExtZbkb() const { return HasStdExtZbkb; }
   bool hasStdExtZbkc() const { return HasStdExtZbkc; }

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32i_zkt1p0"
 # CHECK: attribute      5, "rv32i2p0_zkt1p0"
 
 .attribute arch, "rv32i_zk1p0"
 # CHECK: attribute      5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32izca0p70"
+# CHECK: attribute      5, "rv32i2p0_zca0p70"

llvm/test/MC/RISCV/rv32c-only-valid.s

 # RUN:     | FileCheck --check-prefix=CHECK-NO-RV32 %s
 # RUN: not llvm-mc -triple riscv64 \
 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck --check-prefix=CHECK-NO-RV32-AND-EXT %s
 
 # CHECK-OBJ: c.jal 0x7fe
 # CHECK-ASM: c.jal 2046
 # CHECK-ASM: encoding: [0xfd,0x2f]
 # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
 # CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
-# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set
+# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension), RV32I Base Instruction Set
 c.jal 2046

llvm/test/MC/RISCV/rv32zca-invalid.s

+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zca -mattr=+no-rvc-hints < %s 2>&1 \
+# RUN:     | FileCheck %s
+
+## GPRC
+.LBB:
+c.lw  ra, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+c.sw  sp, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+c.beqz  t0, .LBB # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.bnez  s8, .LBB # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.addi4spn  s4, sp, 12 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+c.srli  s7, 12 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.srai  t0, 12 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.andi  t1, 12 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.and  t1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+c.or   a0, s8 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.xor  t2, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+c.sub  a0, s8 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+
+## GPRNoX0
+c.lwsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.lwsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.jr  x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+c.jalr  zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.addi  x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero
+c.li  zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
+c.slli  zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+c.mv  zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
+c.mv  ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+c.add  ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+c.add  zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+## GPRNoX0X2
+c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
+c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+## SP
+c.addi4spn  a0, a0, 12 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+c.addi16sp  t0, 16 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+# Out of range immediates
+
+## uimmlog2xlennonzero
+c.slli t0, 64 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
+c.srli a0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
+c.srai a0, 0  # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
+
+## simm6
+c.li t0, 128 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-32, 31]
+c.li t0, foo # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-32, 31]
+c.li t0, %lo(foo) # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-32, 31]
+c.li t0, %hi(foo) # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-32, 31]
+c.andi a0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
+c.andi a0, foo # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
+c.andi a0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
+c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
+
+## simm6nonzero
+c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
+c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
+c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
+c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
+c.addi t0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
+c.addi t0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
+
+## c_lui_imm
+c.lui t0, 0 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
+c.lui t0, 32 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
+c.lui t0, 0xffffdf # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
+c.lui t0, 0x1000000 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
+
+## uimm8_lsb00
+c.lwsp  ra, 256(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 252]
+c.swsp  ra, -4(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 252]
+## uimm7_lsb00
+c.lw  s0, -4(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+c.sw  s0, 128(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+
+## simm9_lsb0
+c.bnez  s1, -258 # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-256, 254]
+c.beqz  a0, 256 # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-256, 254]
+
+## simm12_lsb0
+c.j 2048 # CHECK: :[[@LINE]]:5: error: immediate must be a multiple of 2 bytes in the range [-2048, 2046]
+c.jal -2050 # CHECK: :[[@LINE]]:7: error: immediate must be a multiple of 2 bytes in the range [-2048, 2046]
+
+## uimm10_lsb00nonzero
+c.addi4spn  a0, sp, 0 # CHECK: :[[@LINE]]:21: error: immediate must be a multiple of 4 bytes in the range [4, 1020]
+c.addi4spn  a0, sp, 1024 # CHECK: :[[@LINE]]:21: error: immediate must be a multiple of 4 bytes in the range [4, 1020]
+
+## simm10_lsb0000nonzero
+c.addi16sp  sp, -528 # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 16 bytes and non-zero in the range [-512, 496]
+c.addi16sp  sp, 512 # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 16 bytes and non-zero in the range [-512, 496]
+c.addi16sp  sp, 0 # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 16 bytes and non-zero in the range [-512, 496]

llvm/test/MC/RISCV/rv32zca-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zca < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zca -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zca < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zca -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# TODO: more exhaustive testing of immediate encoding.
+
+# CHECK-ASM-AND-OBJ: c.lwsp ra, 0(sp)
+# CHECK-ASM: encoding: [0x82,0x40]
+c.lwsp ra, 0(sp)
+# CHECK-ASM-AND-OBJ: c.swsp ra, 252(sp)
+# CHECK-ASM: encoding: [0x86,0xdf]
+c.swsp ra, 252(sp)
+# CHECK-ASM-AND-OBJ: c.lw a2, 0(a0)
+# CHECK-ASM: encoding: [0x10,0x41]
+c.lw a2, 0(a0)
+# CHECK-ASM-AND-OBJ: c.sw a5, 124(a3)
+# CHECK-ASM: encoding: [0xfc,0xde]
+c.sw a5, 124(a3)
+
+# CHECK-OBJ: c.j 0xfffff808
+# CHECK-ASM: c.j -2048
+# CHECK-ASM: encoding: [0x01,0xb0]
+c.j -2048
+# CHECK-ASM-AND-OBJ: c.jr a7
+# CHECK-ASM: encoding: [0x82,0x88]
+c.jr a7
+# CHECK-ASM-AND-OBJ: c.jalr a1
+# CHECK-ASM: encoding: [0x82,0x95]
+c.jalr a1
+# CHECK-OBJ: c.beqz a3, 0xffffff0e
+# CHECK-ASM: c.beqz a3, -256
+# CHECK-ASM: encoding: [0x81,0xd2]
+c.beqz a3, -256
+# CHECK-OBJ: c.bnez a5, 0x10e
+# CHECK-ASM: c.bnez a5, 254
+# CHECK-ASM: encoding: [0xfd,0xef]
+c.bnez a5,  254
+
+# CHECK-ASM-AND-OBJ: c.li a7, 31
+# CHECK-ASM: encoding: [0xfd,0x48]
+c.li a7, 31
+# CHECK-ASM-AND-OBJ: c.addi a3, -32
+# CHECK-ASM: encoding: [0x81,0x16]
+c.addi a3, -32
+# CHECK-ASM-AND-OBJ: c.addi16sp sp, -512
+# CHECK-ASM: encoding: [0x01,0x71]
+c.addi16sp sp, -512
+# CHECK-ASM-AND-OBJ: c.addi16sp sp, 496
+# CHECK-ASM: encoding: [0x7d,0x61]
+c.addi16sp sp, 496
+# CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 1020
+# CHECK-ASM: encoding: [0xf4,0x1f]
+c.addi4spn a3, sp, 1020
+# CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 4
+# CHECK-ASM: encoding: [0x54,0x00]
+c.addi4spn a3, sp, 4
+# CHECK-ASM-AND-OBJ: c.slli a1, 1
+# CHECK-ASM: encoding: [0x86,0x05]
+c.slli a1, 1
+# CHECK-ASM-AND-OBJ: c.srli a3, 31
+# CHECK-ASM: encoding: [0xfd,0x82]
+c.srli a3, 31
+# CHECK-ASM-AND-OBJ: c.srai a4, 2
+# CHECK-ASM: encoding: [0x09,0x87]
+c.srai a4, 2
+# CHECK-ASM-AND-OBJ: c.andi a5, 15
+# CHECK-ASM: encoding: [0xbd,0x8b]
+c.andi a5, 15
+# CHECK-ASM-AND-OBJ: c.mv a7, s0
+# CHECK-ASM: encoding: [0xa2,0x88]
+c.mv a7, s0
+# CHECK-ASM-AND-OBJ: c.and a1, a2
+# CHECK-ASM: encoding: [0xf1,0x8d]
+c.and a1, a2
+# CHECK-ASM-AND-OBJ: c.or a2, a3
+# CHECK-ASM: encoding: [0x55,0x8e]
+c.or a2, a3
+# CHECK-ASM-AND-OBJ: c.xor a3, a4
+# CHECK-ASM: encoding: [0xb9,0x8e]
+c.xor a3, a4
+# CHECK-ASM-AND-OBJ: c.sub a4, a5
+# CHECK-ASM: encoding: [0x1d,0x8f]
+c.sub a4, a5
+# CHECK-ASM-AND-OBJ: c.nop
+# CHECK-ASM: encoding: [0x01,0x00]
+c.nop
+# CHECK-ASM-AND-OBJ: c.ebreak
+# CHECK-ASM: encoding: [0x02,0x90]
+c.ebreak
+# CHECK-ASM-AND-OBJ: c.lui s0, 1
+# CHECK-ASM: encoding: [0x05,0x64]
+c.lui s0, 1
+# CHECK-ASM-AND-OBJ: c.lui s0, 31
+# CHECK-ASM: encoding: [0x7d,0x64]
+c.lui s0, 31
+# CHECK-ASM-AND-OBJ: c.lui s0, 1048544
+# CHECK-ASM: encoding: [0x01,0x74]
+c.lui s0, 0xfffe0
+# CHECK-ASM-AND-OBJ: c.lui s0, 1048575
+# CHECK-ASM: encoding: [0x7d,0x74]
+c.lui s0, 0xfffff
+# CHECK-ASM-AND-OBJ: c.unimp
+# CHECK-ASM: encoding: [0x00,0x00]
+c.unimp

llvm/test/MC/RISCV/rv64zca-hints-valid.s

+# RUN: llvm-mc %s -triple riscv64 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zca < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zca -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.slli zero, 63
+# CHECK-ASM: encoding: [0x7e,0x10]
+c.slli x0, 63

llvm/test/MC/RISCV/rv64zca-invalid.s

+# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zca < %s 2>&1 | FileCheck %s
+
+## GPRC
+c.ld ra, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+c.sd sp, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+c.addw   a0, a7 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+c.subw   a0, a6 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+## GPRNoX0
+c.ldsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.ldsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Out of range immediates
+
+## uimmlog2xlennonzero
+c.slli t0, 64 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
+c.srli a0, -1 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
+c.srai a0, 0  # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
+
+## simm6
+c.addiw t0, -33 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
+c.addiw t0, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
+c.addiw t0, foo # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
+c.addiw t0, %lo(foo) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
+c.addiw t0, %hi(foo) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
+
+## uimm9_lsb000
+c.ldsp  ra, 512(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 8 bytes in the range [0, 504]
+c.sdsp  ra, -8(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 8 bytes in the range [0, 504]
+## uimm8_lsb000
+c.ld  s0, -8(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 8 bytes in the range [0, 248]
+c.sd  s0, 256(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 8 bytes in the range [0, 248]

llvm/test/MC/RISCV/rv64zca-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
+# RUN:     | llvm-objdump --mattr=+c -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+#
+# RUN: not llvm-mc -triple riscv64 \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+c \
+# RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-RV64 %s
+
+# TODO: more exhaustive testing of immediate encoding.
+
+# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
+# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.ldsp ra, 0(sp)
+# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
+# CHECK-ASM: encoding: [0x86,0xff]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.sdsp ra, 504(sp)
+# CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
+# CHECK-ASM: encoding: [0x98,0x62]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.ld a4, 0(a3)
+# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3)
+# CHECK-ASM: encoding: [0xfc,0xfe]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.sd a5, 248(a3)
+
+# CHECK-ASM-AND-OBJ: c.subw a3, a4
+# CHECK-ASM: encoding: [0x99,0x9e]
+c.subw a3, a4
+# CHECK-ASM-AND-OBJ: c.addw a0, a2
+# CHECK-ASM: encoding: [0x31,0x9d]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.addw a0, a2
+
+# CHECK-ASM-AND-OBJ: c.addiw a3, -32
+# CHECK-ASM: encoding: [0x81,0x36]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.addiw a3, -32
+# CHECK-ASM-AND-OBJ: c.addiw a3, 31
+# CHECK-ASM: encoding: [0xfd,0x26]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.addiw a3, 31
+
+# CHECK-ASM-AND-OBJ: c.slli s0, 1
+# CHECK-ASM: encoding: [0x06,0x04]
+# CHECK-NO-EXT:  error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-RV64:  error: instruction requires the following: RV64I Base Instruction Set
+c.slli s0, 1
+# CHECK-ASM-AND-OBJ: c.srli a3, 63
+# CHECK-ASM: encoding: [0xfd,0x92]
+c.srli a3, 63
+# CHECK-ASM-AND-OBJ: c.srai a2, 63
+# CHECK-ASM: encoding: [0x7d,0x96]
+c.srai a2, 63