[RISCV] Add support for static chain

[melonedo]

Summary

The static chain parameter is a special parameter that is not passed in the usual argument registers or stack space. For example, in x64 System V ABI it is always passed in R10. Although the ABI of RISCV does not assign a register for this purpose, GCC had support for it on RISC-V a long time ago, and it is exposed via __builtin_call_with_static_chain intrinsic, and assign t2 for static chain parameters. This patch also chose t2 for compatibility.

In LLVM, static chain parameters are handled by the nest attribute of an argument to a function (D6332), so tests are added to ensure nest arguments are handled correctly.

[melonedo]

Rebase the commit on master.

[luismarques]

I guess this patch should update the other conventions as well? E.g. error out if nest is used with the GHC CC. There's also the FastCC.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

11081–11082

Nit: "as did" -> "as done"

llvm/test/CodeGen/RISCV/nest-register.ll

2–10

Checking RV32IM and RV64IM is not needed.

[jrtc27]

This doesn’t work with dynamic linking (unless you use the recently-added STO_RISCV_VARIANT_CC) as t2 can be clobbered by the resolver.

[melonedo]

Adopt suggestions

[melonedo]

In D129106#3630316, @jrtc27 wrote:

This doesn’t work with dynamic linking (unless you use the recently-added STO_RISCV_VARIANT_CC) as t2 can be clobbered by the resolver.

Sorry for the delay, I opened an issue in GCC and they feel OK with a scratch register.

[melonedo]

In D129106#3629936, @luismarques wrote:

I guess this patch should update the other conventions as well? E.g. error out if nest is used with the GHC CC. There's also the FastCC.

I added an error check in GHC CC. If not mistaken, the FastCC is internal, so as long as the frontend emit consistent function attrubutes, it does not make a difference whether an argument is attributed 'nest' or not. Ignoring 'nest' in the FastCC should be fine.

[kito-cheng]

Could you re-upload your patch again, the diff seems is only contain fixes for review commets?

[melonedo]

Rebase and upload changes again

[kito-cheng]

LGTM

[MaskRay]

llvm/test/CodeGen/RISCV/nest-register.ll

11

i8* => ptr for opaque pointers

[melonedo]

Use ptr for opaque pointers

[melonedo]

Use opaque pointers

[melonedo]

Also use opaque pointers in ghccc-nest.ll

[jrtc27]

llvm/test/CodeGen/RISCV/ghccc-nest.ll

2

Double negative, though feel this is redundant with the CHECK line

[melonedo]

Revise comments

[MaskRay]

llvm/test/CodeGen/RISCV/ghccc-nest.ll

3

-filetype=null if the output is not used

[melonedo]

Specify -filetype=null

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
                      MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
                      ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
                      bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
                      Optional<unsigned> FirstMaskArgument) {
   unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
   assert(XLen == 32 || XLen == 64);
   MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
 
+  // Static chain parameter must not be passed in normal argument registers,
+  // so we assign t2 for it as done in GCC's __builtin_call_with_static_chain
+  if (ArgFlags.isNest()) {
+    if (unsigned Reg = State.AllocateReg(RISCV::X7)) {
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+      return false;
+    }
+  }
+
   // Any return value split in to more than two values can't be returned
   // directly. Vectors are returned via the available vector registers.
   if (!LocVT.isVector() && IsRet && ValNo > 1)
     return true;
 
   // UseGPRForF16_F32 if targeting one of the soft-float ABIs, if passing a
   // variadic argument, or if no F16/F32 argument registers are available.
   bool UseGPRForF16_F32 = true;
static bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
 
   return true; // CC didn't match.
 }
 
 static bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
 
+  if (ArgFlags.isNest()) {
+    report_fatal_error(
+        "Attribute 'nest' is not supported in GHC calling convention");
+  }
+
   if (LocVT == MVT::i32 || LocVT == MVT::i64) {
     // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
     //                        s1    s2  s3  s4  s5  s6  s7  s8  s9  s10 s11
     static const MCPhysReg GPRList[] = {
         RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22,
         RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27};
     if (unsigned Reg = State.AllocateReg(GPRList)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));

llvm/test/CodeGen/RISCV/ghccc-nest.ll

+; RUN: not --crash llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs -filetype=null < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs -filetype=null < %s 2>&1 | FileCheck %s
+
+define ghccc ptr @nest_receiver(ptr nest %arg) nounwind {
+  ret ptr %arg
+}
+
+define ghccc ptr @nest_caller(ptr %arg) nounwind {
+  %result = call ghccc ptr @nest_receiver(ptr nest %arg)
+  ret ptr %result
+}
+
+; CHECK: LLVM ERROR: Attribute 'nest' is not supported in GHC calling convention

llvm/test/CodeGen/RISCV/nest-register.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+; Tests that the 'nest' parameter attribute causes the relevant parameter to be
+; passed in the right register.
+
+define ptr @nest_receiver(ptr nest %arg) nounwind {
+; RV32I-LABEL: nest_receiver:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    mv a0, t2
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: nest_receiver:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    mv a0, t2
+; RV64I-NEXT:    ret
+;
+  ret ptr %arg
+}
+
+define ptr @nest_caller(ptr %arg) nounwind {
+; RV32I-LABEL: nest_caller:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    mv t2, a0
+; RV32I-NEXT:    call nest_receiver@plt
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: nest_caller:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    mv t2, a0
+; RV64I-NEXT:    call nest_receiver@plt
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+  %result = call ptr @nest_receiver(ptr nest %arg)
+  ret ptr %result
+}