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[RISCV] Add support for static chain
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Authored by melonedo on Jul 4 2022, 11:42 PM.

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Summary

The static chain parameter is a special parameter that is not passed in the usual argument registers or stack space. For example, in x64 System V ABI it is always passed in R10. Although the ABI of RISCV does not assign a register for this purpose, GCC had support for it on RISC-V a long time ago, and it is exposed via __builtin_call_with_static_chain intrinsic, and assign t2 for static chain parameters. This patch also chose t2 for compatibility.

In LLVM, static chain parameters are handled by the nest attribute of an argument to a function (D6332), so tests are added to ensure nest arguments are handled correctly.

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Event Timeline

melonedo created this revision.Jul 4 2022, 11:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 4 2022, 11:42 PM
melonedo requested review of this revision.Jul 4 2022, 11:42 PM
melonedo updated this revision to Diff 442195.Jul 5 2022, 1:05 AM

Rebase the commit on master.

I guess this patch should update the other conventions as well? E.g. error out if nest is used with the GHC CC. There's also the FastCC.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
10206–10207

Nit: "as did" -> "as done"

llvm/test/CodeGen/RISCV/nest-register.ll
1–9

Checking RV32IM and RV64IM is not needed.

jrtc27 added a comment.Jul 5 2022, 7:00 AM

This doesn’t work with dynamic linking (unless you use the recently-added STO_RISCV_VARIANT_CC) as t2 can be clobbered by the resolver.