This is an archive of the discontinued LLVM Phabricator instance.

Differential D128627

[RISCV] Support VECTOR_REVERSE mask operation.
ClosedPublic

Authored by Jimerlife on Jun 27 2022, 2:06 AM.

Details

Reviewers
craig.topper
frasercrmck
benshi001
Commits
rG96ab083622f5: [RISCV] Support VECTOR_REVERSE mask operation.
Summary

Support vector_reverse mask operation. Widen i1 element type to i8, then reverse it, finally truncate result.

Diff Detail

Event Timeline

Jimerlife created this revision.Jun 27 2022, 2:06 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2022, 2:06 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 29 others. · View Herald Transcript
Jimerlife requested review of this revision.Jun 27 2022, 2:06 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptJun 27 2022, 2:06 AM
Harbormaster completed remote builds in B172139: Diff 440133.Jun 27 2022, 2:57 AM
craig.topper accepted this revision.Jun 27 2022, 9:25 AM

LGTM

This revision is now accepted and ready to land.Jun 27 2022, 9:25 AM
reames added a subscriber: reames.Jun 27 2022, 11:39 AM

LGTM, but can you make sure to post a follow up patch to update cost model please?

Jimerlife added a comment.Jun 28 2022, 12:56 AM
In D128627#3613149, @reames wrote:

LGTM, but can you make sure to post a follow up patch to update cost model please?

I am not familiar with cost model, but I can try to do this.

This revision was landed with ongoing or failed builds.Jun 28 2022, 12:58 AM
Closed by commit rG96ab083622f5: [RISCV] Support VECTOR_REVERSE mask operation. (authored by Jimerlife). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jimerlife added a commit: rG96ab083622f5: [RISCV] Support VECTOR_REVERSE mask operation..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
7 lines
test/
CodeGen/
RISCV/
rvv/
622 lines

Diff 440514

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 519 Lines • ▼ Show 20 Lines for (MVT VT : BoolVecVTs) {
setTruncStoreAction(OtherVT, VT, Expand); setTruncStoreAction(OtherVT, VT, Expand);
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, OtherVT, setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, OtherVT,
VT, Expand); VT, Expand);
} }
setOperationAction( setOperationAction(
{ISD::VP_FPTOSI, ISD::VP_FPTOUI, ISD::VP_TRUNCATE, ISD::VP_SETCC}, VT, {ISD::VP_FPTOSI, ISD::VP_FPTOUI, ISD::VP_TRUNCATE, ISD::VP_SETCC}, VT,
Custom); Custom);
setOperationAction(ISD::VECTOR_REVERSE, VT, Custom);
} }
for (MVT VT : IntVecVTs) { for (MVT VT : IntVecVTs) {
if (!isTypeLegal(VT)) if (!isTypeLegal(VT))
continue; continue;
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom); setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
▲ Show 20 Lines • Show All 5,097 Lines • ▼ Show 20 Lines
// subtracting the id of each element from (VLMAX-1). This will convert // subtracting the id of each element from (VLMAX-1). This will convert
// the indices like so: // the indices like so:
// (0, 1,..., VLMAX-2, VLMAX-1) -> (VLMAX-1, VLMAX-2,..., 1, 0). // (0, 1,..., VLMAX-2, VLMAX-1) -> (VLMAX-1, VLMAX-2,..., 1, 0).
// TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16. // TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op, SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
MVT VecVT = Op.getSimpleValueType(); MVT VecVT = Op.getSimpleValueType();
if (VecVT.getVectorElementType() == MVT::i1) {
MVT WidenVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount());
SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, Op.getOperand(0));
SDValue Op2 = DAG.getNode(ISD::VECTOR_REVERSE, DL, WidenVT, Op1);
return DAG.getNode(ISD::TRUNCATE, DL, VecVT, Op2);
}
unsigned EltSize = VecVT.getScalarSizeInBits(); unsigned EltSize = VecVT.getScalarSizeInBits();
unsigned MinSize = VecVT.getSizeInBits().getKnownMinValue(); unsigned MinSize = VecVT.getSizeInBits().getKnownMinValue();
unsigned VectorBitsMax = Subtarget.getRealMaxVLen(); unsigned VectorBitsMax = Subtarget.getRealMaxVLen();
unsigned MaxVLMAX = unsigned MaxVLMAX =
RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize); RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
unsigned GatherOpc = RISCVISD::VRGATHER_VV_VL; unsigned GatherOpc = RISCVISD::VRGATHER_VV_VL;
MVT IntVT = VecVT.changeVectorElementTypeToInteger(); MVT IntVT = VecVT.changeVectorElementTypeToInteger();
▲ Show 20 Lines • Show All 6,673 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-UNKNOWN ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-UNKNOWN
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-256 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-256
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-512 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-BITS-512
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-UNKNOWN ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-UNKNOWN
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-256 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-256
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-512 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+experimental-zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-BITS-512
; ;
; VECTOR_REVERSE - masks ; VECTOR_REVERSE - masks
; ;
; FIXME: Support for mask vectors
;define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) { define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; %res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a) ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i1:
; ret <vscale x 2 x i1> %res ; RV32-BITS-UNKNOWN: # %bb.0:
;} ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
;define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) { ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; %res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a) ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; ret <vscale x 4 x i1> %res ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2
;} ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
;define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) { ; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; %res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a) ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; ret <vscale x 8 x i1> %res ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
;} ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
;define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) { ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; %res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a) ; RV32-BITS-UNKNOWN-NEXT: ret
; ret <vscale x 16 x i1> %res ;
;} ; RV32-BITS-256-LABEL: reverse_nxv2i1:
; ; RV32-BITS-256: # %bb.0:
;define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) { ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; %res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a) ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; ret <vscale x 32 x i1> %res ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
;} ; RV32-BITS-256-NEXT: csrr a0, vlenb
; ; RV32-BITS-256-NEXT: srli a0, a0, 2
;define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) { ; RV32-BITS-256-NEXT: addi a0, a0, -1
; %res = call <vscale x 64 x i1> @llvm.experimental.vector.reverse.nxv64i1(<vscale x 64 x i1> %a) ; RV32-BITS-256-NEXT: vid.v v9
; ret <vscale x 64 x i1> %res ; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
;} ; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv2i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv2i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv2i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)
ret <vscale x 2 x i1> %res
}
define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i1:
; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv4i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv4i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv4i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv4i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
ret <vscale x 4 x i1> %res
}
define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vid.v v10
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv8i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv8i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vid.v v10
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv8i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv8i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
ret <vscale x 8 x i1> %res
}
define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i1:
; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv16i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v10
; RV32-BITS-256-NEXT: vand.vi v8, v12, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv16i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v10
; RV32-BITS-512-NEXT: vand.vi v8, v12, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv16i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v10
; RV64-BITS-256-NEXT: vand.vi v8, v12, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv16i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v10
; RV64-BITS-512-NEXT: vand.vi v8, v12, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)
ret <vscale x 16 x i1> %res
}
define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i1:
; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv32i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v12
; RV32-BITS-256-NEXT: vand.vi v8, v16, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv32i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-512-NEXT: vrgather.vv v16, v8, v12
; RV32-BITS-512-NEXT: vand.vi v8, v16, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv32i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v12
; RV64-BITS-256-NEXT: vand.vi v8, v16, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv32i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-512-NEXT: vrgather.vv v16, v8, v12
; RV64-BITS-512-NEXT: vand.vi v8, v16, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
ret <vscale x 32 x i1> %res
}
define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1:
; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vid.v v8
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv64i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV32-BITS-256-NEXT: vand.vi v8, v24, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv64i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; RV32-BITS-512-NEXT: vid.v v8
; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV32-BITS-512-NEXT: vmv.v.i v16, 0
; RV32-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV32-BITS-512-NEXT: vrgather.vv v28, v16, v8
; RV32-BITS-512-NEXT: vrgather.vv v24, v20, v8
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV32-BITS-512-NEXT: vand.vi v8, v24, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vid.v v8
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv64i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV64-BITS-256-NEXT: vand.vi v8, v24, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv64i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; RV64-BITS-512-NEXT: vid.v v8
; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV64-BITS-512-NEXT: vmv.v.i v16, 0
; RV64-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; RV64-BITS-512-NEXT: vrgather.vv v28, v16, v8
; RV64-BITS-512-NEXT: vrgather.vv v24, v20, v8
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; RV64-BITS-512-NEXT: vand.vi v8, v24, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.experimental.vector.reverse.nxv64i1(<vscale x 64 x i1> %a)
ret <vscale x 64 x i1> %res
}
; ;
; VECTOR_REVERSE - integer ; VECTOR_REVERSE - integer
; ;
define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) { define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
▲ Show 20 Lines • Show All 1,062 Lines • Show Last 20 Lines