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Differential D121692

[RISCV] Add MachineMemOperand when codegen PseudoLA
AbandonedPublic

Authored by StephenFan on Mar 15 2022, 6:09 AM.

Details

Reviewers
craig.topper
asb
lewis-revill
kito-cheng
khchen
jrtc27
Summary

Issue: https://github.com/llvm/llvm-project/issues/54372

Some MachineFunctionPass like Machine-LICM pass needs to use memops information to check if this instruction is safe to move to other places.

This patch adds MachineMemOperand for global address when codegen to PseudoLA

Diff Detail

Unit TestsFailed

TimeTest
60,030 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp
60,070 msx64 debian > libFuzzer.libFuzzer::large.test

Event Timeline

StephenFan created this revision.Mar 15 2022, 6:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 15 2022, 6:09 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald Transcript
StephenFan requested review of this revision.Mar 15 2022, 6:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 15 2022, 6:09 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
StephenFan edited the summary of this revision. (Show Details)Mar 15 2022, 6:10 AM
StephenFan added a reviewer: jrtc27.Mar 15 2022, 6:18 AM
StephenFan abandoned this revision.Mar 15 2022, 6:30 AM
Harbormaster completed remote builds in B154310: Diff 415404.Mar 15 2022, 7:22 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
9 lines
test/
CodeGen/
RISCV/
35 lines

Diff 415404

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,747 Lines • ▼ Show 20 Lines if (IsLocal)
// Use PC-relative addressing to access the symbol. This generates the // Use PC-relative addressing to access the symbol. This generates the
// pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym)) // pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
// %pcrel_lo(auipc)). // %pcrel_lo(auipc)).
return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0); return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
// Use PC-relative addressing to access the GOT for this symbol, then load // Use PC-relative addressing to access the GOT for this symbol, then load
// the address from the GOT. This generates the pattern (PseudoLA sym), // the address from the GOT. This generates the pattern (PseudoLA sym),
// which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))). // which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0); MachineSDNode *LoadAddr = DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr);
MachinePointerInfo MPI =
MachinePointerInfo::getGOT(DAG.getMachineFunction());
DAG.setNodeMemRefs(LoadAddr, {DAG.getMachineFunction().getMachineMemOperand(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    DAG.setNodeMemRefs(LoadAddr, {DAG.getMachineFunction().getMachineMemOperand(
-                                 MPI, MachineMemOperand::MOLoad,
-                                 Subtarget.getXLenVT().getSizeInBits() / 8, Align(8))});
+    DAG.setNodeMemRefs(
+        LoadAddr, {DAG.getMachineFunction().getMachineMemOperand(
+                      MPI, MachineMemOperand::MOLoad,
+                      Subtarget.getXLenVT().getSizeInBits() / 8, Align(8))});
Lint: Pre-merge checks: clang-format: please reformat the code ``` - DAG.setNodeMemRefs(LoadAddr, {DAG.
MPI, MachineMemOperand::MOLoad,
Subtarget.getXLenVT().getSizeInBits() / 8, Align(8))});
return SDValue(LoadAddr, 0);
} }
switch (getTargetMachine().getCodeModel()) { switch (getTargetMachine().getCodeModel()) {
default: default:
report_fatal_error("Unsupported code model for lowering"); report_fatal_error("Unsupported code model for lowering");
case CodeModel::Small: { case CodeModel::Small: {
// Generate a sequence for accessing addresses within the first 2 GiB of // Generate a sequence for accessing addresses within the first 2 GiB of
// address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)). // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
▲ Show 20 Lines • Show All 7,873 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/pseudola-add-memop.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel -relocation-model=pic -o - %s | FileCheck --check-prefix=MIR-RV64 %s
; RUN: llc -mtriple=riscv32 -stop-after=finalize-isel -relocation-model=pic -o - %s | FileCheck --check-prefix=MIR-RV32 %s
@global = global i32 0, align 4
; MIR-RV64: %7:gpr = PseudoLA @global :: (load (s64) from got)
; MIR-RV32: %6:gpr = PseudoLA @global :: (load (s32) from got, align 8)
define void @test(i32 noundef signext %n) local_unnamed_addr #0 {
entry:
%cmp3 = icmp sgt i32 %n, 0
br i1 %cmp3, label %for.body, label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.body, %entry
ret void
for.body: ; preds = %entry, %for.body
%i.04 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%0 = load volatile i32, i32* @global, align 4, !tbaa !5
%add = add nsw i32 %0, 1
store volatile i32 %add, i32* @global, align 4, !tbaa !5
%inc = add nuw nsw i32 %i.04, 1
%cmp = icmp slt i32 %inc, %n
br i1 %cmp, label %for.body, label %for.cond.cleanup, !llvm.loop !9
}
!0 = !{i32 1, !"wchar_size", i32 4}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}