[RISCV] Split f64 undef into two i32 undefs

[• pcwang-thead]

Summary

So that no store instruction will be generated.

[frasercrmck]

This could do with some tests to show the effect on codegen.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8384

"since the ProcessImplicitDefs pass will do it for us". I don't think referring to the DEBUG_TYPE is as helpful.

[• pcwang-thead]

Address comment.

[craig.topper]

This would be more useful as a DAG combine in performDAGCombine. That would allow the integer undefs to be further simplified.

[• pcwang-thead]

Change to DAG combine.

[craig.topper]

llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

269 ↗

(On Diff #403469)

I thought the issue showed up with the ilp32 abi and the D extension, not the ilp32d abi? Please check this test case in this test file fails without the RISCVISelLowering.cpp change.

[• pcwang-thead]

Update tests.

[craig.topper]

Can we put the new test case in double-calling-conv.ll instead? I think that it already has the right command line.

[• pcwang-thead]

Move test to double-calling-conv.ll.

[frasercrmck]

Given that the description says "so that no store will be generated" I think it'd be helpful to pre-commit the test case so that this patch shows the improvement. I tested it locally and see:

define double @func_return_double_undef() nounwind {
; RV32IFD-LABEL: func_return_double_undef:
; RV32IFD:       # %bb.0:
; RV32IFD-NEXT:    addi sp, sp, -16
; RV32IFD-NEXT:    fsd ft0, 8(sp)
; RV32IFD-NEXT:    lw a0, 8(sp)
; RV32IFD-NEXT:    lw a1, 12(sp)
; RV32IFD-NEXT:    addi sp, sp, 16
; RV32IFD-NEXT:    ret
  ret double undef
}

Other than that LGTM.

[asb]

Thanks, LGTM.

[• pcwang-thead]

Rebase.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

default:
     break;
   case RISCVISD::SplitF64: {
     SDValue Op0 = N->getOperand(0);
     // If the input to SplitF64 is just BuildPairF64 then the operation is
     // redundant. Instead, use BuildPairF64's operands directly.
     if (Op0->getOpcode() == RISCVISD::BuildPairF64)
       return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
 
+    if (Op0->isUndef()) {
+      SDValue Lo = DAG.getUNDEF(MVT::i32);
+      SDValue Hi = DAG.getUNDEF(MVT::i32);
+      return DCI.CombineTo(N, Lo, Hi);
+    }
+
     SDLoc DL(N);
 
     // It's cheaper to materialise two 32-bit integers than to load a double
     // from the constant pool and transfer it to integer registers through the
     // stack.
     if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op0)) {
       APInt V = C->getValueAPF().bitcastToAPInt();
       SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32);
static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
   BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
       .addFrameIndex(FI)
       .addImm(0)
       .addMemOperand(MMOLo);
   BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
       .addFrameIndex(FI)
       .addImm(4)
       .addMemOperand(MMOHi);
   MI.eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }
 
 static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
                                                  MachineBasicBlock *BB) {
   assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
          "Unexpected instruction");
 

llvm/test/CodeGen/RISCV/double-calling-conv.ll

 ; RV32IFD-NEXT:    li a7, 0
 ; RV32IFD-NEXT:    call callee_double_stack@plt
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
   %1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
   ret double %1
 }
+
+define double @func_return_double_undef() nounwind {
+; RV32IFD-LABEL: func_return_double_undef:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    ret
+  ret double undef
+}