[RISCV] Improve i64 splat vector lowering in RV32.

[jacquesguan]

Summary

We could use vmv.v.i/vmv.v.x whose eew is 32 to lower the i64 splat vector if the i64 constant scalar could be splitted into two same i32 scalar.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2218

auto doesn't add anything here. It's more characters than MVT

2220

could -> can

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2218

Done

2220

Done

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2219

I may be missing something, but isn't VT.getVectorNumElements problematic with scalable vector types? I'm surprised this doesn't warn/crash.

Also I'm not sure whether this method should assume that VT is scalable. Should it be able to produce a fixed-vector type if passed one?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2219

Also I'm not sure whether this method should assume that VT is scalable. Should it be able to produce a fixed-vector type if passed one?

Assuming scalable is ok. Other parts of this code are creating _VL nodes which must use a scalable type.

2219

I may be missing something, but isn't VT.getVectorNumElements problematic with scalable vector types? I'm surprised this doesn't warn/crash.

It happens to work because of a FIXME in getVectorNumElements(). It just returns getVectorMinNumElements().

This code should use MVT::getVectorVT(MVT::i32, 2 * VT.getVectorElementCount()) I think

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2219

I've resolved the FIXME so this should fail now.

[jacquesguan]

Address comment.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2219

Thanks, done.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2218

Can this be MVT::getVectorVT(MVT::i32, 2 * VT.getVectorElementCount()) as I wrote in my previous comment. If not please tell me why not.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2218

It can not, because the return type of getVectorElementCount is ElementCount, and the operator * is not overloaded for it.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2218

VT.getVectorElementCount() * 2 work? I think the operator overload is there but maybe not symmetric.

[jacquesguan]

Address comment.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2218

Yes, you are right. Thanks a lot.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo,
                                    SDValue Hi, SDValue VL, SelectionDAG &DAG) {
   if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
     int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
     int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
     // If Hi constant is all the same sign bit as Lo, lower this as a custom
     // node in order to try and match RVV vector/scalar instructions.
     if ((LoC >> 31) == HiC)
       return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL);
+
+    // If vl is equal to VLMax and Hi constant is equal to Lo, we could use
+    // vmv.v.x whose EEW = 32 to lower it.
+    auto *Const = dyn_cast<ConstantSDNode>(VL);
+    if (LoC == HiC && Const && Const->getSExtValue() == RISCV::VLMaxSentinel) {
+      auto InterVT =
+          MVT::getScalableVectorVT(MVT::i32, 2 * VT.getVectorNumElements());
+      // TODO: if vl <= min(VLMAX), we could also do this. But we could not
+      // access the subtarget here now.
+      auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT, Lo, VL);
+      return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
+    }
   }
 
   // Fall back to a stack store and stride x0 vector load.
   return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Lo, Hi, VL);
 }
 
 // Called by type legalization to handle splat of i64 on RV32.
 // FIXME: We can optimize this when the type has sign or zero bits in one

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll

%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
     i32 %0)
 
   ret <vscale x 8 x i64> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64_vlmax() nounwind {
 ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64_vlmax:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    li a0, 3
-; CHECK-NEXT:    sw a0, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v8, (a0), zero
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 3
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
     i64 12884901891,
     i32 -1)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64_vlmax() nounwind {
 ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64_vlmax:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    li a0, 3
-; CHECK-NEXT:    sw a0, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v8, (a0), zero
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 3
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
     i64 12884901891,
     i32 -1)
 
   ret <vscale x 2 x i64> %a
 }
 
 define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64_vlmax() nounwind {
 ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64_vlmax:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    li a0, 3
-; CHECK-NEXT:    sw a0, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v8, (a0), zero
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 3
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
     i64 12884901891,
     i32 -1)
 
   ret <vscale x 4 x i64> %a
 }
 
 define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64_vlmax() nounwind {
 ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64_vlmax:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    li a0, 3
-; CHECK-NEXT:    sw a0, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v8, (a0), zero
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 3
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
     i64 12884901891,
     i32 -1)
 
   ret <vscale x 8 x i64> %a
 }