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Differential D117081

[RISCV] Add more i64 splat vector test.
ClosedPublic

Authored by jacquesguan on Jan 11 2022, 7:21 PM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
HsiangKai
khchen
benshi001
Commits
rG3e241353e1c6: [RISCV] Add more i64 splat vector test.
Summary

Precommit test for D117079.

Diff Detail

Event Timeline

jacquesguan created this revision.Jan 11 2022, 7:21 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 23 others. · View Herald TranscriptJan 11 2022, 7:21 PM
jacquesguan requested review of this revision.Jan 11 2022, 7:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 11 2022, 7:21 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
jacquesguan added a child revision: D117079: [RISCV] Improve i64 splat vector lowering in RV32..Jan 11 2022, 7:21 PM
craig.topper accepted this revision.Jan 11 2022, 7:42 PM

LGTM

This revision is now accepted and ready to land.Jan 11 2022, 7:42 PM
Harbormaster completed remote builds in B142817: Diff 399180.Jan 11 2022, 8:04 PM
Closed by commit rG3e241353e1c6: [RISCV] Add more i64 splat vector test. (authored by jacquesguan). · Explain WhyJan 13 2022, 10:04 PM
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rG3e241353e1c6: [RISCV] Add more i64 splat vector test..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
80 lines

Diff 399887

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll

Show First 20 Lines • Show All 718 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
i64 9, i64 9,
i32 %0) i32 %0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64_vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
i64 12884901891,
i32 -1)
ret <vscale x 1 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64_vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
i64 12884901891,
i32 -1)
ret <vscale x 2 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64_vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
i64 12884901891,
i32 -1)
ret <vscale x 4 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64_vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
i64 12884901891,
i32 -1)
ret <vscale x 8 x i64> %a
}