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[RISCV][VP] Add RVV codegen for

Authored by victor-eds on Nov 26 2021, 4:11 AM.



Lower instrinsic to VSELECT_VL.

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victor-eds created this revision.Nov 26 2021, 4:11 AM
victor-eds requested review of this revision.Nov 26 2021, 4:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 26 2021, 4:11 AM
rogfer01 accepted this revision.Dec 1 2021, 11:36 PM

Thanks for the patch @victor-eds!


After this change lands, the only lowering missing for will be for i1 vectors. AFAICT rvv doesn't have specific instructions for that but a sequence of vm<op>.mm and something like this (or a better sequence) should do. We can't fully honour the vl in that case, but I think this is OK as VP doesn't demand us to do that.

(@craig.topper reading the spec I realised that vmerge (perhaps others?) doesn't seem to care about ma/mu only ta/tu so maybe this can be exploited when inserting vsetvl)

This revision is now accepted and ready to land.Dec 1 2021, 11:36 PM
This revision was automatically updated to reflect the committed changes.