This is an archive of the discontinued LLVM Phabricator instance.

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Table of Contentst

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clang/
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test/
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CodeGen/RISCV/
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RISCV/
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riscv-attr-builtin-alias-err.c
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riscv-attr-builtin-alias.c
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riscv-inline-asm-rvv.c
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riscv-v-debuginfo.c
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riscv-v-lifetime.cpp
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rvv-intrinsics-overloaded/
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vaadd.c
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vadc.c
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vadd.c
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vand.c
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vasub.c
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vcompress.c
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vdiv.c
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vfabs.c
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vfadd.c
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vfclass.c
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vfcvt.c
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vfdiv.c
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vfirst.c
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vfmacc.c
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vfmadd.c
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vfmax.c
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vfmerge.c
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vfmin.c
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vfmsac.c
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vfmsub.c
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vfmul.c
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vfmv.c
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vfncvt.c
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vfneg.c
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vfnmacc.c
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vfnmadd.c
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vfnmsac.c
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vfnmsub.c
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vfrdiv.c
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vfrec7.c
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vfredmax.c
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vfredmin.c
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vfredsum.c
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vfrsqrt7.c
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vfrsub.c
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vfsgnj.c
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vfslide1down.c
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vfslide1up.c
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vfsqrt.c
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vfsub.c
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vfwadd.c
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vfwcvt.c
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vfwmacc.c
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vfwmsac.c
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vfwmul.c
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vfwnmacc.c
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vfwnmsac.c
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vfwredsum.c
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vfwsub.c
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vget.c
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vid.c
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viota.c
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vle.c
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vlmul.c
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vloxei.c
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vloxseg.c
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vlse.c
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vlseg.c
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vlsegff.c
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vlsseg.c
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vluxei.c
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vluxseg.c
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vmacc.c
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vmadc.c
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vmadd.c
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vmand.c
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vmax.c
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vmerge.c
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vmfeq.c
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vmfge.c
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vmfgt.c
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vmfle.c
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vmflt.c
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vmfne.c
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vmin.c
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vmmv.c
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vmnand.c
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vmnor.c
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vmnot.c
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vmor.c
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vmsbc.c
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vmsbf.c
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vmseq.c
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vmsge.c
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vmsgt.c
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vmsif.c
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vmsle.c
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vmslt.c
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vmsne.c
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vmsof.c
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vmul.c
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vmv.c
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vmxnor.c
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vmxor.c
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vnclip.c
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vncvt.c
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vneg.c
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vnmsac.c
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vnmsub.c
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vnot.c
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vnsra.c
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vnsrl.c
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vor.c
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vpopc.c
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vredand.c
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vredmax.c
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vredmin.c
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vredor.c
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vredsum.c
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vredxor.c
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vreinterpret.c
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vrem.c
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vrgather.c
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vrsub.c
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vsadd.c
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vsbc.c
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vse.c
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vset.c
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vsext.c
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vslide1down.c
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vslide1up.c
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vslidedown.c
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vslideup.c
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vsll.c
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vsmul.c
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vsoxei.c
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vsoxseg.c
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vsra.c
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vsrl.c
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vsse.c
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vsseg.c
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vssra.c
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vssrl.c
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vssseg.c
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vssub.c
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vsub.c
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vsuxei.c
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vsuxseg.c
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vwadd.c
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vwcvt.c
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vwmacc.c
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vwmul.c
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vwredsum.c
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vwsub.c
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vxor.c
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vzext.c
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rvv-intrinsics/
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vaadd.c
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vadc.c
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vadd.c
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vand.c
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vasub.c
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vcompress.c
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vdiv.c
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vfabs.c
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vfadd.c
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vfclass.c
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vfcvt.c
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vfdiv.c
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vfirst.c
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vfmacc.c
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vfmadd.c
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vfmax.c
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vfmerge.c
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vfmin.c
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vfmsac.c
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vfmsub.c
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vfmul.c
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vfmv.c
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vfncvt.c
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vfneg.c
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vfnmacc.c
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vfnmadd.c
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vfnmsac.c
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vfnmsub.c
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vfrdiv.c
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vfrec7.c
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vfredmax.c
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vfredmin.c
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vfredsum.c
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vfrsqrt7.c
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vfrsub.c
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vfsgnj.c
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vfslide1down.c
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vfslide1up.c
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vfsqrt.c
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vfsub.c
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vfwadd.c
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vfwcvt.c
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vfwmacc.c
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vfwmsac.c
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vfwmul.c
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vfwnmacc.c
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vfwnmsac.c
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vfwredosum.c
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vfwsub.c
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vget.c
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vid.c
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viota.c
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vle.c
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vleff.c
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vlmul.c
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vloxei.c
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vloxseg.c
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vlse.c
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vlseg.c
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vlsegff.c
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vlsseg.c
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vluxei.c
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vluxseg.c
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vmacc.c
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vmadc.c
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vmadd.c
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vmand.c
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vmax.c
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vmclr.c
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vmerge.c
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vmfeq.c
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vmfge.c
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vmfgt.c
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vmfle.c
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vmflt.c
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vmfne.c
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vmin.c
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vmmv.c
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vmnand.c
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vmnor.c
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vmnot.c
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vmor.c
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vmsbc.c
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vmsbf.c
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vmseq.c
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vmset.c
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vmsge.c
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vmsgt.c
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vmsif.c
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vmsle.c
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vmslt.c
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vmsne.c
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vmsof.c
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vmul.c
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vmv.c
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vmxnor.c
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vmxor.c
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vnclip.c
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vncvt.c
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vneg.c
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vnmsac.c
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vnmsub.c
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vnot.c
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vnsra.c
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vnsrl.c
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vor.c
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vpopc.c
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vredand.c
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vredmax.c
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vredmin.c
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vredor.c
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vredsum.c
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vredxor.c
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vreinterpret.c
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vrem.c
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vrgather.c
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vrsub.c
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vsadd.c
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vsbc.c
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vse.c
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vset.c
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vsetvl.c
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vsetvlmax.c
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vsext.c
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vslide1down.c
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vslide1up.c
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vslidedown.c
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vslideup.c
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vsll.c
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vsmul.c
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vsoxei.c
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vsoxseg.c
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vsra.c
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vsrl.c
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vsse.c
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vsseg.c
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vssra.c
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vssrl.c
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vssseg.c
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vssub.c
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vsub.c
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vsuxei.c
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vsuxseg.c
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vundefined.c
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vwadd.c
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vwcvt.c
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vwmacc.c
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vwmul.c
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vwredsum.c
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vwsub.c
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vxor.c
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vzext.c
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rvv_errors.c
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Driver/
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riscv-arch.c
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Preprocessor/
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riscv-target-features.c
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utils/TableGen/
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TableGen/
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RISCVVEmitter.cpp
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llvm/lib/Support/
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lib/
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Support/
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RISCVISAInfo.cpp

Differential D112613

[Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction
ClosedPublic

Authored by eopXD on Oct 27 2021, 4:47 AM.

Download Raw Diff

Details

Reviewers

kito.cheng
khchen
craig.topper
kito-cheng

Commits

rG14c5fd920b0e: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

Summary

According to v-spec v1.0, zve-32x is the new minimum extension to include
to have vector instructions.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

eopXD created this revision.Oct 27 2021, 4:47 AM

Herald added subscribers: achieveartificialintelligence, vkmr, frasercrmck and 26 others. · View Herald TranscriptOct 27 2021, 4:47 AM

eopXD requested review of this revision.Oct 27 2021, 4:47 AM

Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptOct 27 2021, 4:47 AM

Herald added subscribers: llvm-commits, cfe-commits, MaskRay. · View Herald Transcript

Harbormaster completed remote builds in B130918: Diff 382610.Oct 27 2021, 4:47 AM

eopXD added a parent revision: D112408: [RISCV] Add the zve extension according to the v1.0 spec.Oct 27 2021, 4:51 AM

eopXD retitled this revision from [RISCV][RVV] Change TARGET_BUILTIN require to zve32x to [WIP][RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction.

eopXD edited the summary of this revision. (Show Details)Oct 27 2021, 4:55 AM

Update code.

Harbormaster completed remote builds in B130920: Diff 382615.Oct 27 2021, 5:50 AM

Rebase.

Herald added subscribers: VincentWu, luke957. · View Herald TranscriptNov 1 2021, 11:07 PM

Harbormaster completed remote builds in B131886: Diff 383977.Nov 1 2021, 11:47 PM

Follow clang-format.

eopXD added a child revision: D112986: [Clang][RISCV] Restrict rvv builtins with zve macros.Nov 1 2021, 11:57 PM

eopXD retitled this revision from [WIP][RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction to [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction.Nov 2 2021, 12:09 AM

eopXD edited the summary of this revision. (Show Details)

Harbormaster completed remote builds in B131892: Diff 383983.Nov 2 2021, 12:32 AM

The title of this patch isn't descriptive of the changes in this patch. Based on the title I would only expect changes to RISCVEmitter.cpp. Can you clarify the title?

craig.topper added inline comments.Nov 5 2021, 1:17 PM

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
3	Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x imply zve32x?

eopXD edited parent revisions, added: D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap; removed: D112408: [RISCV] Add the zve extension according to the v1.0 spec.Nov 6 2021, 2:12 AM

eopXD added inline comments.Nov 6 2021, 2:14 AM

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
3	Just added D113336 to resolve this. I will rebase this patch and change test cases.

Rebase.

Harbormaster completed remote builds in B132843: Diff 385276.Nov 6 2021, 7:48 AM

Update code.

eopXD marked an inline comment as done.Nov 6 2021, 7:56 AM

eopXD added inline comments.

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
3	Rebased.

Harbormaster completed remote builds in B132845: Diff 385278.Nov 6 2021, 8:57 AM

eopXD edited child revisions, added: D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0; removed: D112986: [Clang][RISCV] Restrict rvv builtins with zve macros.Jan 19 2022, 11:57 PM

eopXD mentioned this in D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap.Jan 20 2022, 12:51 AM

eopXD edited the summary of this revision. (Show Details)Jan 20 2022, 1:36 AM

Rebase.

eopXD removed a parent revision: D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap.Jan 20 2022, 1:48 AM

Rebase.

LGTM but I don't have full scope on the builtins side of things. I'd also add a missing word to the title: "Change TARGET_BUILTIN to require ..."

Harbormaster completed remote builds in B144518: Diff 401554.Jan 20 2022, 3:04 AM

Apply @frasercrmck 's suggested title, thanks!

eopXD retitled this revision from [RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction to [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction.Jan 20 2022, 4:09 AM

LGTM

This revision is now accepted and ready to land.Jan 20 2022, 6:35 AM

Closed by commit rG14c5fd920b0e: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction (authored by eopXD). · Explain WhyJan 20 2022, 6:53 AM

This revision was automatically updated to reflect the committed changes.

eopXD added a commit: rG14c5fd920b0e: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction.

Revision Contents

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clang/

test/

CodeGen/

RISCV/

riscv-attr-builtin-alias-err.c

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riscv-attr-builtin-alias.c

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riscv-inline-asm-rvv.c

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riscv-v-debuginfo.c

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riscv-v-lifetime.cpp

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rvv-intrinsics-overloaded/

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rvv-intrinsics/

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Driver/

riscv-arch.c

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Preprocessor/

riscv-target-features.c

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utils/

TableGen/

RISCVVEmitter.cpp

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llvm/

lib/

Support/

RISCVISAInfo.cpp

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Diff 382615

clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c

	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: not %clang_cc1 -triple riscv64 -fsyntax-only -verify \			// RUN: not %clang_cc1 -triple riscv64 -fsyntax-only -verify \
	// RUN: -target-feature +experimental-v %s 2>&1 \			// RUN: -target-feature +experimental-zve32x %s 2>&1 \
	// RUN: \| FileCheck %s			// RUN: \| FileCheck %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	#define __rvv_generic \			#define __rvv_generic \
	static inline __attribute__((__always_inline__, __nodebug__))			static inline __attribute__((__always_inline__, __nodebug__))

	__rvv_generic			__rvv_generic
	__attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv_i8m1)))			__attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv_i8m1)))
	vint8m1_t vadd_generic (vint8m1_t op0, vint8m1_t op1, size_t op2);			vint8m1_t vadd_generic (vint8m1_t op0, vint8m1_t op1, size_t op2);

	// CHECK: passing 'vint8m2_t' (aka '__rvv_int8m2_t') to parameter of incompatible type 'vint8m1_t'			// CHECK: passing 'vint8m2_t' (aka '__rvv_int8m2_t') to parameter of incompatible type 'vint8m1_t'
	vint8m2_t test(vint8m2_t op0, vint8m2_t op1, size_t vl) {			vint8m2_t test(vint8m2_t op0, vint8m2_t op1, size_t vl) {
	vint8m2_t ret = vadd_generic(op0, op1, vl);			vint8m2_t ret = vadd_generic(op0, op1, vl);
	return ret;			return ret;
	}			}

clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -emit-llvm -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -emit-llvm -target-feature +experimental-zve32x \
	// RUN: %s -o - \			// RUN: %s -o - \
	// RUN: \| FileCheck %s			// RUN: \| FileCheck %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	#define __rvv_generic \			#define __rvv_generic \
	static inline __attribute__((__always_inline__, __nodebug__))			static inline __attribute__((__always_inline__, __nodebug__))

	Show All 25 Lines

clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

	// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zve32x \
	// RUN: -O2 -emit-llvm %s -o - \			// RUN: -O2 -emit-llvm %s -o - \
	// RUN: \| FileCheck %s			// RUN: \| FileCheck %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x \
	// RUN: -O2 -emit-llvm %s -o - \			// RUN: -O2 -emit-llvm %s -o - \
	// RUN: \| FileCheck %s			// RUN: \| FileCheck %s

	// Test RISC-V V-extension specific inline assembly constraints.			// Test RISC-V V-extension specific inline assembly constraints.
	#include <riscv_vector.h>			#include <riscv_vector.h>

	void test_v_reg() {			void test_v_reg() {
	asm volatile(			asm volatile(
	Show All 24 Lines

clang/test/CodeGen/RISCV/riscv-v-debuginfo.c

	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +experimental-zve32x -target-feature +experimental-zve32f \
	// RUN: -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \			// RUN: -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \
	// RUN: \| FileCheck --check-prefix=DEBUGINFO %s			// RUN: \| FileCheck --check-prefix=DEBUGINFO %s
	#include <stdint.h>			#include <stdint.h>

	__rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2) {			__rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2) {
	__rvv_int16m2_t ret;			__rvv_int16m2_t ret;
	return ret;			return ret;
	}			}
	Show All 19 Lines

clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp

	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v \			// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-zve32x \
	// RUN: -O1 -disable-llvm-passes -emit-llvm -o - %s \| FileCheck %s			// RUN: -O1 -disable-llvm-passes -emit-llvm -o - %s \| FileCheck %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	vint32m1_t Baz();			vint32m1_t Baz();

	// CHECK-LABEL: @_Z4Testv(			// CHECK-LABEL: @_Z4Testv(
	// CHECK-NEXT: entry:			// CHECK-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				craig.topperUnsubmitted Done Reply Inline Actions Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x imply zve32x? craig.topper: Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x imply zve32x?
				eopXDAuthorUnsubmitted Done Reply Inline Actions Just added D113336 to resolve this. I will rebase this patch and change test cases. eopXD: Just added D113336 to resolve this. I will rebase this patch and change test cases.
				eopXDAuthorUnsubmitted Done Reply Inline Actions Rebased. eopXD: Rebased.

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vaadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vaadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vadc_vvm_i8mf8(			// CHECK-RV64-LABEL: @test_vadc_vvm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vand_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vand_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vasub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vasub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vcompress_vm_i8mf8(			// CHECK-RV64-LABEL: @test_vcompress_vm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.]], <vscale x 1 x i8> [[SRC:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.]], <vscale x 1 x i8> [[SRC:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vdiv_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vdiv_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfabs_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfabs_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \			// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(			// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.]], <vscale x 1 x half> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.]], <vscale x 1 x half> [[OP2:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2(			// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2(			// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfdiv_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfdiv_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfdiv.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfdiv.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfirst_m_b1(			// CHECK-RV64-LABEL: @test_vfirst_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret i64 [[TMP0]]			// CHECK-RV64-NEXT: ret i64 [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmax_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmax_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmerge_vfm_f32mf2(			// CHECK-RV64-LABEL: @test_vfmerge_vfm_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmin_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmin_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmul_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmul_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmul.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmul.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32(			// CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> [[SRC:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> [[SRC:%.]])
	// CHECK-RV64-NEXT: ret float [[TMP0]]			// CHECK-RV64-NEXT: ret float [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4(			// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfneg_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfneg_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrdiv_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfrdiv_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1(			// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1(			// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1(			// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 383 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrsub_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfrsub_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfsgnj_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfsgnj_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnj.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnj.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfsub_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfsub_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwadd_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwadd_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwmul_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwmul_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1(			// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwsub_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwsub_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	▲ Show 20 Lines • Show All 315 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(			// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.]], i64 0)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.]], i64 0)
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(			// CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(			// CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i1> [[OP1:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i1> [[OP1:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_m(			// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]], i64 0)			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]], i64 0)
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4(			// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.]], i64 0)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.]], i64 0)
	// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64(i8 [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vloxseg2.nxv1i8.nxv1i8.i64(i8 [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8_m(			// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]], i64 0)			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8>* [[TMP0]], i64 [[BSTRIDE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]], i64 0)
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8_m(			// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8_m(
	// CHECK-RV32-NEXT: entry:			// CHECK-RV32-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8_m(			// CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8_m(
	// CHECK-RV32-NEXT: entry:			// CHECK-RV32-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf8_m(			// CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf8_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlsseg2.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.]], <vscale x 1 x i8> [[MASKEDOFF1:%.]], i8 [[BASE:%.]], i64 [[BSTRIDE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]], i64 0)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlsseg2.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF0:%.]], <vscale x 1 x i8> [[MASKEDOFF1:%.]], i8 [[BASE:%.]], i64 [[BSTRIDE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]], i64 0)
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64(i8 [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vluxseg2.nxv1i8.nxv1i8.i64(i8 [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmadc_vvm_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmadc_vvm_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmand_mm_b1(			// CHECK-RV64-LABEL: @test_vmand_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmax_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmax_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmerge_vvm_i8mf8(			// CHECK-RV64-LABEL: @test_vmerge_vvm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmin_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmin_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmmv_m_b1(			// CHECK-RV64-LABEL: @test_vmmv_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmnand_mm_b1(			// CHECK-RV64-LABEL: @test_vmnand_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmnor_mm_b1(			// CHECK-RV64-LABEL: @test_vmnor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmnot_m_b1(			// CHECK-RV64-LABEL: @test_vmnot_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmor_mm_b1(			// CHECK-RV64-LABEL: @test_vmor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsbc_vvm_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsbc_vvm_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsbf_m_b1(			// CHECK-RV64-LABEL: @test_vmsbf_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmseq_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmseq_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsge_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsge_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsgt_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsgt_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsif_m_b1(			// CHECK-RV64-LABEL: @test_vmsif_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsle_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsle_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmslt_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmslt_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsne_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsne_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsof_m_b1(			// CHECK-RV64-LABEL: @test_vmsof_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmul_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmul_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8(			// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmxnor_mm_b1(			// CHECK-RV64-LABEL: @test_vmxnor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmxor_mm_b1(			// CHECK-RV64-LABEL: @test_vmxor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnclip_wv_i8mf8(			// CHECK-RV64-LABEL: @test_vnclip_wv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vncvt_x_x_w_i8mf8(			// CHECK-RV64-LABEL: @test_vncvt_x_x_w_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i16> [[SRC:%.]], i64 0, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i16> [[SRC:%.]], i64 0, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 535 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vneg_v_i8mf8(			// CHECK-RV64-LABEL: @test_vneg_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 0, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 0, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	▲ Show 20 Lines • Show All 392 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnot_v_i8mf8(			// CHECK-RV64-LABEL: @test_vnot_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 -1, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 -1, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnsra_wv_i8mf8(			// CHECK-RV64-LABEL: @test_vnsra_wv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnsrl_wv_u8mf8(			// CHECK-RV64-LABEL: @test_vnsrl_wv_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vor_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vor_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vpopc_m_b1(			// CHECK-RV64-LABEL: @test_vpopc_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vpopc.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vpopc.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret i64 [[TMP0]]			// CHECK-RV64-NEXT: ret i64 [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredand_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredand_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredmax_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredmax_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredmin_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredmin_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredor_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredor_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 918 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredsum_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredsum_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 918 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredxor_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredxor_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 918 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vreinterpret.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8(			// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC:%.*]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC:%.*]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vrem_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vrem_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vrsub_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vrsub_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsbc_vvm_i8mf8(			// CHECK-RV64-LABEL: @test_vsbc_vvm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vse8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vse8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(			// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.]], <vscale x 8 x i8> [[VAL:%.*]], i64 0)
	// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4(			// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsll_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsll_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsmul_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsmul_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsoxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsoxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c

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	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsoxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsoxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsra_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsra_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsrl_vv_u8mf8(			// CHECK-RV64-LABEL: @test_vsrl_vv_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[BSTRIDE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[BSTRIDE:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsseg2e8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsseg2e8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssra_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vssra_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssrl_vv_u8mf8(			// CHECK-RV64-LABEL: @test_vssrl_vv_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssseg2e8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vssseg2e8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], i64 [[BSTRIDE:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], i64 [[BSTRIDE:%.]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vssub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsuxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsuxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsuxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsuxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[V0:%.]], <vscale x 1 x i8> [[V1:%.]], i8* [[BASE:%.]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwadd_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwadd_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwcvt_x_x_v_i16mf4(			// CHECK-RV64-LABEL: @test_vwcvt_x_x_v_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 0, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 0, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf8_i16m1(			// CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf8_i16m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 4 x i16> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 4 x i16> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwsub_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwsub_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vxor_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vxor_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4(			// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vaadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vaadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vadc_vvm_i8mf8(			// CHECK-RV64-LABEL: @test_vadc_vvm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	▲ Show 20 Lines • Show All 1,580 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vand_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vand_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vasub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vasub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vcompress_vm_i8mf8(			// CHECK-RV64-LABEL: @test_vcompress_vm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.]], <vscale x 1 x i8> [[SRC:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.]], <vscale x 1 x i8> [[SRC:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vdiv_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vdiv_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfabs_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfabs_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \			// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(			// CHECK-RV64-LABEL: @test_vfadd_vv_f16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.]], <vscale x 1 x half> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.]], <vscale x 1 x half> [[OP2:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2(			// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2(			// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfdiv_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfdiv_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfdiv.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfdiv.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfirst_m_b1(			// CHECK-RV64-LABEL: @test_vfirst_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret i64 [[TMP0]]			// CHECK-RV64-NEXT: ret i64 [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 580 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmax_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmax_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmerge_vfm_f32mf2(			// CHECK-RV64-LABEL: @test_vfmerge_vfm_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmin_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmin_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmul_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfmul_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmul.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmul.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2(			// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(float [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(float [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4(			// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfneg_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfneg_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 581 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
	▲ Show 20 Lines • Show All 581 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrdiv_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfrdiv_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1(			// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1(			// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1(			// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfrsub_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfrsub_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.]], float [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfsgnj_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfsgnj_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnj.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsgnj.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2(			// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfsub_vv_f32mf2(			// CHECK-RV64-LABEL: @test_vfsub_vv_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwadd_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwadd_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2(			// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwmul_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwmul_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1(			// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vfwsub_vv_f64m1(			// CHECK-RV64-LABEL: @test_vfwsub_vv_f64m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(			// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.]], i64 8)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.]], i64 8)
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vid_v_u8mf8(			// CHECK-RV64-LABEL: @test_vid_v_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_viota_m_u8mf8(			// CHECK-RV64-LABEL: @test_viota_m_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vle8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vle8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8(			// CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4(			// CHECK-RV64-LABEL: @test_vlmul_ext_v_i8mf8_i8mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.]], i64 0)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> undef, <vscale x 1 x i8> [[OP1:%.]], i64 0)
	// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vloxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vloxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vlse8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], i64 [[BSTRIDE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], i64 [[BSTRIDE:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8(			// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8(
	// CHECK-RV32-NEXT: entry:			// CHECK-RV32-NEXT: entry:
	▲ Show 20 Lines • Show All 14,573 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
	// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \			// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
	// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8(			// CHECK-RV32-LABEL: @test_vlseg2e8ff_v_i8mf8(
	// CHECK-RV32-NEXT: entry:			// CHECK-RV32-NEXT: entry:
	▲ Show 20 Lines • Show All 16,381 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vlsseg2e8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	▲ Show 20 Lines • Show All 8,189 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP1:%.]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vluxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	▲ Show 20 Lines • Show All 32,403 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmadc_vvm_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmadc_vvm_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[CARRYIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmand_mm_b1(			// CHECK-RV64-LABEL: @test_vmand_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmax_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmax_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmclr_m_b1(			// CHECK-RV64-LABEL: @test_vmclr_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmerge_vvm_i8mf8(			// CHECK-RV64-LABEL: @test_vmerge_vvm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfeq_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfge_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfgt_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfle_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmflt_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64(			// CHECK-RV64-LABEL: @test_vmfne_vv_f32mf2_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x float> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmin_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmin_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmmv_m_b1(			// CHECK-RV64-LABEL: @test_vmmv_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmnand_mm_b1(			// CHECK-RV64-LABEL: @test_vmnand_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmnor_mm_b1(			// CHECK-RV64-LABEL: @test_vmnor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmnot_m_b1(			// CHECK-RV64-LABEL: @test_vmnot_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmor_mm_b1(			// CHECK-RV64-LABEL: @test_vmor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsbc_vvm_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsbc_vvm_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsbf_m_b1(			// CHECK-RV64-LABEL: @test_vmsbf_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmseq_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmseq_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmset_m_b1(			// CHECK-RV64-LABEL: @test_vmset_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsge_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsge_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsgt_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsgt_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsif_m_b1(			// CHECK-RV64-LABEL: @test_vmsif_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsle_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsle_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmslt_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmslt_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsne_vv_i8mf8_b64(			// CHECK-RV64-LABEL: @test_vmsne_vv_i8mf8_b64(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmsof_m_b1(			// CHECK-RV64-LABEL: @test_vmsof_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmul_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vmul_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8(			// CHECK-RV64-LABEL: @test_vmv_v_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmxnor_mm_b1(			// CHECK-RV64-LABEL: @test_vmxnor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vmxor_mm_b1(			// CHECK-RV64-LABEL: @test_vmxor_mm_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], <vscale x 64 x i1> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnclip_wv_i8mf8(			// CHECK-RV64-LABEL: @test_vnclip_wv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vncvt_x_x_w_i8mf8(			// CHECK-RV64-LABEL: @test_vncvt_x_x_w_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i16> [[SRC:%.]], i64 0, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i16> [[SRC:%.]], i64 0, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vneg_v_i8mf8(			// CHECK-RV64-LABEL: @test_vneg_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 0, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 0, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnot_v_i8mf8(			// CHECK-RV64-LABEL: @test_vnot_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 -1, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 -1, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnsra_wv_i8mf8(			// CHECK-RV64-LABEL: @test_vnsra_wv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vnsrl_wv_u8mf8(			// CHECK-RV64-LABEL: @test_vnsrl_wv_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vor_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vor_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vpopc_m_b1(			// CHECK-RV64-LABEL: @test_vpopc_m_b1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vpopc.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call i64 @llvm.riscv.vpopc.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret i64 [[TMP0]]			// CHECK-RV64-NEXT: ret i64 [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredand_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredand_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredmax_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredmax_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredmin_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredmin_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredor_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredor_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredsum_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredsum_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 918 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vredxor_vs_i8mf8_i8m1(			// CHECK-RV64-LABEL: @test_vredxor_vs_i8mf8_i8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 8 x i8> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 918 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8(			// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC:%.*]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC:%.*]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vrem_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vrem_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
	▲ Show 20 Lines • Show All 1,578 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	▲ Show 20 Lines • Show All 3,523 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vrsub_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vrsub_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.]], i8 [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsadd_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsadd_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsbc_vvm_i8mf8(			// CHECK-RV64-LABEL: @test_vsbc_vvm_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], <vscale x 1 x i1> [[BORROWIN:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vse8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vse8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[VL:%.*]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(			// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)
	// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -emit-llvm -o - %s \
	// RUN: \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsetvl_e8m1(			// CHECK-RV64-LABEL: @test_vsetvl_e8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[AVL_ADDR:%.*]] = alloca i64, align 8			// CHECK-RV64-NEXT: [[AVL_ADDR:%.*]] = alloca i64, align 8
	// CHECK-RV64-NEXT: store i64 [[AVL:%.]], i64 [[AVL_ADDR]], align 8			// CHECK-RV64-NEXT: store i64 [[AVL:%.]], i64 [[AVL_ADDR]], align 8
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -emit-llvm -o - %s \
	// RUN: \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsetvlmax_e8m1(			// CHECK-RV64-LABEL: @test_vsetvlmax_e8m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)			// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
	// CHECK-RV64-NEXT: ret i64 [[TMP0]]			// CHECK-RV64-NEXT: ret i64 [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4(			// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(			// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsll_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsll_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsmul_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsmul_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsoxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsoxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
	▲ Show 20 Lines • Show All 4,635 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsoxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsoxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsra_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsra_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsrl_vv_u8mf8(			// CHECK-RV64-LABEL: @test_vsrl_vv_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsse8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[BSTRIDE:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], i64 [[BSTRIDE:%.]], i64 [[VL:%.]])
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsseg2e8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsseg2e8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	▲ Show 20 Lines • Show All 4,065 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssra_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vssra_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssrl_vv_u8mf8(			// CHECK-RV64-LABEL: @test_vssrl_vv_u8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[SHIFT:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssseg2e8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vssseg2e8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	▲ Show 20 Lines • Show All 4,065 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vssub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vssub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsub_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vsub_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsuxei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsuxei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>			// CHECK-RV64-NEXT: [[TMP0:%.]] = bitcast i8 [[BASE:%.]] to <vscale x 1 x i8>
	// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VALUE:%.]], <vscale x 1 x i8> [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.]], i64 [[VL:%.]])
	▲ Show 20 Lines • Show All 4,635 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x \
	// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \			// RUN: -target-feature +experimental-zfh -target-feature +experimental-v \
	// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \			// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
	// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vsuxseg2ei8_v_i8mf8(			// CHECK-RV64-LABEL: @test_vsuxseg2ei8_v_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \			// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
	// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \			// RUN: -target-feature +experimental-zve32x -target-feature +experimental-zve64x -target-feature +experimental-v -target-feature +experimental-zfh \
	// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vundefined_i8mf8(			// CHECK-RV64-LABEL: @test_vundefined_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> undef			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> undef
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwadd_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwadd_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwcvt_x_x_v_i16mf4(			// CHECK-RV64-LABEL: @test_vwcvt_x_x_v_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 0, i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 0, i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf8_i16m1(			// CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf8_i16m1(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 4 x i16> [[SCALAR:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 1 x i8> [[VECTOR:%.]], <vscale x 4 x i16> [[SCALAR:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vwsub_vv_i16mf4(			// CHECK-RV64-LABEL: @test_vwsub_vv_i16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vxor_vv_i8mf8(			// CHECK-RV64-LABEL: @test_vxor_vv_i8mf8(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[OP2:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c

	// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py			// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
	// REQUIRES: riscv-registered-target			// REQUIRES: riscv-registered-target
	// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s			// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s

	#include <riscv_vector.h>			#include <riscv_vector.h>

	// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4(			// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[VL:%.*]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
	//			//
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clang/test/CodeGen/RISCV/rvv_errors.c

	// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +experimental-v -fsyntax-only -verify			// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +f -target-feature +d -target-feature +experimental-zve32x -target-feature +experimental-v -fsyntax-only -verify

	void test() {			void test() {
	__builtin_rvv_vsetvli(1, 7, 0); // expected-error {{argument value 7 is outside the valid range [0, 3]}}			__builtin_rvv_vsetvli(1, 7, 0); // expected-error {{argument value 7 is outside the valid range [0, 3]}}
	__builtin_rvv_vsetvlimax(-1, 0); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 3]}}			__builtin_rvv_vsetvlimax(-1, 0); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
	__builtin_rvv_vsetvli(1, 0, 4); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}			__builtin_rvv_vsetvli(1, 0, 4); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}
	__builtin_rvv_vsetvlimax(0, 4); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}			__builtin_rvv_vsetvlimax(0, 4); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}
	__builtin_rvv_vsetvli(1, 0, 8); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}			__builtin_rvv_vsetvli(1, 0, 8); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}
	__builtin_rvv_vsetvlimax(0, -1); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}			__builtin_rvv_vsetvlimax(0, -1); // expected-error {{LMUL argument must be in the range [0,3] or [5,7]}}
	}			}

clang/test/Driver/riscv-arch.c

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	// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
	// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s			// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
	// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'			// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 -menable-experimental-extensions -### %s \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 -menable-experimental-extensions -### %s \
	// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s			// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
	// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"			// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"

	// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32ifdv -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
	// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'			// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32ifdv'
	// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'			// RV32-EXPERIMENTAL-V-NOFLAG: requires '-menable-experimental-extensions'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
	// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'			// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
	// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension 'v'			// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension 'v'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32ifdv0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
	// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"			// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh -### %s \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh -### %s \
	// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH-NOFLAG %s			// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH-NOFLAG %s
	// RV32-EXPERIMENTAL-ZFH-NOFLAG: error: invalid arch name 'rv32izfh'			// RV32-EXPERIMENTAL-ZFH-NOFLAG: error: invalid arch name 'rv32izfh'
	// RV32-EXPERIMENTAL-ZFH-NOFLAG: requires '-menable-experimental-extensions'			// RV32-EXPERIMENTAL-ZFH-NOFLAG: requires '-menable-experimental-extensions'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 -menable-experimental-extensions -### %s \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 -menable-experimental-extensions -### %s \
	// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s			// RUN: -fsyntax-only 2>&1 \| FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
	// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"			// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 \| \
				// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvamo -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
	// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'			// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izve32x0p10_zvamo'
	// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'			// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvamo0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
	// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'			// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izve32x0p10_zvamo0p1'
	// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for experimental extension 'zvamo'			// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for experimental extension 'zvamo'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvamo0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
	// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"			// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvlsseg -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
	// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg'			// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izve32x0p10_zvlsseg'
	// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions'			// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
	// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izvlsseg0p1'			// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izve32x0p10_zvlsseg0p1'
	// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg'			// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
	// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"			// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvl32b -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
	// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izvl32b0p10'			// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izve32x0p10_zvl32b'
	// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'			// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s
	// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izvl32b0p1'			// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izve32x0p10_zvl32b0p1'
	// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension			// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension

	// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \			// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32x0p10_zvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 \| \
	// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s			// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s
	// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"			// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"

clang/test/Preprocessor/riscv-target-features.c

	Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
	// RUN: -o - \| FileCheck --check-prefix=CHECK-ZBT-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-ZBT-EXT %s
	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izbt0p93 -x c -E -dM %s \			// RUN: -march=rv64izbt0p93 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-ZBT-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-ZBT-EXT %s
	// CHECK-ZBT-NOT: __riscv_b			// CHECK-ZBT-NOT: __riscv_b
	// CHECK-ZBT-EXT: __riscv_zbt 93000			// CHECK-ZBT-EXT: __riscv_zbt 93000

	// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv32iv0p10 -x c -E -dM %s \			// RUN: -march=rv32ifdv0p10 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s
	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64iv0p10 -x c -E -dM %s \			// RUN: -march=rv64ifdv0p10 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s
	// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv32izvlsseg0p10 -x c -E -dM %s \			// RUN: -march=rv32izve32x0p10_zvlsseg0p10 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s
	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv32izvlsseg0p10 -x c -E -dM %s \			// RUN: -march=rv64izve32x0p10_zvlsseg0p10 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-V-EXT %s
	// CHECK-V-EXT: __riscv_v 10000			// CHECK-V-EXT: __riscv_v 10000
	// CHECK-V-EXT: __riscv_vector 1			// CHECK-V-EXT: __riscv_vector 1
	// CHECK-V-EXT: __riscv_zvlsseg 10000			// CHECK-V-EXT: __riscv_zvlsseg 10000

	// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv32izvamo0p10 -x c -E -dM %s \			// RUN: -march=rv32izve32x0p10_zvamo0p10 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-ZVAMO-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-ZVAMO-EXT %s
	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv32izvamo0p10 -x c -E -dM %s \			// RUN: -march=rv32izve32x0p10_zvamo0p10 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-ZVAMO-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-ZVAMO-EXT %s
	// CHECK-ZVAMO-EXT: __riscv_v 10000			// CHECK-ZVAMO-EXT: __riscv_v 10000
	// CHECK-ZVAMO-EXT: __riscv_vector 1			// CHECK-ZVAMO-EXT: __riscv_vector 1
	// CHECK-ZVAMO-EXT: __riscv_zvamo 10000			// CHECK-ZVAMO-EXT: __riscv_zvamo 10000
	// CHECK-ZVAMO-EXT: __riscv_zvlsseg 10000			// CHECK-ZVAMO-EXT: __riscv_zvlsseg 10000

	// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv32izfh0p1 -x c -E -dM %s \			// RUN: -march=rv32izfh0p1 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-ZFH-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-ZFH-EXT %s
	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izfh0p1 -x c -E -dM %s \			// RUN: -march=rv64izfh0p1 -x c -E -dM %s \
	// RUN: -o - \| FileCheck --check-prefix=CHECK-ZFH-EXT %s			// RUN: -o - \| FileCheck --check-prefix=CHECK-ZFH-EXT %s
	// CHECK-ZFH-EXT: __riscv_zfh 1000			// CHECK-ZFH-EXT: __riscv_zfh 1000

	// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \			// RUN: -march=rv64ifdv0p10 -x c -E -dM %s -o - \
	// RUN: \| FileCheck --check-prefix=CHECK-V-MINVLEN %s			// RUN: \| FileCheck --check-prefix=CHECK-V-MINVLEN %s
	// CHECK-V-MINVLEN: __riscv_v_max_eew 64			// CHECK-V-MINVLEN: __riscv_v_max_eew 64
	// CHECK-V-MINVLEN: __riscv_v_max_eew_fp 64			// CHECK-V-MINVLEN: __riscv_v_max_eew_fp 64
	// CHECK-V-MINVLEN: __riscv_v_min_vlen 128			// CHECK-V-MINVLEN: __riscv_v_min_vlen 128


	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izve64d0p10 -x c -E -dM %s -o - \			// RUN: -march=rv64ifdzve64d0p10 -x c -E -dM %s -o - \
	// RUN: \| FileCheck --check-prefix=CHECK-ZVE64D-EXT %s			// RUN: \| FileCheck --check-prefix=CHECK-ZVE64D-EXT %s
	// CHECK-ZVE64D-EXT: __riscv_v_max_eew 64			// CHECK-ZVE64D-EXT: __riscv_v_max_eew 64
	// CHECK-ZVE64D-EXT: __riscv_v_max_eew_fp 64			// CHECK-ZVE64D-EXT: __riscv_v_max_eew_fp 64
	// CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64			// CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64
	// CHECK-ZVE64D-EXT: __riscv_zve32f 10000			// CHECK-ZVE64D-EXT: __riscv_zve32f 10000
	// CHECK-ZVE64D-EXT: __riscv_zve32x 10000			// CHECK-ZVE64D-EXT: __riscv_zve32x 10000
	// CHECK-ZVE64D-EXT: __riscv_zve64d 10000			// CHECK-ZVE64D-EXT: __riscv_zve64d 10000
	// CHECK-ZVE64D-EXT: __riscv_zve64f 10000			// CHECK-ZVE64D-EXT: __riscv_zve64f 10000
	// CHECK-ZVE64D-EXT: __riscv_zve64x 10000			// CHECK-ZVE64D-EXT: __riscv_zve64x 10000

	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izve64f0p10 -x c -E -dM %s -o - \			// RUN: -march=rv64ifzve64f0p10 -x c -E -dM %s -o - \
	// RUN: \| FileCheck --check-prefix=CHECK-ZVE64F-EXT %s			// RUN: \| FileCheck --check-prefix=CHECK-ZVE64F-EXT %s
	// CHECK-ZVE64F-EXT: __riscv_v_max_eew 64			// CHECK-ZVE64F-EXT: __riscv_v_max_eew 64
	// CHECK-ZVE64F-EXT: __riscv_v_max_eew_fp 32			// CHECK-ZVE64F-EXT: __riscv_v_max_eew_fp 32
	// CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64			// CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64
	// CHECK-ZVE64F-EXT: __riscv_zve32f 10000			// CHECK-ZVE64F-EXT: __riscv_zve32f 10000
	// CHECK-ZVE64F-EXT: __riscv_zve32x 10000			// CHECK-ZVE64F-EXT: __riscv_zve32x 10000
	// CHECK-ZVE64F-EXT: __riscv_zve64f 10000			// CHECK-ZVE64F-EXT: __riscv_zve64f 10000
	// CHECK-ZVE64F-EXT: __riscv_zve64x 10000			// CHECK-ZVE64F-EXT: __riscv_zve64x 10000

	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izve64x0p10 -x c -E -dM %s -o - \			// RUN: -march=rv64izve64x0p10 -x c -E -dM %s -o - \
	// RUN: \| FileCheck --check-prefix=CHECK-ZVE64X-EXT %s			// RUN: \| FileCheck --check-prefix=CHECK-ZVE64X-EXT %s
	// CHECK-ZVE64X-EXT: __riscv_v_max_eew 64			// CHECK-ZVE64X-EXT: __riscv_v_max_eew 64
	// CHECK-ZVE64X-EXT: __riscv_v_max_eew_fp 0			// CHECK-ZVE64X-EXT: __riscv_v_max_eew_fp 0
	// CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64			// CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64
	// CHECK-ZVE64X-EXT: __riscv_zve32x 10000			// CHECK-ZVE64X-EXT: __riscv_zve32x 10000
	// CHECK-ZVE64X-EXT: __riscv_zve64x 10000			// CHECK-ZVE64X-EXT: __riscv_zve64x 10000

	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izve32f0p10 -x c -E -dM %s -o - \			// RUN: -march=rv64ifzve32f0p10 -x c -E -dM %s -o - \
	// RUN: \| FileCheck --check-prefix=CHECK-ZVE32F-EXT %s			// RUN: \| FileCheck --check-prefix=CHECK-ZVE32F-EXT %s
	// CHECK-ZVE32F-EXT: __riscv_v_max_eew 32			// CHECK-ZVE32F-EXT: __riscv_v_max_eew 32
	// CHECK-ZVE32F-EXT: __riscv_v_max_eew_fp 32			// CHECK-ZVE32F-EXT: __riscv_v_max_eew_fp 32
	// CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32			// CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32
	// CHECK-ZVE32F-EXT: __riscv_zve32f 10000			// CHECK-ZVE32F-EXT: __riscv_zve32f 10000
	// CHECK-ZVE32F-EXT: __riscv_zve32x 10000			// CHECK-ZVE32F-EXT: __riscv_zve32x 10000

	// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \			// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
	// RUN: -march=rv64izve32x0p10 -x c -E -dM %s -o - \			// RUN: -march=rv64izve32x0p10 -x c -E -dM %s -o - \
	// RUN: \| FileCheck --check-prefix=CHECK-ZVE32X-EXT %s			// RUN: \| FileCheck --check-prefix=CHECK-ZVE32X-EXT %s
	// CHECK-ZVE32X-EXT: __riscv_v_max_eew 32			// CHECK-ZVE32X-EXT: __riscv_v_max_eew 32
	// CHECK-ZVE32X-EXT: __riscv_v_max_eew_fp 0			// CHECK-ZVE32X-EXT: __riscv_v_max_eew_fp 0
	// CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32			// CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
	// CHECK-ZVE32X-EXT: __riscv_zve32x 10000			// CHECK-ZVE32X-EXT: __riscv_zve32x 10000

clang/utils/TableGen/RISCVVEmitter.cpp

Show First 20 Lines • Show All 896 Lines • ▼ Show 20 Lines	OS << "/*===---- riscv_vector.h - RISC-V V-extension RVVIntrinsics "
" */\n\n";		" */\n\n";

OS << "#ifndef __RISCV_VECTOR_H\n";		OS << "#ifndef __RISCV_VECTOR_H\n";
OS << "#define __RISCV_VECTOR_H\n\n";		OS << "#define __RISCV_VECTOR_H\n\n";

OS << "#include <stdint.h>\n";		OS << "#include <stdint.h>\n";
OS << "#include <stddef.h>\n\n";		OS << "#include <stddef.h>\n\n";

OS << "#ifndef __riscv_vector\n";		OS << "#ifndef __riscv_zve32x\n";
OS << "#error \"Vector intrinsics require the vector extension.\"\n";		OS << "#error \"Vector intrinsics require the vector extension.\"\n";
OS << "#endif\n\n";		OS << "#endif\n\n";

OS << "#ifdef __cplusplus\n";		OS << "#ifdef __cplusplus\n";
OS << "extern \"C\" {\n";		OS << "extern \"C\" {\n";
OS << "#endif\n\n";		OS << "#endif\n\n";

createRVVHeaders(OS);		createRVVHeaders(OS);
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
}		}

void RVVEmitter::createBuiltins(raw_ostream &OS) {		void RVVEmitter::createBuiltins(raw_ostream &OS) {
std::vector<std::unique_ptr<RVVIntrinsic>> Defs;		std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
createRVVIntrinsics(Defs);		createRVVIntrinsics(Defs);

OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";		OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "		OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
"ATTRS, \"experimental-v\")\n";		"ATTRS, \"experimental-zve32x\")\n";
OS << "#endif\n";		OS << "#endif\n";
for (auto &Def : Defs) {		for (auto &Def : Defs) {
OS << "RISCVV_BUILTIN(__builtin_rvv_" << Def->getName() << ",\""		OS << "RISCVV_BUILTIN(__builtin_rvv_" << Def->getName() << ",\""
<< Def->getBuiltinTypeStr() << "\", \"n\")\n";		<< Def->getBuiltinTypeStr() << "\", \"n\")\n";
}		}
OS << "#undef RISCVV_BUILTIN\n";		OS << "#undef RISCVV_BUILTIN\n";
}		}

▲ Show 20 Lines • Show All 253 Lines • Show Last 20 Lines

llvm/lib/Support/RISCVISAInfo.cpp

Show First 20 Lines • Show All 696 Lines • ▼ Show 20 Lines	RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
return std::move(ISAInfo);		return std::move(ISAInfo);
}		}

Error RISCVISAInfo::checkDependency() {		Error RISCVISAInfo::checkDependency() {
bool IsRv32 = XLen == 32;		bool IsRv32 = XLen == 32;
bool HasE = Exts.count("e") == 1;		bool HasE = Exts.count("e") == 1;
bool HasD = Exts.count("d") == 1;		bool HasD = Exts.count("d") == 1;
bool HasF = Exts.count("f") == 1;		bool HasF = Exts.count("f") == 1;
		bool HasZvamo = Exts.count("zvamo") == 1;
		bool HasZvlsseg = Exts.count("zvlsseg") == 1;
		bool HasVector = MaxEew != 0;
		bool HasZvl = MinVLen != 0;

if (HasE && !IsRv32)		if (HasE && !IsRv32)
return createStringError(		return createStringError(
errc::invalid_argument,		errc::invalid_argument,
"standard user-level extension 'e' requires 'rv32'");		"standard user-level extension 'e' requires 'rv32'");

// It's illegal to specify the 'd' (double-precision floating point)		// It's illegal to specify the 'd' (double-precision floating point)
// extension without also specifying the 'f' (single precision		// extension without also specifying the 'f' (single precision
// floating-point) extension.		// floating-point) extension.
// TODO: This has been removed in later specs, which specify that D implies F		// TODO: This has been removed in later specs, which specify that D implies F
if (HasD && !HasF)		if (HasD && !HasF)
return createStringError(errc::invalid_argument,		return createStringError(errc::invalid_argument,
"d requires f extension to also be specified");		"d requires f extension to also be specified");

		if (HasZvamo && !HasVector)
		return createStringError(
		errc::invalid_argument,
		"zvamo requires v or zve* extension to also be specified");

		if (HasZvlsseg && !HasVector)
		return createStringError(
		errc::invalid_argument,
		"zvlsseg requires v or zve* extension to also be specified");

		if (HasZvl && !HasVector)
		return createStringError(
		errc::invalid_argument,
		"zvlb requires v or zve extension to also be specified");
		return Error::success();

// Additional dependency checks.		// Additional dependency checks.
// TODO: The 'q' extension requires rv64.		// TODO: The 'q' extension requires rv64.
// TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.		// TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.

return Error::success();		return Error::success();
}		}

void RISCVISAInfo::updateImplication() {		void RISCVISAInfo::updateImplication() {
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This is an archive of the discontinued LLVM Phabricator instance.

[Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instructionClosedPublic

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Event Timeline

Revision Contents

Diff 382615

clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c

clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c

clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

clang/test/CodeGen/RISCV/riscv-v-debuginfo.c

clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c

[Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction
ClosedPublic