[RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.

[craig.topper]

Summary

Similar to what we do for add/sub/mul.

This can help remove some sext.w. There are some regressions on
some bswap tests, but I have an idea how to fix that for a follow up.

A new PACKW pattern is added to handle the new sext_inreg placement.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1140

Does this pattern still get generated? If so it's a shame one isn't canonicalised to the other :(

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1140

I think we would still generate it for this

int foo(unsigned long long x, unsigned long long y) {
  return (x << 16) | (y & 0xffff);
}

Type legalization doesn't get involved since x and y are i64. A sign extend will be introduced for the result due to ABI.

In general, we should be pushing sext to the inputs of and/or/xor looking for locations that would make them free. This case could be done with a simple peephole. More complex cases could require looking back through multiple logic ops which could become computationally expensive.

[craig.topper]

I've posted D108738 to make bitreverse expansion more efficient out of the box. That should prevent the regressions here.

[craig.topper]

Rebase on top of bitreverse changes from D108738

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1140

Yeah, ok

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
     break;
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
-    if (N->getOperand(1).getOpcode() == ISD::Constant)
-      return;
+    if (N->getOperand(1).getOpcode() != ISD::Constant) {
       Results.push_back(customLegalizeToWOp(N, DAG));
       break;
+    }
+
+    // Custom legalize ISD::SHL by placing a SIGN_EXTEND_INREG after. This is
+    // similar to customLegalizeToWOpWithSExt, but we must zero_extend the
+    // shift amount.
+    if (N->getOpcode() == ISD::SHL) {
+      SDLoc DL(N);
+      SDValue NewOp0 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
+      SDValue NewOp1 =
+          DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue NewWOp = DAG.getNode(ISD::SHL, DL, MVT::i64, NewOp0, NewOp1);
+      SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
+                                   DAG.getValueType(MVT::i32));
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes));
+    }
+
+    break;
   case ISD::ROTL:
   case ISD::ROTR:
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     Results.push_back(customLegalizeToWOp(N, DAG));
     break;
   case ISD::CTTZ:
   case ISD::CTTZ_ZERO_UNDEF:

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : PatGpr<riscv_clzw, CLZW>;
 def : PatGpr<riscv_ctzw, CTZW>;
 def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
                                (and GPR:$rs1, 0x000000000000FFFF)),
                            i32)),
           (PACKW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
+                   (and GPR:$rs1, 0x000000000000FFFF))),
+          (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
                    (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbc] in {
 def : PatGprGpr<int_riscv_clmul, CLMUL>;
 def : PatGprGpr<int_riscv_clmulh, CLMULH>;

llvm/test/CodeGen/RISCV/alu32.ll

 define i32 @slli(i32 %a) nounwind {
 ; RV32I-LABEL: slli:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 7
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: slli:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 7
+; RV64I-NEXT:    slliw a0, a0, 7
 ; RV64I-NEXT:    ret
   %1 = shl i32 %a, 7
   ret i32 %1
 }
 
 define i32 @srli(i32 %a) nounwind {
 ; RV32I-LABEL: srli:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a2, a0, 24
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    lui a3, 4080
 ; RV64I-NEXT:    and a2, a2, a3
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %tmp = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %tmp
 }
 
 define i64 @test_bswap_i64(i64 %a) nounwind {

llvm/test/CodeGen/RISCV/copysign-casts.ll

 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_promote_f_h:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    addiw a2, a2, -1
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    lui a2, 1048568
+; RV64I-NEXT:    lui a2, 8
 ; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    slli a1, a1, 16
+; RV64I-NEXT:    slliw a1, a1, 16
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_promote_f_h:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/mul.ll

 ;
 ; RV32IM-LABEL: mul_pow2:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a0, a0, 3
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: mul_pow2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 3
+; RV64I-NEXT:    slliw a0, a0, 3
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: mul_pow2:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    slli a0, a0, 3
+; RV64IM-NEXT:    slliw a0, a0, 3
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, 8
   ret i32 %1
 }
 
 define i64 @mul64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: mul64:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

; RV64I-NEXT:    ret
   ret i32 %1
 }
 
 ; slliw should be selected whenever the return is signext.
 
 define i32 @aext_slliw_aext(i32 %a) nounwind {
 ; RV64I-LABEL: aext_slliw_aext:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    slliw a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = shl i32 %a, 1
   ret i32 %1
 }
 
 define i32 @aext_slliw_sext(i32 signext %a) nounwind {
 ; RV64I-LABEL: aext_slliw_sext:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 2
+; RV64I-NEXT:    slliw a0, a0, 2
 ; RV64I-NEXT:    ret
   %1 = shl i32 %a, 2
   ret i32 %1
 }
 
 define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {
 ; RV64I-LABEL: aext_slliw_zext:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 3
+; RV64I-NEXT:    slliw a0, a0, 3
 ; RV64I-NEXT:    ret
   %1 = shl i32 %a, 3
   ret i32 %1
 }
 
 define signext i32 @sext_slliw_aext(i32 %a) nounwind {
 ; RV64I-LABEL: sext_slliw_aext:
 ; RV64I:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

; RV64ZBP-NEXT:    ret
   %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
   ret i64 %or
 }
 
 define signext i32 @rori_i32_fshl(i32 signext %a) nounwind {
 ; RV64I-LABEL: rori_i32_fshl:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a1, a0, 1
-; RV64I-NEXT:    slli a0, a0, 31
+; RV64I-NEXT:    slliw a0, a0, 31
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: rori_i32_fshl:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    roriw a0, a0, 1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rori_i32_fshl:
; RV64ZBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
   store i32 %1, i32* %x
   ret void
 }
 
 define signext i32 @rori_i32_fshr(i32 signext %a) nounwind {
 ; RV64I-LABEL: rori_i32_fshr:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    srliw a0, a0, 31
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: rori_i32_fshr:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    roriw a0, a0, 31
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rori_i32_fshr:

 }
 
 ; This test is similar to the type legalized version of the fshl/fshr tests, but
 ; instead of having the same input to both shifts it has different inputs. Make
 ; sure we don't match it as a roriw.
 define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
 ; RV64I-LABEL: not_rori_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 31
+; RV64I-NEXT:    slliw a0, a0, 31
 ; RV64I-NEXT:    srliw a1, a1, 1
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: not_rori_i32:
 ; RV64B:       # %bb.0:
-; RV64B-NEXT:    slli a0, a0, 31
+; RV64B-NEXT:    slliw a0, a0, 31
 ; RV64B-NEXT:    srliw a1, a1, 1
 ; RV64B-NEXT:    or a0, a0, a1
-; RV64B-NEXT:    sext.w a0, a0
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: not_rori_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    slli a0, a0, 31
+; RV64ZBB-NEXT:    slliw a0, a0, 31
 ; RV64ZBB-NEXT:    srliw a1, a1, 1
 ; RV64ZBB-NEXT:    or a0, a0, a1
-; RV64ZBB-NEXT:    sext.w a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: not_rori_i32:
 ; RV64ZBP:       # %bb.0:
-; RV64ZBP-NEXT:    slli a0, a0, 31
+; RV64ZBP-NEXT:    slliw a0, a0, 31
 ; RV64ZBP-NEXT:    srliw a1, a1, 1
 ; RV64ZBP-NEXT:    or a0, a0, a1
-; RV64ZBP-NEXT:    sext.w a0, a0
 ; RV64ZBP-NEXT:    ret
   %a = shl i32 %x, 31
   %b = lshr i32 %y, 1
   %c = or i32 %a, %b
   ret i32 %c
 }
 
 ; This is similar to the type legalized roriw pattern, but the and mask is more

llvm/test/CodeGen/RISCV/rv64zbb.ll

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a2, a0, 24
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    lui a3, 4080
 ; RV64I-NEXT:    and a2, a2, a3
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: bswap_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 24
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: bswap_i32:

llvm/test/CodeGen/RISCV/rv64zbp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64B
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZBP
 
 define signext i32 @gorc1_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc1_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc1_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc1_i32:
; RV64ZBP-NEXT:    ret
   %or = or i64 %shr, %a
   %or2 = or i64 %or, %shl
   ret i64 %or2
 }
 
 define signext i32 @gorc2_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc2_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    lui a3, 209715
 ; RV64I-NEXT:    addiw a3, a3, 819
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc2_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 2
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc2_i32:
; RV64ZBP-NEXT:    ret
   %or = or i64 %shr, %a
   %or2 = or i64 %or, %shl
   ret i64 %or2
 }
 
 define signext i32 @gorc3_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc3_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    lui a3, 209715
 ; RV64I-NEXT:    addiw a3, a3, 819
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc3_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 3
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc3_i32:
; RV64ZBP-NEXT:    ret
   %or2 = or i64 %shr2, %or1b
   %or2b = or i64 %or2, %shl2
   ret i64 %or2b
 }
 
 define signext i32 @gorc4_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc4_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    lui a3, 61681
 ; RV64I-NEXT:    addiw a3, a3, -241
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc4_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 4
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc4_i32:
; RV64ZBP-NEXT:    ret
   %or = or i64 %shr, %a
   %or2 = or i64 %or, %shl
   ret i64 %or2
 }
 
 define signext i32 @gorc5_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc5_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    lui a3, 61681
 ; RV64I-NEXT:    addiw a3, a3, -241
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc5_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 5
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc5_i32:
; RV64ZBP-NEXT:    ret
   %or2 = or i64 %shr2, %or1b
   %or2b = or i64 %or2, %shl2
   ret i64 %or2b
 }
 
 define signext i32 @gorc6_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc6_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    lui a3, 209715
 ; RV64I-NEXT:    addiw a3, a3, 819
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    lui a3, 61681
 ; RV64I-NEXT:    addiw a3, a3, -241
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc6_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 6
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc6_i32:
; RV64ZBP-NEXT:    ret
   %or2 = or i64 %shr2, %or1b
   %or2b = or i64 %or2, %shl2
   ret i64 %or2b
 }
 
 define signext i32 @gorc7_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc7_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    lui a3, 209715
 ; RV64I-NEXT:    addiw a3, a3, 819
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
; RV64ZBP-NEXT:    ret
   %or3 = or i64 %shr3, %or2b
   %or3b = or i64 %or3, %shl3
   ret i64 %or3b
 }
 
 define signext i32 @gorc8_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc8_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 8
+; RV64I-NEXT:    slliw a1, a0, 8
 ; RV64I-NEXT:    lui a2, 1044496
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 8
 ; RV64I-NEXT:    lui a3, 4080
 ; RV64I-NEXT:    addiw a3, a3, 255
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc8_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 8
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc8_i32:
; RV64ZBP-NEXT:    ret
   %or = or i64 %shr, %a
   %or2 = or i64 %or, %shl
   ret i64 %or2
 }
 
 define signext i32 @gorc16_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc16_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 16
+; RV64I-NEXT:    slliw a1, a0, 16
 ; RV64I-NEXT:    srliw a2, a0, 16
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc16_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 16
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc16_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    gorciw a0, a0, 16
 ; RV64ZBP-NEXT:    ret
   %shl = shl i32 %a, 16
   %shr = lshr i32 %a, 16
   %or = or i32 %shr, %a
   %or2 = or i32 %or, %shl
   ret i32 %or2
 }
 
 define i32 @gorc16_rotl_i32(i32 %a) nounwind {
 ; RV64I-LABEL: gorc16_rotl_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a1, a0, 16
-; RV64I-NEXT:    slli a2, a0, 16
+; RV64I-NEXT:    slliw a2, a0, 16
 ; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc16_rotl_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 16
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc16_rotl_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    gorciw a0, a0, 16
 ; RV64ZBP-NEXT:    ret
   %rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
   %or = or i32 %rot, %a
   ret i32 %or
 }
 
 define i32 @gorc16_rotr_i32(i32 %a) nounwind {
 ; RV64I-LABEL: gorc16_rotr_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 16
+; RV64I-NEXT:    slliw a1, a0, 16
 ; RV64I-NEXT:    srliw a2, a0, 16
 ; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc16_rotr_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 16
; RV64ZBP-NEXT:    ret
   %or2 = or i64 %or, %shl
   ret i64 %or2
 }
 
 ; gorc2, gorc2 -> gorc2
 define signext i32 @gorc2b_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc2b_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a3, a0, 2
 ; RV64I-NEXT:    lui a4, 209715
 ; RV64I-NEXT:    addiw a4, a4, 819
 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    or a0, a3, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    and a2, a2, a4
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: gorc2b_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    gorciw a0, a0, 2
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: gorc2b_i32:
; RV64ZBP-NEXT:    ret
   %or2b = or i64 %or2, %shl2
   ret i64 %or2b
 }
 
 ; gorc1, gorc2, gorc1 -> gorc2
 define signext i32 @gorc3b_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: gorc3b_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a3, a0, 1
 ; RV64I-NEXT:    lui a4, 349525
 ; RV64I-NEXT:    addiw a4, a4, 1365
 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    or a0, a3, a0
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a3, 838861
 ; RV64I-NEXT:    addiw a3, a3, -820
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    srli a3, a0, 2
 ; RV64I-NEXT:    lui a5, 209715
 ; RV64I-NEXT:    addiw a5, a5, 819
 ; RV64I-NEXT:    and a3, a3, a5
 ; RV64I-NEXT:    or a0, a3, a0
; RV64ZBP-NEXT:    ret
   %rot = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32)
   %or = or i64 %rot, %a
   ret i64 %or
 }
 
 define signext i32 @grev1_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev1_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    addiw a2, a2, 1365
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev1_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev1_i32:
; RV64ZBP-NEXT:    ret
   %shr = and i64 %and1, 6148914691236517205
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 define signext i32 @grev2_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev2_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev2_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 2
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev2_i32:
; RV64ZBP-NEXT:    ret
   %shr = and i64 %and1, 3689348814741910323
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 define signext i32 @grev3_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev3_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    addiw a2, a2, 1365
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev3_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 3
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev3_i32:
; RV64ZBP-NEXT:    ret
   %shr2 = and i64 %and2b, 3689348814741910323
   %or2 = or i64 %shl2, %shr2
   ret i64 %or2
 }
 
 define signext i32 @grev4_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev4_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 4
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev4_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 4
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev4_i32:
; RV64ZBP-NEXT:    ret
   %shr = and i64 %and1, 1085102592571150095
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 define signext i32 @grev5_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev5_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    addiw a2, a2, 1365
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 4
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev5_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 5
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev5_i32:
; RV64ZBP-NEXT:    ret
   %shr2 = and i64 %and2b, 1085102592571150095
   %or2 = or i64 %shl2, %shr2
   ret i64 %or2
 }
 
 define signext i32 @grev6_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev6_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 4
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev6_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 6
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev6_i32:
; RV64ZBP-NEXT:    ret
   %shr2 = and i64 %and2b, 1085102592571150095
   %or2 = or i64 %shl2, %shr2
   ret i64 %or2
 }
 
 define signext i32 @grev7_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev7_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    addiw a2, a2, 1365
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 4
+; RV64I-NEXT:    slliw a1, a0, 4
 ; RV64I-NEXT:    lui a2, 986895
 ; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 4
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev7_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 7
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev7_i32:
; RV64ZBP-NEXT:    ret
   %shr3 = and i64 %and3b, 1085102592571150095
   %or3 = or i64 %shl3, %shr3
   ret i64 %or3
 }
 
 define signext i32 @grev8_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev8_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 8
+; RV64I-NEXT:    slliw a1, a0, 8
 ; RV64I-NEXT:    lui a2, 1044496
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 8
 ; RV64I-NEXT:    lui a2, 4080
 ; RV64I-NEXT:    addiw a2, a2, 255
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev8_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 8
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev8_i32:
; RV64ZBP-NEXT:    ret
   %shr = and i64 %and1, 71777214294589695
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 define signext i32 @grev16_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev16_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 16
+; RV64I-NEXT:    slliw a1, a0, 16
 ; RV64I-NEXT:    srliw a0, a0, 16
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev16_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 16
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev16_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    greviw a0, a0, 16
 ; RV64ZBP-NEXT:    ret
   %shl = shl i32 %a, 16
   %shr = lshr i32 %a, 16
   %or = or i32 %shl, %shr
   ret i32 %or
 }
 
 declare i32 @llvm.fshl.i32(i32, i32, i32)
 declare i32 @llvm.fshr.i32(i32, i32, i32)
 
 define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev16_i32_fshl:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a1, a0, 16
-; RV64I-NEXT:    slli a0, a0, 16
+; RV64I-NEXT:    slliw a0, a0, 16
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev16_i32_fshl:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    roriw a0, a0, 16
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev16_i32_fshl:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    roriw a0, a0, 16
 ; RV64ZBP-NEXT:    ret
   %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
   ret i32 %or
 }
 
 define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev16_i32_fshr:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 16
+; RV64I-NEXT:    slliw a1, a0, 16
 ; RV64I-NEXT:    srliw a0, a0, 16
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev16_i32_fshr:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    roriw a0, a0, 16
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev16_i32_fshr:
; RV64ZBP-NEXT:    ret
   %shr = lshr i64 %a, 32
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 define signext i32 @grev3b_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev3b_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    addiw a2, a2, 1365
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev3b_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 3
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev3b_i32:
; RV64ZBP-NEXT:    ret
   %or1 = or i64 %shl1, %shr1
   ret i64 %or1
 }
 
 ; grev1, grev2, grev1 -> grev2
 define signext i32 @grev2b_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev2b_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a4, 838861
 ; RV64I-NEXT:    addiw a4, a4, -820
 ; RV64I-NEXT:    and a1, a1, a4
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a4, 209715
 ; RV64I-NEXT:    addiw a4, a4, 819
 ; RV64I-NEXT:    and a0, a0, a4
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev2b_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 2
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev2b_i32:
; RV64ZBP-NEXT:    ret
   %or3 = or i64 %shl3, %shr3
   ret i64 %or3
 }
 
 ; grev1, grev2, grev1, grev2 -> identity
 define signext i32 @grev0_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: grev0_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    lui a2, 699051
 ; RV64I-NEXT:    addiw a2, a2, -1366
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    lui a4, 838861
 ; RV64I-NEXT:    addiw a4, a4, -820
 ; RV64I-NEXT:    and a1, a1, a4
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    lui a5, 209715
 ; RV64I-NEXT:    addiw a5, a5, 819
 ; RV64I-NEXT:    and a0, a0, a5
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slliw a1, a0, 1
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slliw a1, a0, 2
 ; RV64I-NEXT:    and a1, a1, a4
 ; RV64I-NEXT:    srli a0, a0, 2
 ; RV64I-NEXT:    and a0, a0, a5
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: grev0_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: grev0_i32:
 ; RV64ZBP:       # %bb.0:

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a2, a0, 24
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    lui a3, 4080
 ; RV64I-NEXT:    and a2, a2, a3
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: bswap_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 24
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: bswap_i32:

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a2, a0, 24
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    lui a3, 4080
 ; RV64I-NEXT:    and a2, a2, a3
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 4
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    slliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    srli a1, a0, 2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    slli a0, a0, 2
+; RV64I-NEXT:    slliw a0, a0, 2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    srli a1, a0, 1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    addiw a2, a2, 1365
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    slliw a0, a0, 1
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: bitreverse_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 31
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: bitreverse_i32:

 ; RV64I-NEXT:    lui a3, 16
 ; RV64I-NEXT:    addiw a3, a3, -256
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    or a2, a2, a3
 ; RV64I-NEXT:    slli a3, a0, 8
 ; RV64I-NEXT:    lui a4, 4080
 ; RV64I-NEXT:    and a3, a3, a4
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    lui a3, 61681
 ; RV64I-NEXT:    addiw a3, a3, -241
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    slliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    srli a2, a0, 2
 ; RV64I-NEXT:    lui a3, 209715
 ; RV64I-NEXT:    addiw a3, a3, 819
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    slli a0, a0, 2
+; RV64I-NEXT:    slliw a0, a0, 2
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    srli a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    or a0, a2, a0

 ; RV64ZBP-NEXT:    ret
   %1 = call i64 @llvm.bitreverse.i64(i64 %a)
   ret i64 %1
 }
 
 define i32 @bswap_rotr_i32(i32 %a) {
 ; RV64I-LABEL: bswap_rotr_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srliw a1, a0, 8
-; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    addiw a2, a2, -256
+; RV64I-NEXT:    slli a1, a0, 8
+; RV64I-NEXT:    lui a2, 4080
 ; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    slli a2, a0, 24
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    srliw a2, a0, 24
-; RV64I-NEXT:    or a1, a1, a2
-; RV64I-NEXT:    slli a2, a0, 8
-; RV64I-NEXT:    lui a3, 4080
-; RV64I-NEXT:    and a2, a2, a3
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    srliw a0, a0, 8
+; RV64I-NEXT:    andi a0, a0, -256
 ; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    or a1, a0, a1
-; RV64I-NEXT:    slli a1, a1, 16
-; RV64I-NEXT:    srliw a0, a0, 16
-; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    slliw a0, a0, 16
+; RV64I-NEXT:    srliw a1, a1, 16
+; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: bswap_rotr_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 8
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: bswap_rotr_i32:
 ; RV64ZBP:       # %bb.0:
 ; RV64ZBP-NEXT:    greviw a0, a0, 8
 ; RV64ZBP-NEXT:    ret
   %1 = call i32 @llvm.bswap.i32(i32 %a)
   %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16)
   ret i32 %2
 }
 
 define i32 @bswap_rotl_i32(i32 %a) {
 ; RV64I-LABEL: bswap_rotl_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srliw a1, a0, 8
-; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    addiw a2, a2, -256
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    srliw a2, a0, 24
-; RV64I-NEXT:    or a1, a1, a2
+; RV64I-NEXT:    srliw a1, a0, 24
+; RV64I-NEXT:    srliw a2, a0, 8
+; RV64I-NEXT:    andi a2, a2, -256
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    lui a3, 4080
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    slli a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    or a1, a0, a1
-; RV64I-NEXT:    slli a1, a1, 16
 ; RV64I-NEXT:    srliw a0, a0, 16
+; RV64I-NEXT:    slliw a1, a1, 16
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: bswap_rotl_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 8
 ; RV64B-NEXT:    ret
 ;

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    slli a3, a0, 8
 ; RV64I-NEXT:    lui a4, 4080
 ; RV64I-NEXT:    and a3, a3, a4
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 4
 ; RV64I-NEXT:    lui a3, 61681
 ; RV64I-NEXT:    addiw a3, a3, -241
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    slliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    srli a1, a0, 2
 ; RV64I-NEXT:    lui a3, 209715
 ; RV64I-NEXT:    addiw a3, a3, 819
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    slli a0, a0, 2
+; RV64I-NEXT:    slliw a0, a0, 2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    srli a1, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
 ; RV64I-NEXT:    addiw a3, a3, 1365
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    slliw a0, a0, 1
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 8
+; RV64I-NEXT:    srliw a1, a0, 8
 ; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    srli a2, a0, 24
+; RV64I-NEXT:    srliw a2, a0, 24
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    and a2, a2, a4
-; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    slliw a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: bitreverse_bswap_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    greviw a0, a0, 7
 ; RV64B-NEXT:    ret

 }
 
 define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: pack_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -1
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    slli a1, a1, 16
+; RV64I-NEXT:    slliw a1, a1, 16
 ; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: pack_i32:
 ; RV64B:       # %bb.0:
 ; RV64B-NEXT:    packw a0, a0, a1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBP-LABEL: pack_i32: