[RISCV] Add a PreprocessISelDAG peephole for (i64 (srl (and X, C)))

[craig.topper]

Summary

For cases where C is a uimm32 but not simm32. We can split the and
into (and (and X, sext32(C), 0xffffffff)). The outer and will be
selected with the srl to form srliw. The inner and will be selected
as an AND instruction with a sext32(C) materialized separately.

This prevents regressions from D108663, but is helpful on its own.

[craig.topper]

Maybe a better fix is to just move the and after the shift in DAG combine. That would guarantee bit 31 moves right at least 1 bit. That would be enough to guarantee it goes from a uimm32 constant to a simm32 constant.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 } // namespace llvm
 
 void RISCVDAGToDAGISel::PreprocessISelDAG() {
   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
                                        E = CurDAG->allnodes_end();
        I != E;) {
     SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
 
+    // Look for (srl (and X, C)) where C is a uimm32 constant, but not a simm32
+    // contant. Split it into (srl (and (and X, sext32(C)), 0xffffffff). This
+    // will allow srliw to be used for the outer srl+and, and sext32(C) can be
+    // materialized easier than C.
+    if (N->getOpcode() == ISD::SRL && N->getValueType(0) == MVT::i64 &&
+        N->getOperand(0).getOpcode() == ISD::AND &&
+        N->getOperand(0)->hasOneUse() &&
+        isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)) &&
+        N->getOperand(0)->getOperand(1)->hasOneUse()) {
+      SDValue And = N->getOperand(0);
+      uint64_t C = And.getConstantOperandVal(1);
+      if (isUInt<32>(C) && !isInt<32>(C) && C != UINT64_C(0xFFFFFFFF)) {
+        SDLoc DL(And);
+        C = SignExtend64(C, 32);
+        SDValue And1 =
+            CurDAG->getNode(ISD::AND, DL, MVT::i64, And->getOperand(0),
+                            CurDAG->getConstant(C, DL, MVT::i64));
+        SDValue And2 = CurDAG->getNode(
+            ISD::AND, DL, MVT::i64, And1,
+            CurDAG->getConstant(UINT64_C(0xFFFFFFFF), DL, MVT::i64));
+        CurDAG->UpdateNodeOperands(N, And2, N->getOperand(1));
+      }
+    }
+
     // Lower SPLAT_VECTOR_SPLIT_I64 to two scalar stores and a stride 0 vector
     // load. Done after lowering and combining so that we have a chance to
     // optimize this to VMV_V_X_VL when the upper bits aren't needed.
     if (N->getOpcode() != RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL)
       continue;
 
     assert(N->getNumOperands() == 3 && "Unexpected number of operands");
     MVT VT = N->getSimpleValueType(0);

llvm/test/CodeGen/RISCV/copysign-casts.ll

 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_demote_h_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 8
 ; RV64I-NEXT:    addiw a2, a2, -1
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    addi a2, zero, 1
-; RV64I-NEXT:    slli a2, a2, 31
+; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    srli a1, a1, 16
+; RV64I-NEXT:    srliw a1, a1, 16
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_demote_h_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.x.w a0, fa1
 ; RV32IF-NEXT:    fmv.x.w a1, fa0
 ; RV32IF-NEXT:    lui a2, 8

llvm/test/CodeGen/RISCV/rv64zbp.ll

 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    slli a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    lui a1, 61681
 ; RV64I-NEXT:    addiw a1, a1, -241
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a1, a1, 4
-; RV64I-NEXT:    lui a2, 241
-; RV64I-NEXT:    addiw a2, a2, -241
-; RV64I-NEXT:    slli a2, a2, 12
-; RV64I-NEXT:    addi a2, a2, 240
+; RV64I-NEXT:    lui a2, 986895
+; RV64I-NEXT:    addiw a2, a2, 240
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    srli a0, a0, 4
+; RV64I-NEXT:    srliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    lui a1, 209715
 ; RV64I-NEXT:    addiw a1, a1, 819
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a1, a1, 2
 ; RV64I-NEXT:    lui a2, 838861
 ; RV64I-NEXT:    addiw a2, a2, -820
 ; RV64I-NEXT:    and a0, a0, a2

 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    slli a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 4
-; RV64I-NEXT:    lui a3, 241
-; RV64I-NEXT:    addiw a3, a3, -241
-; RV64I-NEXT:    slli a3, a3, 12
-; RV64I-NEXT:    addi a3, a3, 240
+; RV64I-NEXT:    lui a3, 986895
+; RV64I-NEXT:    addiw a3, a3, 240
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    srli a0, a0, 4
+; RV64I-NEXT:    srliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    lui a2, 209715
 ; RV64I-NEXT:    addiw a2, a2, 819
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 2
 ; RV64I-NEXT:    lui a3, 838861
 ; RV64I-NEXT:    addiw a3, a3, -820
 ; RV64I-NEXT:    and a0, a0, a3

 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    slli a0, a0, 24
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    lui a1, 61681
 ; RV64I-NEXT:    addiw a1, a1, -241
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a1, a1, 4
-; RV64I-NEXT:    lui a3, 241
-; RV64I-NEXT:    addiw a3, a3, -241
-; RV64I-NEXT:    slli a3, a3, 12
-; RV64I-NEXT:    addi a3, a3, 240
+; RV64I-NEXT:    lui a3, 986895
+; RV64I-NEXT:    addiw a3, a3, 240
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    srli a0, a0, 4
+; RV64I-NEXT:    srliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    lui a1, 209715
 ; RV64I-NEXT:    addiw a1, a1, 819
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a1, a1, 2
 ; RV64I-NEXT:    lui a3, 838861
 ; RV64I-NEXT:    addiw a3, a3, -820
 ; RV64I-NEXT:    and a0, a0, a3