[RISCV] Add a helper function to allow ReplaceNodeResults to use sign extension for any_extend of i32 constants.

[craig.topper]

Summary

any_extend is constant folded as zero extension, but that's not
ideal for RISCV.

Use the helper for shifts, rotates, and uaddo/usubo. There are
still more cases to update, but we need tests first.

[luismarques]

Can't we just address the root problem and make those any_extends be sign-extended for RISC-V, where they are handled?

[craig.topper]

In D105785#2873425, @luismarques wrote:

Can't we just address the root problem and make those any_extends be sign-extended for RISC-V, where they are handled?

Alternative version D105918

[craig.topper]

We no longer need this after D105918

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
case ISD::ROTR:
     return RISCVISD::RORW;
   case RISCVISD::GREV:
     return RISCVISD::GREVW;
   case RISCVISD::GORC:
     return RISCVISD::GORCW;
   }
 }
 
+// Helper function to use sign extension instead of zero extension for
+// any_extend of i32 constants to improve constant materialization.
+static SDValue extendValue(unsigned ExtOpc, const SDLoc &DL, EVT VT, SDValue V,
+                           SelectionDAG &DAG) {
+  if (ExtOpc == ISD::ANY_EXTEND && V.getValueType() == MVT::i32 &&
+      isa<ConstantSDNode>(V))
+    ExtOpc = ISD::SIGN_EXTEND;
+  return DAG.getNode(ExtOpc, DL, VT, V);
+}
+
 // Converts the given 32-bit operation to a target-specific SelectionDAG node.
 // Because i32 isn't a legal type for RV64, these operations would otherwise
 // be promoted to i64, making it difficult to select the SLLW/DIVUW/.../*W
 // later one because the fact the operation was originally of type i32 is
 // lost.
 static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG,
                                    unsigned ExtOpc = ISD::ANY_EXTEND) {
   SDLoc DL(N);
   RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode());
-  SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
-  SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));
+  SDValue NewOp0 = extendValue(ExtOpc, DL, MVT::i64, N->getOperand(0), DAG);
+  SDValue NewOp1 = extendValue(ExtOpc, DL, MVT::i64, N->getOperand(1), DAG);
   SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
   // ReplaceNodeResults requires we maintain the same type for the return value.
   return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);
 }
 
 // Converts the given 32-bit operation to a i64 operation with signed extension
 // semantic to reduce the signed extension instructions.
 static SDValue customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) {
   SDLoc DL(N);
-  SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
-  SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+  SDValue NewOp0 =
+      extendValue(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0), DAG);
+  SDValue NewOp1 =
+      extendValue(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1), DAG);
   SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1);
   SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
                                DAG.getValueType(MVT::i32));
   return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
 }
 
 void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
                                              SmallVectorImpl<SDValue> &Results,
case ISD::UREM: {
     break;
   }
   case ISD::UADDO:
   case ISD::USUBO: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     bool IsAdd = N->getOpcode() == ISD::UADDO;
     // Create an ADDW or SUBW.
-    SDValue LHS = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
-    SDValue RHS = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+    SDValue LHS =
+        extendValue(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0), DAG);
+    SDValue RHS =
+        extendValue(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1), DAG);
     SDValue Res =
         DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS);
     Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Res,
                       DAG.getValueType(MVT::i32));
 
     // Sign extend the LHS and perform an unsigned compare with the ADDW result.
     // Since the inputs are sign extended from i32, this is equivalent to
     // comparing the lower 32 bits.

llvm/test/CodeGen/RISCV/alu32.ll

 ; RV32I-LABEL: sub_negative_constant_lhs:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, -2
 ; RV32I-NEXT:    sub a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sub_negative_constant_lhs:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a1, zero, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    addi a1, a1, -2
+; RV64I-NEXT:    addi a1, zero, -2
 ; RV64I-NEXT:    subw a0, a1, a0
 ; RV64I-NEXT:    ret
   %1 = sub i32 -2, %a
   ret i32 %1
 }
 
 define i32 @sll(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sll:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, -1
 ; RV32I-NEXT:    sll a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sll_negative_constant_lhs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    sllw a0, a1, a0
 ; RV64I-NEXT:    ret
   %1 = shl i32 -1, %a
   ret i32 %1
 }
 
 define i32 @slt(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: slt:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, -1
 ; RV32I-NEXT:    srl a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: srl_negative_constant_lhs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    srlw a0, a1, a0
 ; RV64I-NEXT:    ret
   %1 = lshr i32 -1, %a
   ret i32 %1
 }
 
 define i32 @sra(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sra:

 ; RV32I-LABEL: sra_negative_constant_lhs:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    sra a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sra_negative_constant_lhs:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a1, zero, 1
-; RV64I-NEXT:    slli a1, a1, 31
+; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    sraw a0, a1, a0
 ; RV64I-NEXT:    ret
   %1 = ashr i32 2147483648, %a
   ret i32 %1
 }
 
 define i32 @or(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: or:

llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

; RV64IBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
   store i32 %1, i32* %x
   ret void
 }
 
 define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
 ; RV64I-LABEL: rol_i32_neg_constant_rhs:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    neg a1, a0
-; RV64I-NEXT:    addi a2, zero, 1
-; RV64I-NEXT:    slli a2, a2, 32
-; RV64I-NEXT:    addi a2, a2, -2
-; RV64I-NEXT:    srlw a1, a2, a1
-; RV64I-NEXT:    sllw a0, a2, a0
-; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addi a1, zero, -2
+; RV64I-NEXT:    sllw a2, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    srlw a0, a1, a0
+; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: rol_i32_neg_constant_rhs:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 1
-; RV64IB-NEXT:    slli a1, a1, 32
-; RV64IB-NEXT:    addi a1, a1, -2
+; RV64IB-NEXT:    addi a1, zero, -2
 ; RV64IB-NEXT:    rolw a0, a1, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: rol_i32_neg_constant_rhs:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addi a1, zero, 1
-; RV64IBB-NEXT:    slli a1, a1, 32
-; RV64IBB-NEXT:    addi a1, a1, -2
+; RV64IBB-NEXT:    addi a1, zero, -2
 ; RV64IBB-NEXT:    rolw a0, a1, a0
 ; RV64IBB-NEXT:    ret
 ;
 ; RV64IBP-LABEL: rol_i32_neg_constant_rhs:
 ; RV64IBP:       # %bb.0:
-; RV64IBP-NEXT:    addi a1, zero, 1
-; RV64IBP-NEXT:    slli a1, a1, 32
-; RV64IBP-NEXT:    addi a1, a1, -2
+; RV64IBP-NEXT:    addi a1, zero, -2
 ; RV64IBP-NEXT:    rolw a0, a1, a0
 ; RV64IBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 -2, i32 -2, i32 %a)
   ret i32 %1
 }
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
; RV64IBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
   store i32 %1, i32* %x
   ret void
 }
 
 define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
 ; RV64I-LABEL: ror_i32_neg_constant_rhs:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    neg a1, a0
-; RV64I-NEXT:    addi a2, zero, 1
-; RV64I-NEXT:    slli a2, a2, 32
-; RV64I-NEXT:    addi a2, a2, -2
-; RV64I-NEXT:    sllw a1, a2, a1
-; RV64I-NEXT:    srlw a0, a2, a0
-; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addi a1, zero, -2
+; RV64I-NEXT:    srlw a2, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    sllw a0, a1, a0
+; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: ror_i32_neg_constant_rhs:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 1
-; RV64IB-NEXT:    slli a1, a1, 32
-; RV64IB-NEXT:    addi a1, a1, -2
+; RV64IB-NEXT:    addi a1, zero, -2
 ; RV64IB-NEXT:    rorw a0, a1, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: ror_i32_neg_constant_rhs:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addi a1, zero, 1
-; RV64IBB-NEXT:    slli a1, a1, 32
-; RV64IBB-NEXT:    addi a1, a1, -2
+; RV64IBB-NEXT:    addi a1, zero, -2
 ; RV64IBB-NEXT:    rorw a0, a1, a0
 ; RV64IBB-NEXT:    ret
 ;
 ; RV64IBP-LABEL: ror_i32_neg_constant_rhs:
 ; RV64IBP:       # %bb.0:
-; RV64IBP-NEXT:    addi a1, zero, 1
-; RV64IBP-NEXT:    slli a1, a1, 32
-; RV64IBP-NEXT:    addi a1, a1, -2
+; RV64IBP-NEXT:    addi a1, zero, -2
 ; RV64IBP-NEXT:    rorw a0, a1, a0
 ; RV64IBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 -2, i32 -2, i32 %a)
   ret i32 %1
 }
 
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 

llvm/test/CodeGen/RISCV/xaluo.ll

 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi a2, a0, -2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.i32.constant:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    addi a2, zero, 1
-; RV64-NEXT:    slli a2, a2, 32
-; RV64-NEXT:    addi a3, a2, -2
-; RV64-NEXT:    addw a2, a0, a3
-; RV64-NEXT:    sext.w a4, a0
-; RV64-NEXT:    sltu a2, a2, a4
-; RV64-NEXT:    add a0, a0, a3
+; RV64-NEXT:    sext.w a2, a0
+; RV64-NEXT:    addiw a3, a0, -2
+; RV64-NEXT:    sltu a2, a3, a2
+; RV64-NEXT:    addi a0, a0, -2
 ; RV64-NEXT:    sw a0, 0(a1)
 ; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.i32.constant:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi a2, a0, -2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    sw a2, 0(a1)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.i32.constant:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    addi a2, zero, 1
-; RV64ZBA-NEXT:    slli a2, a2, 32
-; RV64ZBA-NEXT:    addi a3, a2, -2
-; RV64ZBA-NEXT:    addw a2, a0, a3
-; RV64ZBA-NEXT:    sext.w a4, a0
-; RV64ZBA-NEXT:    sltu a2, a2, a4
-; RV64ZBA-NEXT:    add a0, a0, a3
+; RV64ZBA-NEXT:    sext.w a2, a0
+; RV64ZBA-NEXT:    addiw a3, a0, -2
+; RV64ZBA-NEXT:    sltu a2, a3, a2
+; RV64ZBA-NEXT:    addi a0, a0, -2
 ; RV64ZBA-NEXT:    sw a0, 0(a1)
 ; RV64ZBA-NEXT:    mv a0, a2
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 -2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res

 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi a2, a0, 2
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.i32.constant.rhs:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    addi a2, zero, -1
-; RV64-NEXT:    slli a2, a2, 32
-; RV64-NEXT:    addi a3, a2, 2
-; RV64-NEXT:    addw a2, a0, a3
-; RV64-NEXT:    sext.w a4, a0
-; RV64-NEXT:    sltu a2, a4, a2
-; RV64-NEXT:    add a0, a0, a3
+; RV64-NEXT:    addiw a2, a0, 2
+; RV64-NEXT:    sext.w a3, a0
+; RV64-NEXT:    sltu a2, a3, a2
+; RV64-NEXT:    addi a0, a0, 2
 ; RV64-NEXT:    sw a0, 0(a1)
 ; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.i32.constant.rhs:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi a2, a0, 2
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
 ; RV32ZBA-NEXT:    sw a2, 0(a1)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.i32.constant.rhs:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    addi a2, zero, -1
-; RV64ZBA-NEXT:    slli a2, a2, 32
-; RV64ZBA-NEXT:    addi a3, a2, 2
-; RV64ZBA-NEXT:    addw a2, a0, a3
-; RV64ZBA-NEXT:    sext.w a4, a0
-; RV64ZBA-NEXT:    sltu a2, a4, a2
-; RV64ZBA-NEXT:    add a0, a0, a3
+; RV64ZBA-NEXT:    addiw a2, a0, 2
+; RV64ZBA-NEXT:    sext.w a3, a0
+; RV64ZBA-NEXT:    sltu a2, a3, a2
+; RV64ZBA-NEXT:    addi a0, a0, 2
 ; RV64ZBA-NEXT:    sw a0, 0(a1)
 ; RV64ZBA-NEXT:    mv a0, a2
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 -2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit
 }
 
 define zeroext i1 @usubo.i32.constant.lhs(i32 %v1, i32* %res) {
 ; RV32-LABEL: usubo.i32.constant.lhs:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi a2, zero, -2
 ; RV32-NEXT:    sub a2, a2, a0
 ; RV32-NEXT:    addi a0, a2, 1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.i32.constant.lhs:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    addi a2, zero, 1
-; RV64-NEXT:    slli a2, a2, 32
-; RV64-NEXT:    addi a3, a2, -2
+; RV64-NEXT:    addi a3, zero, -2
 ; RV64-NEXT:    subw a2, a3, a0
 ; RV64-NEXT:    addi a2, a2, 1
 ; RV64-NEXT:    seqz a2, a2
 ; RV64-NEXT:    sub a0, a3, a0
 ; RV64-NEXT:    sw a0, 0(a1)
 ; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.i32.constant.lhs:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi a2, zero, -2
 ; RV32ZBA-NEXT:    sub a2, a2, a0
 ; RV32ZBA-NEXT:    addi a0, a2, 1
 ; RV32ZBA-NEXT:    seqz a0, a0
 ; RV32ZBA-NEXT:    sw a2, 0(a1)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.i32.constant.lhs:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    addi a2, zero, 1
-; RV64ZBA-NEXT:    slli a2, a2, 32
-; RV64ZBA-NEXT:    addi a3, a2, -2
+; RV64ZBA-NEXT:    addi a3, zero, -2
 ; RV64ZBA-NEXT:    subw a2, a3, a0
 ; RV64ZBA-NEXT:    addi a2, a2, 1
 ; RV64ZBA-NEXT:    seqz a2, a2
 ; RV64ZBA-NEXT:    sub a0, a3, a0
 ; RV64ZBA-NEXT:    sw a0, 0(a1)
 ; RV64ZBA-NEXT:    mv a0, a2
 ; RV64ZBA-NEXT:    ret
 entry: