[AArch64][SME] Add load and store instructions

[c-rhodes]

Summary

This patch adds support for following contiguous load and store
instructions:

• LD1B, LD1H, LD1W, LD1D, LD1Q
• ST1B, ST1H, ST1W, ST1D, ST1Q

A new register class and operand is added for the 32-bit vector select
register W12-W15. The differences in the following tests which have been
re-generated are caused by the introduction of this register class:

• llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
• llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
• llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
• llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

D88663 attempts to resolve the issue with the store pair test
differences in the AArch64 load/store optimizer.

The GlobalISel differences are caused by changes in the enum values of
register classes, tests have been updated with the new values.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

[CarolineConcatto]

Maybe you should add dependency of this patch with D105570 in the commit message .
The operand needed for Za horizontal and vertical are added there.

llvm/lib/Target/AArch64/SMEInstrFormats.td

360

nit: align

llvm/test/MC/AArch64/SME/st1w-diagnostics.s

3

Is it possible to create a diagnostic test for Match_InvalidMatrixTileVectorH or Match_InvalidMatrixTileVectorV?
They are added in D105570, but I don't see it being used here.

[david-arm]

Hi @c-rhodes, I've not finished reviewing all the tests and instr format td changes yet, but here are some comments so far!

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3027

nit: Just for readability is worth putting braces {} around the outer if-block?

3713–3714

I think you can avoid the if block above entirely if you simply add an extra condition here, right? For example,

(ParseRes == MatchOperand_NoMatch && NoMatchIsError && !RegTok.getString().startswith_insensitive("za"))

That way we just fall through to the default and return MatchOperand_NoMatch, which is what you want I think? It feels like the new if block exists simply to stop the if block below from returning MatchOperand_ParseFail.

3990

Should we be checking for '{' first and reporting an error if it's not? It could be '(', for example.

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

527

Is it worth asserting that RegOpnd >= AArch64::W12 here?

llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

78

I realise adding a new class might have an effect on the other test files, but I'm not sure why this has changed from FPR64 to WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 here?

[david-arm]

llvm/test/MC/AArch64/SME/ld1b-diagnostics.s

5

nit: Does 'za0' refer to what the tile should be? At first I thought za0 was just typed wrong and should be za1.

[c-rhodes]

• Address comments.
• Update sed lines in tests to fix failing Windows precommit.

[c-rhodes]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3990

Should we be checking for '{' first and reporting an error if it's not? It could be '(', for example.

Not sure what you mean here, if the current token isn't { then we wouldn't be here since the case is case AsmToken::LCurly:.

llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

78

I realise adding a new class might have an effect on the other test files, but I'm not sure why this has changed from FPR64 to WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 here?

Not entirely sure myself to be honest, not being familiar with GlobalISel. @aemerson any thoughts on the difference here?

llvm/test/MC/AArch64/SME/ld1b-diagnostics.s

5

nit: Does 'za0' refer to what the tile should be? At first I thought za0 was just typed wrong and should be za1.

Yeah za0 is what's valid, fair point though I can see how that could be confusing, I've clarified the comments by prefixing 'expected: '.

llvm/test/MC/AArch64/SME/st1w-diagnostics.s

3

Is it possible to create a diagnostic test for Match_InvalidMatrixTileVectorH or Match_InvalidMatrixTileVectorV?
They are added in D105570, but I don't see it being used here.

The diagnostics for the matrix operands need some work to be honest, at the moment none of the invalid match types are triggered. Ideally the invalid tile test below would trigger:

case Match_InvalidMatrixTileVectorH32:
  return Error(Loc, "invalid matrix operand, expected za[0-3]h.s");

but za4h.s isn't in matchMatrixRegName so tryParseMatrixRegister returns no match and za4h.s gets parsed as a token, at which point the operand parsing loop in ParseIntruction tries to parse a comma before the next operand, and since there isn't one separating the matrix operand and index, it errors, emitting: 'unexpected token in argument list'.

I suppose we could treat matchMatrixRegName as an error and return MatchOperand_ParseFail. The diagnostic wouldn't be as accurate as what's added in D105570, but it would be an improvement over the current diagnostic which is emitted for the next operand ([).

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

78

I *think*, and please verify my theory here, that this is just because in this test we're hard coding an enum integer 1245194 for FPR64, as the operand for the INLINEASM instruction. If you add a new regclass that could be shifting the entries in the enum so 1245194 is no longer referencing FPR64. You should be able to just find the new integer value for FPR64 and change the test to use that.

[c-rhodes]

• Update enum value of FPR64 regclass in llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir, since the old value is now referencing WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15.
• Tweaked isMatrixRegOperand to return NearMatch to improve diagnostics.
• Added diagnostics tests for load/store instructions where the matrix operand is valid (i.e. it can be parsed) but doesn't match what's expected for the instruction.

[c-rhodes]

llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

78

I *think*, and please verify my theory here, that this is just because in this test we're hard coding an enum integer 1245194 for FPR64, as the operand for the INLINEASM instruction. If you add a new regclass that could be shifting the entries in the enum so 1245194 is no longer referencing FPR64. You should be able to just find the new integer value for FPR64 and change the test to use that.

that seems to be the case, cheers @aemerson! I've took the new enum value for FPR64 from llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll and updated it here.

llvm/test/MC/AArch64/SME/st1w-diagnostics.s

3

Is it possible to create a diagnostic test for Match_InvalidMatrixTileVectorH or Match_InvalidMatrixTileVectorV?
They are added in D105570, but I don't see it being used here.

The diagnostics for the matrix operands need some work to be honest, at the moment none of the invalid match types are triggered. Ideally the invalid tile test below would trigger:

case Match_InvalidMatrixTileVectorH32:
  return Error(Loc, "invalid matrix operand, expected za[0-3]h.s");

but za4h.s isn't in matchMatrixRegName so tryParseMatrixRegister returns no match and za4h.s gets parsed as a token, at which point the operand parsing loop in ParseIntruction tries to parse a comma before the next operand, and since there isn't one separating the matrix operand and index, it errors, emitting: 'unexpected token in argument list'.

I suppose we could treat matchMatrixRegName as an error and return MatchOperand_ParseFail. The diagnostic wouldn't be as accurate as what's added in D105570, but it would be an improvement over the current diagnostic which is emitted for the next operand ([).

Returning MatchOperand_ParseFail broke a bunch of unrelated tests so isn't really an option, but I've tweaked the isMatrixRegOperand predicate to return near match. The diagnostics added in D105570 are now used instead of invalid operand for instruction and I've added more diagnostics tests.

[CarolineConcatto]

Hey @c-rhodes
For me the patch looks ok now.
Just before submit fix the formatting.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

def tvecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
   return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
 }]> {
   let EncoderMethod = "getVecShiftR64OpValue";
   let DecoderMethod = "DecodeVecShiftR64Imm";
   let ParserMatchClass = Imm1_64Operand;
 }
 
 def Imm0_1Operand : AsmImmRange<0, 1>;
+def Imm0_3Operand : AsmImmRange<0, 3>;
 def Imm0_7Operand : AsmImmRange<0, 7>;
 def Imm0_15Operand : AsmImmRange<0, 15>;
 def Imm0_31Operand : AsmImmRange<0, 31>;
 def Imm0_63Operand : AsmImmRange<0, 63>;
 
 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
   return (((uint32_t)Imm) < 8);
 }]> {

 
 // imm0_7 predicate - True if the immediate is in the range [0,7]
 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
   return ((uint64_t)Imm) < 8;
 }]> {
   let ParserMatchClass = Imm0_7Operand;
 }
 
+// imm0_3 predicate - True if the immediate is in the range [0,3]
+def imm0_3 : Operand<i64>, ImmLeaf<i64, [{
+  return ((uint64_t)Imm) < 4;
+}]> {
+  let ParserMatchClass = Imm0_3Operand;
+}
+
 // imm32_0_7 predicate - True if the 32-bit immediate is in the range [0,7]
 def imm32_0_7 : Operand<i32>, TImmLeaf<i32, [{
   return ((uint32_t)Imm) < 8;
 }]> {
   let ParserMatchClass = Imm0_7Operand;
 }
 
 // imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

return 32 - 1                                   // XZR/SP
               - hasBasePointer(MF);  // X19
   case AArch64::FPR8RegClassID:
   case AArch64::FPR16RegClassID:
   case AArch64::FPR32RegClassID:
   case AArch64::FPR64RegClassID:
   case AArch64::FPR128RegClassID:
     return 32;
 
+  case AArch64::MatrixIndexGPR32_12_15RegClassID:
+    return 4;
+
   case AArch64::DDRegClassID:
   case AArch64::DDDRegClassID:
   case AArch64::DDDDRegClassID:
   case AArch64::QQRegClassID:
   case AArch64::QQQRegClassID:
   case AArch64::QQQQRegClassID:
     return 32;
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
   let ParserMethod = "tryParseGPROperand<true>";
 }
 
 class GPR64ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{
   let ParserMatchClass = !cast<AsmOperandClass>(Name);
   let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x', 0>";
 }
 
-foreach Scale = [8, 16, 32, 64] in {
+foreach Scale = [8, 16, 32, 64, 128] in {
   def GPR64shiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64shifted", Scale, "GPR64">;
   def GPR64shifted # Scale : GPR64ExtendRegisterOperand<"GPR64shiftedAsmOpnd" # Scale, Scale, GPR64>;
 
   def GPR64NoXZRshiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64NoXZRshifted", Scale, "GPR64common">;
   def GPR64NoXZRshifted # Scale : GPR64ExtendRegisterOperand<"GPR64NoXZRshiftedAsmOpnd" # Scale, Scale, GPR64common>;
 }
 
 // Accumulator array tiles.

 }
 
 class MatrixOperand<RegisterClass RC, int EltSize> : RegisterOperand<RC> {
   let ParserMatchClass = MatrixAsmOperand<!cast<string>(RC), EltSize>;
   let PrintMethod = "printMatrix<" # EltSize # ">";
 }
 
 def MatrixOp : MatrixOperand<MPR, 0>;
+
+def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>;
+def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
+  let EncoderMethod = "EncodeMatrixIndexGPR32";
+}

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 def SMOPS_MPPZZ_D  : sme_int_outer_product_i64<0b001, "smops">;
 def UMOPA_MPPZZ_D  : sme_int_outer_product_i64<0b110, "umopa">;
 def UMOPS_MPPZZ_D  : sme_int_outer_product_i64<0b111, "umops">;
 def SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa">;
 def SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops">;
 def USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa">;
 def USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops">;
 }
+
+let Predicates = [HasSME] in {
+//===----------------------------------------------------------------------===//
+// Loads and stores
+//===----------------------------------------------------------------------===//
+
+defm LD1_MXIPXX : sme_mem_ld_ss<"ld1">;
+defm ST1_MXIPXX : sme_mem_st_ss<"st1">;
+
+} // End let Predicates = [HasSME]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

if (!KindRes) {
     return MatchOperand_ParseFail;
   }
   unsigned ElementWidth = KindRes->second;
 
   Parser.Lex();
 
   Operands.push_back(AArch64Operand::CreateMatrixRegister(
       Reg, ElementWidth, Kind, S, getLoc(), getContext()));
+
+  if (getLexer().is(AsmToken::LBrac)) {
+    // There's no comma after matrix operand, so we can parse the next operand
+    // immediately.
+    if (parseOperand(Operands, false, false))
+      return MatchOperand_NoMatch;
+  }
   return MatchOperand_Success;
 }
 
 /// tryParseOptionalShift - Some operands take an optional shift argument. Parse
 /// them if present.
 OperandMatchResultTy
 AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
auto ParseVector = [this, &Parser](unsigned &Reg, StringRef &Kind, SMLoc Loc,
     if (ParseRes == MatchOperand_Success) {
       if (parseVectorKind(Kind, VectorKind))
         return ParseRes;
       llvm_unreachable("Expected a valid vector kind");
     }
 
     if (RegTok.isNot(AsmToken::Identifier) ||
         ParseRes == MatchOperand_ParseFail ||
-        (ParseRes == MatchOperand_NoMatch && NoMatchIsError)) {
+        (ParseRes == MatchOperand_NoMatch && NoMatchIsError &&
+         !RegTok.getString().startswith_insensitive("za"))) {
       Error(Loc, "vector register expected");
       return MatchOperand_ParseFail;
     }
 
     return MatchOperand_NoMatch;
   };
 
   SMLoc S = getLoc();
case AsmToken::LBrac: {
     Operands.push_back(AArch64Operand::CreateToken("[", false, Loc,
                                                    getContext()));
     Parser.Lex(); // Eat '['
 
     // There's no comma after a '[', so we can parse the next operand
     // immediately.
     return parseOperand(Operands, false, false);
   }
-  case AsmToken::LCurly:
-    return parseNeonVectorList(Operands);
+  case AsmToken::LCurly: {
+    if (!parseNeonVectorList(Operands))
+      return false;
+
+    SMLoc Loc = Parser.getTok().getLoc();
+    Operands.push_back(AArch64Operand::CreateToken("{", false, Loc,
+                                                   getContext()));
+    Parser.Lex(); // Eat '{'
+
+    // There's no comma after a '{', so we can parse the next operand
+    // immediately.
+    return parseOperand(Operands, false, false);
+  }
   case AsmToken::Identifier: {
     // If we're expecting a Condition Code operand, then just parse that.
     if (isCondCode)
       return parseCondCode(Operands, invertCondCode);
 
     // If it's a register name, parse it.
     if (!parseRegister(Operands))
       return false;
do {
       // Parse and remember the operand.
       if (parseOperand(Operands, (N == 4 && condCodeFourthOperand) ||
                                      (N == 3 && condCodeThirdOperand) ||
                                      (N == 2 && condCodeSecondOperand),
                        condCodeSecondOperand || condCodeThirdOperand)) {
         return true;
       }
 
-      // After successfully parsing some operands there are two special cases to
-      // consider (i.e. notional operands not separated by commas). Both are due
-      // to memory specifiers:
+      // After successfully parsing some operands there are three special cases
+      // to consider (i.e. notional operands not separated by commas). Two are
+      // due to memory specifiers:
       //  + An RBrac will end an address for load/store/prefetch
       //  + An '!' will indicate a pre-indexed operation.
       //
+      // And a further case is '}', which ends a group of tokens specifying the
+      // SME accumulator array 'ZA' or tile vector, i.e.
+      //
+      //   '{ ZA }' or '{ <ZAt><HV>.<BHSDQ>[<Wv>, #<imm>] }'
+      //
       // It's someone else's responsibility to make sure these tokens are sane
       // in the given context!
 
-      SMLoc RLoc = Parser.getTok().getLoc();
       if (parseOptionalToken(AsmToken::RBrac))
         Operands.push_back(
-            AArch64Operand::CreateToken("]", false, RLoc, getContext()));
-      SMLoc ELoc = Parser.getTok().getLoc();
+            AArch64Operand::CreateToken("]", false, getLoc(), getContext()));
       if (parseOptionalToken(AsmToken::Exclaim))
         Operands.push_back(
-            AArch64Operand::CreateToken("!", false, ELoc, getContext()));
+            AArch64Operand::CreateToken("!", false, getLoc(), getContext()));
+      if (parseOptionalToken(AsmToken::RCurly))
+        Operands.push_back(
+            AArch64Operand::CreateToken("}", false, getLoc(), getContext()));
 
       ++N;
     } while (parseOptionalToken(AsmToken::Comma));
   }
 
   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
     return true;
 
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidMemoryIndexed4:
     return Error(Loc, "index must be a multiple of 4 in range [0, 16380].");
   case Match_InvalidMemoryIndexed8:
     return Error(Loc, "index must be a multiple of 8 in range [0, 32760].");
   case Match_InvalidMemoryIndexed16:
     return Error(Loc, "index must be a multiple of 16 in range [0, 65520].");
   case Match_InvalidImm0_1:
     return Error(Loc, "immediate must be an integer in range [0, 1].");
+  case Match_InvalidImm0_3:
+    return Error(Loc, "immediate must be an integer in range [0, 3].");
   case Match_InvalidImm0_7:
     return Error(Loc, "immediate must be an integer in range [0, 7].");
   case Match_InvalidImm0_15:
     return Error(Loc, "immediate must be an integer in range [0, 15].");
   case Match_InvalidImm0_31:
     return Error(Loc, "immediate must be an integer in range [0, 31].");
   case Match_InvalidImm0_63:
     return Error(Loc, "immediate must be an integer in range [0, 63].");
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidGPR64shifted8:
     return Error(Loc, "register must be x0..x30 or xzr, without shift");
   case Match_InvalidGPR64shifted16:
     return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #1'");
   case Match_InvalidGPR64shifted32:
     return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #2'");
   case Match_InvalidGPR64shifted64:
     return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #3'");
+  case Match_InvalidGPR64shifted128:
+    return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #4'");
   case Match_InvalidGPR64NoXZRshifted8:
     return Error(Loc, "register must be x0..x30 without shift");
   case Match_InvalidGPR64NoXZRshifted16:
     return Error(Loc, "register must be x0..x30 with required shift 'lsl #1'");
   case Match_InvalidGPR64NoXZRshifted32:
     return Error(Loc, "register must be x0..x30 with required shift 'lsl #2'");
   case Match_InvalidGPR64NoXZRshifted64:
     return Error(Loc, "register must be x0..x30 with required shift 'lsl #3'");
+  case Match_InvalidGPR64NoXZRshifted128:
+    return Error(Loc, "register must be x0..x30 with required shift 'lsl #4'");
   case Match_InvalidZPR32UXTW8:
   case Match_InvalidZPR32SXTW8:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'");
   case Match_InvalidZPR32UXTW16:
   case Match_InvalidZPR32SXTW16:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'");
   case Match_InvalidZPR32UXTW32:
   case Match_InvalidZPR32SXTW32:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMemoryIndexed16UImm6:
   case Match_InvalidMemoryIndexedSImm6:
   case Match_InvalidMemoryIndexedSImm5:
   case Match_InvalidMemoryIndexedSImm8:
   case Match_InvalidMemoryIndexedSImm9:
   case Match_InvalidMemoryIndexed16SImm9:
   case Match_InvalidMemoryIndexed8SImm10:
   case Match_InvalidImm0_1:
+  case Match_InvalidImm0_3:
   case Match_InvalidImm0_7:
   case Match_InvalidImm0_15:
   case Match_InvalidImm0_31:
   case Match_InvalidImm0_63:
   case Match_InvalidImm0_127:
   case Match_InvalidImm0_255:
   case Match_InvalidImm0_65535:
   case Match_InvalidImm1_8:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEIndexRange0_3:
   case Match_InvalidLabel:
   case Match_InvalidComplexRotationEven:
   case Match_InvalidComplexRotationOdd:
   case Match_InvalidGPR64shifted8:
   case Match_InvalidGPR64shifted16:
   case Match_InvalidGPR64shifted32:
   case Match_InvalidGPR64shifted64:
+  case Match_InvalidGPR64shifted128:
   case Match_InvalidGPR64NoXZRshifted8:
   case Match_InvalidGPR64NoXZRshifted16:
   case Match_InvalidGPR64NoXZRshifted32:
   case Match_InvalidGPR64NoXZRshifted64:
+  case Match_InvalidGPR64NoXZRshifted128:
   case Match_InvalidZPR32UXTW8:
   case Match_InvalidZPR32UXTW16:
   case Match_InvalidZPR32UXTW32:
   case Match_InvalidZPR32UXTW64:
   case Match_InvalidZPR32SXTW8:
   case Match_InvalidZPR32SXTW16:
   case Match_InvalidZPR32SXTW32:
   case Match_InvalidZPR32SXTW64:

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
                                              const void *Decoder);
 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst,
                                                     unsigned RegNo,
                                                     uint64_t Address,
                                                     const void *Decoder);
 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
+static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst,
+                                                              unsigned RegNo,
+                                                              uint64_t Address,
+                                                              const void *Decoder);
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                           uint64_t Address,
DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
   uint32_t Insn =
       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
 
   const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
 
   for (auto Table : Tables) {
     DecodeStatus Result =
         decodeInstruction(Table, MI, Insn, Address, this, STI);
+
+    switch (MI.getOpcode()) {
+    default:
+      break;
+    // For Scalable Matrix Extension (SME) instructions that have an implicit
+    // operand for the accumulator (ZA) which isn't encoded, manually insert
+    // operand.
+    case AArch64::LD1_MXIPXX_H_B:
+    case AArch64::LD1_MXIPXX_V_B:
+    case AArch64::ST1_MXIPXX_H_B:
+    case AArch64::ST1_MXIPXX_V_B:
+      MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0));
+      break;
+    }
+
     if (Result != MCDisassembler::Fail)
       return Result;
   }
 
   return MCDisassembler::Fail;
 }
 
 static MCSymbolizer *
if (RegNo > 31)
     return Fail;
   unsigned Register = GPR64DecoderTable[RegNo];
   if (Register == AArch64::XZR)
     Register = AArch64::SP;
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
+static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = {
+    AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15
+};
+
+static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst,
+                                                              unsigned RegNo,
+                                                              uint64_t Addr,
+                                                              const void *Decoder) {
+  if (RegNo > 3)
+    return Fail;
+
+  unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
 static const unsigned GPR32DecoderTable[] = {
     AArch64::W0,  AArch64::W1,  AArch64::W2,  AArch64::W3,  AArch64::W4,
     AArch64::W5,  AArch64::W6,  AArch64::W7,  AArch64::W8,  AArch64::W9,
     AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
     AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
     AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
     AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
     AArch64::W30, AArch64::WZR

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   case AArch64::GPR64allRegClassID:
   case AArch64::GPR64noipRegClassID:
   case AArch64::GPR64common_and_GPR64noipRegClassID:
   case AArch64::GPR64noip_and_tcGPR64RegClassID:
   case AArch64::tcGPR64RegClassID:
   case AArch64::rtcGPR64RegClassID:
   case AArch64::WSeqPairsClassRegClassID:
   case AArch64::XSeqPairsClassRegClassID:
+  case AArch64::MatrixIndexGPR32_12_15RegClassID:
     return getRegBank(AArch64::GPRRegBankID);
   case AArch64::CCRRegClassID:
     return getRegBank(AArch64::CCRegBankID);
   default:
     llvm_unreachable("Register class not supported");
   }
 }
 

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

public:
 
   template<int hasRs, int hasRt2> unsigned
   fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
                         const MCSubtargetInfo &STI) const;
 
   unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
                                      const MCSubtargetInfo &STI) const;
 
+  uint32_t EncodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
+                                  SmallVectorImpl<MCFixup> &Fixups,
+                                  const MCSubtargetInfo &STI) const;
+
 private:
   FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
   void
   verifyInstructionPredicates(const MCInst &MI,
                               const FeatureBitset &AvailableFeatures) const;
 };
 
 } // end anonymous namespace

 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpIdx);
   assert(MO.isImm() && "Expected an immediate value for the scale amount!");
   return MO.getImm() - 8;
 }
 
+uint32_t AArch64MCCodeEmitter::EncodeMatrixIndexGPR32(
+    const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
+  auto RegOpnd = MI.getOperand(OpIdx).getReg();
+  assert(RegOpnd >= AArch64::W12 && RegOpnd <= AArch64::W15 &&
+         "Expected register in the range w12-w15!");
+  return RegOpnd - AArch64::W12;
+}
+
 uint32_t
 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const {
   // Test shift
   auto ShiftOpnd = MI.getOperand(OpIdx + 1).getImm();
   assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL &&
          "Unexpected shift type for imm8_opt_lsl immediate.");

llvm/lib/Target/AArch64/SMEInstrFormats.td

class sme_add_vector_to_tile_u32<bit V, string mnemonic>
   let Inst{1-0} = ZAda;
 }
 
 class sme_add_vector_to_tile_u64<bit V, string mnemonic>
     : sme_add_vector_to_tile_inst<0b1, V, TileOp64, ZPR64, mnemonic> {
   bits<3> ZAda;
   let Inst{2-0} = ZAda;
 }
+
+//===----------------------------------------------------------------------===//
+// SME Contiguous Loads
+//===----------------------------------------------------------------------===//
+
+class sme_mem_ld_ss_base<bit Q, bit V, bits<2> msz, dag outs, dag ins,
+                         string mnemonic, string argstr>
+    : I<outs, ins, mnemonic, argstr, "", []>, Sched<[]> {
+  bits<5> Rm;
+  bits<2> Rv;
+  bits<3> Pg;
+  bits<5> Rn;
+  let Inst{31-25} = 0b1110000;
+  let Inst{24}    = Q;
+  let Inst{23-22} = msz;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Rm;
+  let Inst{15}    = V;
+  let Inst{14-13} = Rv;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4}     = 0b0;
+
+  let mayLoad = 1;
+}
+
+class sme_mem_ld_ss_inst_BHSD<bits<2> msz, string mnemonic,
+                              MatrixTileVectorOperand tile_ty, bit is_col,
+                              Operand imm_ty, RegisterOperand gpr_ty>
+    : sme_mem_ld_ss_base<
+        0b0, is_col, msz, (outs tile_ty:$ZAt),
+        (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn,
+             gpr_ty:$Rm),
+        mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
+
+class sme_mem_ld_ss_inst_Q<string mnemonic, MatrixTileVectorOperand tile_ty,
+                           bit is_col>
+    : sme_mem_ld_ss_base<
+        0b1, is_col, 0b11, (outs tile_ty:$ZAt),
+        (ins MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn,
+             GPR64shifted128:$Rm),
+        mnemonic, "\t\\{$ZAt[$Rv]\\}, $Pg/z, [$Rn, $Rm]">;
+
+multiclass sme_mem_ss_aliases_BHSD<string mnemonic, Instruction inst,
+                                   MatrixTileVectorOperand tile_ty, Operand imm_ty,
+                                   RegisterOperand gpr_ty,
+                                   string pg_suffix=""> {
+  def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
+  // Default XZR offset aliases
+  def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv, $imm]\\}, $Pg" # pg_suffix # ", [$Rn]",
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
+  def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn]",
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
+}
+
+multiclass sme_mem_ss_aliases_Q<string mnemonic, Instruction inst,
+                                MatrixTileVectorOperand tile_ty,
+                                string pg_suffix=""> {
+  def : InstAlias<mnemonic # "\t$ZAt[$Rv], $Pg" # pg_suffix # ", [$Rn, $Rm]",
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn, GPR64shifted128:$Rm), 0>;
+  // Default XZR offset aliases
+  def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv]\\}, $Pg" # pg_suffix # ", [$Rn]",
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 2>;
+  def : InstAlias<mnemonic # "\t$ZAt[$Rv], $Pg" # pg_suffix # ", [$Rn]",
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
+}
+
+multiclass sme_mem_ss_aliases<string mnemonic, string inst, bit is_col,
+                              string pg_suffix=""> {
+  defm : sme_mem_ss_aliases_BHSD<mnemonic # "b", !cast<Instruction>(inst # _B),
+                                 !if(is_col, TileVectorOpV8, TileVectorOpH8),
+                                 imm0_15, GPR64shifted8, pg_suffix>;
+  defm : sme_mem_ss_aliases_BHSD<mnemonic # "h", !cast<Instruction>(inst # _H),
+                                 !if(is_col, TileVectorOpV16, TileVectorOpH16),
+                                 imm0_7, GPR64shifted16, pg_suffix>;
+  defm : sme_mem_ss_aliases_BHSD<mnemonic # "w", !cast<Instruction>(inst # _S),
+                                 !if(is_col, TileVectorOpV32, TileVectorOpH32),
+                                 imm0_3, GPR64shifted32, pg_suffix>;
+  defm : sme_mem_ss_aliases_BHSD<mnemonic # "d", !cast<Instruction>(inst # _D),
+                                 !if(is_col, TileVectorOpV64, TileVectorOpH64),
+                                 imm0_1, GPR64shifted64, pg_suffix>;
+  defm : sme_mem_ss_aliases_Q   <mnemonic # "q", !cast<Instruction>(inst # _Q),
+                                 !if(is_col, TileVectorOpV128, TileVectorOpH128),
+                                 pg_suffix>;
+}
+
+multiclass sme_mem_ld_ss_aliases<string inst, bit is_col> {
+  defm NAME : sme_mem_ss_aliases<"ld1", inst, is_col, "/z">;
+}
+
+multiclass sme_mem_ld_v_ss<string mnemonic, bit is_col> {
+  def _B : sme_mem_ld_ss_inst_BHSD<0b00, mnemonic # "b",
+                                   !if(is_col, TileVectorOpV8,
+                                               TileVectorOpH8),
+                                   is_col, imm0_15, GPR64shifted8> {
+    bits<4> imm;
+    let Inst{3-0} = imm;
+  }
+  def _H : sme_mem_ld_ss_inst_BHSD<0b01, mnemonic # "h",
+                                   !if(is_col, TileVectorOpV16,
+                                               TileVectorOpH16),
+                                   is_col, imm0_7, GPR64shifted16> {
+    bits<1> ZAt;
+    bits<3> imm;
+    let Inst{3}   = ZAt;
+    let Inst{2-0} = imm;
+  }
+  def _S : sme_mem_ld_ss_inst_BHSD<0b10, mnemonic # "w",
+                                   !if(is_col, TileVectorOpV32,
+                                               TileVectorOpH32),
+                                   is_col, imm0_3, GPR64shifted32> {
+    bits<2> ZAt;
+    bits<2> imm;
+    let Inst{3-2} = ZAt;
+    let Inst{1-0} = imm;
+  }
+  def _D : sme_mem_ld_ss_inst_BHSD<0b11, mnemonic # "d",
+                                   !if(is_col, TileVectorOpV64,
+                                               TileVectorOpH64),
+                                   is_col, imm0_1, GPR64shifted64> {
+    bits<3> ZAt;
+    bits<1> imm;
+    let Inst{3-1} = ZAt;
+    let Inst{0}   = imm;
+  }
+  def _Q : sme_mem_ld_ss_inst_Q<mnemonic # "q",
+                                !if(is_col, TileVectorOpV128,
+                                            TileVectorOpH128),
+                                is_col> {
+    bits<4> ZAt;
+    let Inst{3-0} = ZAt;
+  }
+
+  defm : sme_mem_ld_ss_aliases<NAME, is_col>;
+}
+
+multiclass sme_mem_ld_ss<string mnemonic> {
+  defm _H : sme_mem_ld_v_ss<mnemonic, /*is_col=*/0b0>;
+  defm _V : sme_mem_ld_v_ss<mnemonic, /*is_col=*/0b1>;
+}
+
+//===----------------------------------------------------------------------===//
+// SME Contiguous Stores
+//===----------------------------------------------------------------------===//
+
+class sme_mem_st_ss_base<bit Q, bit V, bits<2> msz, dag ins,
+                         string mnemonic, string argstr>
+    : I<(outs), ins, mnemonic, argstr, "", []>, Sched<[]> {
+  bits<5> Rm;
+  bits<2> Rv;
+  bits<3> Pg;
+  bits<5> Rn;
+  let Inst{31-25} = 0b1110000;
+  let Inst{24}    = Q;
+  let Inst{23-22} = msz;
+  let Inst{21}    = 0b1;
+  let Inst{20-16} = Rm;
+  let Inst{15}    = V;
+  let Inst{14-13} = Rv;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Rn;
+  let Inst{4}     = 0b0;
+
+  let mayStore = 1;
+  let hasSideEffects = 1;
+}
+
+class sme_mem_st_ss_inst_BHSD<bits<2> msz, string mnemonic,
+                              MatrixTileVectorOperand tile_ty, bit is_col,
+                              Operand imm_ty, RegisterOperand gpr_ty>
+    : sme_mem_st_ss_base<
+        0b0, is_col, msz,
+        (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg,
+             GPR64sp:$Rn, gpr_ty:$Rm),
+        mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
+
+class sme_mem_st_ss_inst_Q<string mnemonic, MatrixTileVectorOperand tile_ty,
+                           bit is_col>
+    : sme_mem_st_ss_base<
+        0b1, is_col, 0b11,
+        (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, PPR3bAny:$Pg,
+             GPR64sp:$Rn, GPR64shifted128:$Rm),
+        mnemonic, "\t\\{$ZAt[$Rv]\\}, $Pg, [$Rn, $Rm]">;
+
+multiclass sme_mem_st_ss_aliases<string inst, bit is_col> {
+  defm NAME : sme_mem_ss_aliases<"st1", inst, is_col>;
+}
+
+multiclass sme_mem_st_v_ss<string mnemonic, bit is_col> {
+  def _B : sme_mem_st_ss_inst_BHSD<0b00, mnemonic # "b",
+                                   !if(is_col, TileVectorOpV8,
+                                               TileVectorOpH8),
+                                   is_col, imm0_15, GPR64shifted8> {
+    bits<4> imm;
+    let Inst{3-0} = imm;
+  }
+  def _H : sme_mem_st_ss_inst_BHSD<0b01, mnemonic # "h",
+                                   !if(is_col, TileVectorOpV16,
+                                               TileVectorOpH16),
+                                   is_col, imm0_7, GPR64shifted16> {
+    bits<1> ZAt;
+    bits<3> imm;
+    let Inst{3}   = ZAt;
+    let Inst{2-0} = imm;
+  }
+  def _S : sme_mem_st_ss_inst_BHSD<0b10, mnemonic # "w",
+                                   !if(is_col, TileVectorOpV32,
+                                               TileVectorOpH32),
+                                   is_col, imm0_3, GPR64shifted32> {
+    bits<2> ZAt;
+    bits<2> imm;
+    let Inst{3-2} = ZAt;
+    let Inst{1-0} = imm;
+  }
+  def _D : sme_mem_st_ss_inst_BHSD<0b11, mnemonic # "d",
+                                   !if(is_col, TileVectorOpV64,
+                                               TileVectorOpH64),
+                                   is_col, imm0_1, GPR64shifted64> {
+    bits<3> ZAt;
+    bits<1> imm;
+    let Inst{3-1} = ZAt;
+    let Inst{0}   = imm;
+  }
+  def _Q : sme_mem_st_ss_inst_Q<mnemonic # "q",
+                                !if(is_col, TileVectorOpV128,
+                                            TileVectorOpH128),
+                                is_col> {
+    bits<4> ZAt;
+    let Inst{3-0} = ZAt;
+  }
+
+  defm : sme_mem_st_ss_aliases<NAME, is_col>;
+}
+
+multiclass sme_mem_st_ss<string mnemonic> {
+  defm _H : sme_mem_st_v_ss<mnemonic, /*is_col=*/0b0>;
+  defm _V : sme_mem_st_v_ss<mnemonic, /*is_col=*/0b1>;
+}
+

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll

define void @asm_simple_register_clobber() {
   ; CHECK:   RET_ReallyLR
   call void asm sideeffect "mov x0, 7", "~{x0}"(), !srcloc !0
   ret void
 }
 
 define i64 @asm_register_early_clobber() {
   ; CHECK-LABEL: name: asm_register_early_clobber
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK:   INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 1441803 /* regdef-ec:GPR64common */, def early-clobber %0, 1441803 /* regdef-ec:GPR64common */, def early-clobber %1, !0
+  ; CHECK:   INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 1572875 /* regdef-ec:GPR64common */, def early-clobber %0, 1572875 /* regdef-ec:GPR64common */, def early-clobber %1, !0
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY %0
   ; CHECK:   [[COPY1:%[0-9]+]]:_(s64) = COPY %1
   ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
   ; CHECK:   $x0 = COPY [[ADD]](s64)
   ; CHECK:   RET_ReallyLR implicit $x0
   call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !0
   %asmresult = extractvalue { i64, i64 } %1, 0
   %asmresult1 = extractvalue { i64, i64 } %1, 1

 entry:
   %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
   ret i32 %0
 }
 
 define i64 @test_single_register_output_s64() nounwind ssp {
   ; CHECK-LABEL: name: test_single_register_output_s64
   ; CHECK: bb.1.entry:
-  ; CHECK:   INLINEASM &"mov $0, 7", 0 /* attdialect */, 1441802 /* regdef:GPR64common */, def %0
+  ; CHECK:   INLINEASM &"mov $0, 7", 0 /* attdialect */, 1572874 /* regdef:GPR64common */, def %0
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY %0
   ; CHECK:   $x0 = COPY [[COPY]](s64)
   ; CHECK:   RET_ReallyLR implicit $x0
 entry:
   %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind
   ret i64 %0
 }
 
define float @test_multiple_register_outputs_same() #0 {
   %add = fadd float %asmresult, %asmresult1
   ret float %add
 }
 
 ; Check support for returning several floats
 define double @test_multiple_register_outputs_mixed() #0 {
   ; CHECK-LABEL: name: test_multiple_register_outputs_mixed
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1245194 /* regdef:FPR64 */, def %1
+  ; CHECK:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1376266 /* regdef:FPR64 */, def %1
   ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK:   [[COPY1:%[0-9]+]]:_(s64) = COPY %1
   ; CHECK:   $d0 = COPY [[COPY1]](s64)
   ; CHECK:   RET_ReallyLR implicit $d0
   %1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"()
   %asmresult = extractvalue { float, double } %1, 1
   ret double %asmresult
 }
define float @test_vector_output() nounwind {
   ret float %2
 }
 
 define void @test_input_register_imm() {
   ; CHECK-LABEL: name: test_input_register_imm
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
-  ; CHECK:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 1441801 /* reguse:GPR64common */, [[COPY]]
+  ; CHECK:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 1572873 /* reguse:GPR64common */, [[COPY]]
   ; CHECK:   RET_ReallyLR
   call void asm sideeffect "mov x0, $0", "r"(i64 42)
   ret void
 }
 
 ; Make sure that boolean immediates are properly (zero) extended.
 define i32 @test_boolean_imm_ext() {
   ; CHECK-LABEL: name: test_boolean_imm_ext

 }
 
 define zeroext i8 @test_input_register(i8* %src) nounwind {
   ; CHECK-LABEL: name: test_input_register
   ; CHECK: bb.1.entry:
   ; CHECK:   liveins: $x0
   ; CHECK:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
-  ; CHECK:   INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %1, 1441801 /* reguse:GPR64common */, [[COPY1]]
+  ; CHECK:   INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %1, 1572873 /* reguse:GPR64common */, [[COPY1]]
   ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
   ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
   ; CHECK:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
 entry:
   %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind
   ret i8 %0

llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

 ---
 name:            inlineasm_virt_mixed_types
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.1:
     ; CHECK-LABEL: name: inlineasm_virt_mixed_types
-    ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1245194 /* regdef:FPR64 */, def %1
+    ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1245194 /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1
     ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
     ; CHECK: $d0 = COPY [[COPY1]](s64)
     ; CHECK: RET_ReallyLR implicit $d0
     INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0:gpr32common, 1245194 /* regdef:FPR64 */, def %1:fpr64
     %3:_(s32) = COPY %0
     %4:_(s64) = COPY %1
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 ...

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir

 # RUN: llc -run-pass=aarch64-ldst-opt -aarch64-load-store-renaming=true -mattr=+reserve-x10 \
 # RUN:     -mattr=+reserve-x11 -mattr=+reserve-x15 -mtriple=arm64-apple-iphoneos -verify-machineinstrs \
 # RUN:     -o - %s | FileCheck --check-prefix=CHECK --check-prefix=PRESERVED %s
 
 # RUN: llc -run-pass=aarch64-ldst-opt -aarch64-load-store-renaming=true -mtriple=arm64-apple-iphoneos \
 # RUN:     -verify-machineinstrs -o - %s | FileCheck --check-prefix=CHECK --check-prefix=NOPRES %s
 
 
 # Make sure we do not pick reserved registers. For test1, we would pick x10,
 # and for test2 we would pick x15, both of which are reserved.
 #
 ---
 # CHECK-LABEL: name: test1
 # CHECK:       bb.0:
 # CHECK-NEXT:     liveins: $x0, $x1
-# PRESERVED:      $x12, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
+# PRESERVED:      $x18, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
 # NOPRES:         $x10, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
 # CHECK-NEXT:     renamable $x9 = LDRXui renamable $x0, 1 :: (load (s64))
 # CHECK-NEXT:     STRXui renamable $x9, renamable $x0, 100 :: (store (s64), align 4)
 # CHECK-NEXT:     renamable $x8 = ADDXrr $x8, $x8
-# PRESERVED-NEXT: STPXi renamable $x8, killed $x12, renamable $x0, 10 :: (store (s64), align 4)
+# PRESERVED-NEXT: STPXi renamable $x8, killed $x18, renamable $x0, 10 :: (store (s64), align 4)
 # NOPRES-NEXT:    STPXi renamable $x8, killed $x10, renamable $x0, 10 :: (store (s64), align 4)
 # CHECK-NEXT:     RET undef $lr
 
 name:            test1
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
bb.0:
     RET undef $lr
 
 ...
 # CHECK-LABEL: name: test2
 # CHECK:       bb.0:
 # CHECK-NEXT:     liveins: $x0, $x1, $x10, $x11, $x12, $x13
 # CHECK:          renamable $w19 = LDRWui renamable $x0, 0 :: (load (s64))
 # PRESERVED-NEXT: $x18, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
-# NOPRES-NEXT:    $x15, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
+# NOPRES-NEXT:    $x18, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
 # CHECK-NEXT:     renamable $x9 = LDRXui renamable $x0, 3 :: (load (s64))
 # CHECK-NEXT:     renamable $x14 = LDRXui renamable $x0, 5 :: (load (s64))
 # PRESERVED-NEXT: STPXi renamable $x9, killed $x18, renamable $x0, 10 :: (store (s64), align 4)
-# NOPRES-NEXT:    STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store (s64), align 4)
+# NOPRES-NEXT:    STPXi renamable $x9, killed $x18, renamable $x0, 10 :: (store (s64), align 4)
 # CHECK-NEXT:     STRXui killed renamable $x14, renamable $x0, 200 :: (store (s64), align 4)
 # CHECK-NEXT:     renamable $w8 = ADDWrr $w19, $w19
 # CHECK-NEXT:     STRWui renamable $w8, renamable $x0, 100 :: (store (s64), align 4)
 # CHECK-NEXT:     RET undef $lr
 #
 name:            test2
 alignment:       4
 tracksRegLiveness: true

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

 ---
 # Make sure we do not use any registers that are defined between paired candidates
 # ($x14 in this example)
 # CHECK-LABEL: name: test11
 # CHECK: bb.0:
 # CHECK-NEXT: liveins: $x0, $x1, $x11, $x12, $x13
 
 # CHECK:         renamable $w10 = LDRWui renamable $x0, 0 :: (load (s64))
-# CHECK-NEXT:    $x15, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
+# CHECK-NEXT:    $x18, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
 # CHECK-NEXT:    renamable $x9 = LDRXui renamable $x0, 3 :: (load (s64))
 # CHECK-NEXT:    renamable $x14 = LDRXui renamable $x0, 5 :: (load (s64))
-# CHECK-NEXT:    STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store (s64), align 4)
+# CHECK-NEXT:    STPXi renamable $x9, killed $x18, renamable $x0, 10 :: (store (s64), align 4)
 # CHECK-NEXT:    STRXui killed renamable $x14, renamable $x0, 200 :: (store (s64), align 4)
 # CHECK-NEXT:    renamable $w8 = ADDWrr $w10, $w10
 # CHECK-NEXT:    STRWui renamable $w8, renamable $x0, 100 :: (store (s64), align 4)
 # CHECK-NEXT:    RET undef $lr
 #
 name:            test11
 alignment:       4
 tracksRegLiveness: true

 
 ...
 ---
 # Make sure we do not use any registers that are defined between def to rename and the first
 # paired store. ($x14 in this example)
 # CHECK-LABEL: name: test13
 # CHECK: bb.0:
 # CHECK-NEXT: liveins: $x0, $x1, $x10, $x11, $x12, $x13
-# CHECK:        $x15, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
+# CHECK:        $x18, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
 # CHECK-NEXT:    renamable $x14 = LDRXui renamable $x0, 4 :: (load (s64))
 # CHECK-NEXT:    STRXui killed renamable $x14, renamable $x0, 100 :: (store (s64), align 4)
 # CHECK-NEXT:    renamable $x9 = LDRXui renamable $x0, 2 :: (load (s64))
-# CHECK-NEXT:    STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store (s64), align 4)
+# CHECK-NEXT:    STPXi renamable $x9, killed $x18, renamable $x0, 10 :: (store (s64), align 4)
 # CHECK-NEXT:    RET undef $lr
 #
 name:            test13
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }

llvm/test/MC/AArch64/SME/ld1b-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0)
+
+ld1b {za1h.b[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: ld1b {za1h.b[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+ld1b {za0h.b[w11, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1b {za0h.b[w11, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {za0h.b[w16, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1b {za0h.b[w16, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-15)
+
+ld1b {za0h.b[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
+// CHECK-NEXT: ld1b {za0h.b[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {za0h.b[w12, #16]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
+// CHECK-NEXT: ld1b {za0h.b[w12, #16]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+ld1b {za0h.b[w12, #0]}, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate qualifier (expected: /z)
+
+ld1b {za0h.b[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+ld1b {za0h.b[w12, #0]}, p0/z, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/z, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {za0h.b[w12, #0]}, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
+// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
+// CHECK-NEXT: ld1b {za0h.b[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/ld1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+ld1b    {za0h.b[w12, #0]}, p0/z, [x0, x0]
+// CHECK-INST: ld1b    {za0h.b[w12, #0]}, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x00,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 00 e0 <unknown>
+
+ld1b    {za0h.b[w14, #5]}, p5/z, [x10, x21]
+// CHECK-INST: ld1b    {za0h.b[w14, #5]}, p5/z, [x10, x21]
+// CHECK-ENCODING: [0x45,0x55,0x15,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 15 e0 <unknown>
+
+ld1b    {za0h.b[w15, #7]}, p3/z, [x13, x8]
+// CHECK-INST: ld1b    {za0h.b[w15, #7]}, p3/z, [x13, x8]
+// CHECK-ENCODING: [0xa7,0x6d,0x08,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 08 e0 <unknown>
+
+ld1b    {za0h.b[w15, #15]}, p7/z, [sp]
+// CHECK-INST: ld1b    {za0h.b[w15, #15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x1f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 1f e0 <unknown>
+
+ld1b    {za0h.b[w12, #5]}, p3/z, [x17, x16]
+// CHECK-INST: ld1b    {za0h.b[w12, #5]}, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0x0e,0x10,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 10 e0 <unknown>
+
+ld1b    {za0h.b[w12, #1]}, p1/z, [x1, x30]
+// CHECK-INST: ld1b    {za0h.b[w12, #1]}, p1/z, [x1, x30]
+// CHECK-ENCODING: [0x21,0x04,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 1e e0 <unknown>
+
+ld1b    {za0h.b[w14, #8]}, p5/z, [x19, x20]
+// CHECK-INST: ld1b    {za0h.b[w14, #8]}, p5/z, [x19, x20]
+// CHECK-ENCODING: [0x68,0x56,0x14,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 14 e0 <unknown>
+
+ld1b    {za0h.b[w12, #0]}, p6/z, [x12, x2]
+// CHECK-INST: ld1b    {za0h.b[w12, #0]}, p6/z, [x12, x2]
+// CHECK-ENCODING: [0x80,0x19,0x02,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 02 e0 <unknown>
+
+ld1b    {za0h.b[w14, #1]}, p2/z, [x1, x26]
+// CHECK-INST: ld1b    {za0h.b[w14, #1]}, p2/z, [x1, x26]
+// CHECK-ENCODING: [0x21,0x48,0x1a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 1a e0 <unknown>
+
+ld1b    {za0h.b[w12, #13]}, p2/z, [x22, x30]
+// CHECK-INST: ld1b    {za0h.b[w12, #13]}, p2/z, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x0a,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 1e e0 <unknown>
+
+ld1b    {za0h.b[w15, #2]}, p5/z, [x9, x1]
+// CHECK-INST: ld1b    {za0h.b[w15, #2]}, p5/z, [x9, x1]
+// CHECK-ENCODING: [0x22,0x75,0x01,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 01 e0 <unknown>
+
+ld1b    {za0h.b[w13, #7]}, p2/z, [x12, x11]
+// CHECK-INST: ld1b    {za0h.b[w13, #7]}, p2/z, [x12, x11]
+// CHECK-ENCODING: [0x87,0x29,0x0b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 0b e0 <unknown>
+
+ld1b    za0h.b[w12, #0], p0/z, [x0, x0]
+// CHECK-INST: ld1b    {za0h.b[w12, #0]}, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x00,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 00 e0 <unknown>
+
+ld1b    za0h.b[w14, #5], p5/z, [x10, x21]
+// CHECK-INST: ld1b    {za0h.b[w14, #5]}, p5/z, [x10, x21]
+// CHECK-ENCODING: [0x45,0x55,0x15,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 15 e0 <unknown>
+
+ld1b    za0h.b[w15, #7], p3/z, [x13, x8]
+// CHECK-INST: ld1b    {za0h.b[w15, #7]}, p3/z, [x13, x8]
+// CHECK-ENCODING: [0xa7,0x6d,0x08,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 08 e0 <unknown>
+
+ld1b    za0h.b[w15, #15], p7/z, [sp]
+// CHECK-INST: ld1b    {za0h.b[w15, #15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x1f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 1f e0 <unknown>
+
+ld1b    za0h.b[w12, #5], p3/z, [x17, x16]
+// CHECK-INST: ld1b    {za0h.b[w12, #5]}, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0x0e,0x10,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 10 e0 <unknown>
+
+ld1b    za0h.b[w12, #1], p1/z, [x1, x30]
+// CHECK-INST: ld1b    {za0h.b[w12, #1]}, p1/z, [x1, x30]
+// CHECK-ENCODING: [0x21,0x04,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 1e e0 <unknown>
+
+ld1b    za0h.b[w14, #8], p5/z, [x19, x20]
+// CHECK-INST: ld1b    {za0h.b[w14, #8]}, p5/z, [x19, x20]
+// CHECK-ENCODING: [0x68,0x56,0x14,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 14 e0 <unknown>
+
+ld1b    za0h.b[w12, #0], p6/z, [x12, x2]
+// CHECK-INST: ld1b    {za0h.b[w12, #0]}, p6/z, [x12, x2]
+// CHECK-ENCODING: [0x80,0x19,0x02,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 02 e0 <unknown>
+
+ld1b    za0h.b[w14, #1], p2/z, [x1, x26]
+// CHECK-INST: ld1b    {za0h.b[w14, #1]}, p2/z, [x1, x26]
+// CHECK-ENCODING: [0x21,0x48,0x1a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 1a e0 <unknown>
+
+ld1b    za0h.b[w12, #13], p2/z, [x22, x30]
+// CHECK-INST: ld1b    {za0h.b[w12, #13]}, p2/z, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x0a,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 1e e0 <unknown>
+
+ld1b    za0h.b[w15, #2], p5/z, [x9, x1]
+// CHECK-INST: ld1b    {za0h.b[w15, #2]}, p5/z, [x9, x1]
+// CHECK-ENCODING: [0x22,0x75,0x01,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 01 e0 <unknown>
+
+ld1b    za0h.b[w13, #7], p2/z, [x12, x11]
+// CHECK-INST: ld1b    {za0h.b[w13, #7]}, p2/z, [x12, x11]
+// CHECK-ENCODING: [0x87,0x29,0x0b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 0b e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+ld1b    {za0v.b[w12, #0]}, p0/z, [x0, x0]
+// CHECK-INST: ld1b    {za0v.b[w12, #0]}, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x00,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 00 e0 <unknown>
+
+ld1b    {za0v.b[w14, #5]}, p5/z, [x10, x21]
+// CHECK-INST: ld1b    {za0v.b[w14, #5]}, p5/z, [x10, x21]
+// CHECK-ENCODING: [0x45,0xd5,0x15,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 15 e0 <unknown>
+
+ld1b    {za0v.b[w15, #7]}, p3/z, [x13, x8]
+// CHECK-INST: ld1b    {za0v.b[w15, #7]}, p3/z, [x13, x8]
+// CHECK-ENCODING: [0xa7,0xed,0x08,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 08 e0 <unknown>
+
+ld1b    {za0v.b[w15, #15]}, p7/z, [sp]
+// CHECK-INST: ld1b    {za0v.b[w15, #15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x1f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 1f e0 <unknown>
+
+ld1b    {za0v.b[w12, #5]}, p3/z, [x17, x16]
+// CHECK-INST: ld1b    {za0v.b[w12, #5]}, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0x8e,0x10,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 10 e0 <unknown>
+
+ld1b    {za0v.b[w12, #1]}, p1/z, [x1, x30]
+// CHECK-INST: ld1b    {za0v.b[w12, #1]}, p1/z, [x1, x30]
+// CHECK-ENCODING: [0x21,0x84,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 1e e0 <unknown>
+
+ld1b    {za0v.b[w14, #8]}, p5/z, [x19, x20]
+// CHECK-INST: ld1b    {za0v.b[w14, #8]}, p5/z, [x19, x20]
+// CHECK-ENCODING: [0x68,0xd6,0x14,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 14 e0 <unknown>
+
+ld1b    {za0v.b[w12, #0]}, p6/z, [x12, x2]
+// CHECK-INST: ld1b    {za0v.b[w12, #0]}, p6/z, [x12, x2]
+// CHECK-ENCODING: [0x80,0x99,0x02,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 02 e0 <unknown>
+
+ld1b    {za0v.b[w14, #1]}, p2/z, [x1, x26]
+// CHECK-INST: ld1b    {za0v.b[w14, #1]}, p2/z, [x1, x26]
+// CHECK-ENCODING: [0x21,0xc8,0x1a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 1a e0 <unknown>
+
+ld1b    {za0v.b[w12, #13]}, p2/z, [x22, x30]
+// CHECK-INST: ld1b    {za0v.b[w12, #13]}, p2/z, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x8a,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 1e e0 <unknown>
+
+ld1b    {za0v.b[w15, #2]}, p5/z, [x9, x1]
+// CHECK-INST: ld1b    {za0v.b[w15, #2]}, p5/z, [x9, x1]
+// CHECK-ENCODING: [0x22,0xf5,0x01,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 01 e0 <unknown>
+
+ld1b    {za0v.b[w13, #7]}, p2/z, [x12, x11]
+// CHECK-INST: ld1b    {za0v.b[w13, #7]}, p2/z, [x12, x11]
+// CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 0b e0 <unknown>
+
+ld1b    za0v.b[w12, #0], p0/z, [x0, x0]
+// CHECK-INST: ld1b    {za0v.b[w12, #0]}, p0/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x00,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 00 e0 <unknown>
+
+ld1b    za0v.b[w14, #5], p5/z, [x10, x21]
+// CHECK-INST: ld1b    {za0v.b[w14, #5]}, p5/z, [x10, x21]
+// CHECK-ENCODING: [0x45,0xd5,0x15,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 15 e0 <unknown>
+
+ld1b    za0v.b[w15, #7], p3/z, [x13, x8]
+// CHECK-INST: ld1b    {za0v.b[w15, #7]}, p3/z, [x13, x8]
+// CHECK-ENCODING: [0xa7,0xed,0x08,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 08 e0 <unknown>
+
+ld1b    za0v.b[w15, #15], p7/z, [sp]
+// CHECK-INST: ld1b    {za0v.b[w15, #15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x1f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 1f e0 <unknown>
+
+ld1b    za0v.b[w12, #5], p3/z, [x17, x16]
+// CHECK-INST: ld1b    {za0v.b[w12, #5]}, p3/z, [x17, x16]
+// CHECK-ENCODING: [0x25,0x8e,0x10,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 10 e0 <unknown>
+
+ld1b    za0v.b[w12, #1], p1/z, [x1, x30]
+// CHECK-INST: ld1b    {za0v.b[w12, #1]}, p1/z, [x1, x30]
+// CHECK-ENCODING: [0x21,0x84,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 1e e0 <unknown>
+
+ld1b    za0v.b[w14, #8], p5/z, [x19, x20]
+// CHECK-INST: ld1b    {za0v.b[w14, #8]}, p5/z, [x19, x20]
+// CHECK-ENCODING: [0x68,0xd6,0x14,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 14 e0 <unknown>
+
+ld1b    za0v.b[w12, #0], p6/z, [x12, x2]
+// CHECK-INST: ld1b    {za0v.b[w12, #0]}, p6/z, [x12, x2]
+// CHECK-ENCODING: [0x80,0x99,0x02,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 02 e0 <unknown>
+
+ld1b    za0v.b[w14, #1], p2/z, [x1, x26]
+// CHECK-INST: ld1b    {za0v.b[w14, #1]}, p2/z, [x1, x26]
+// CHECK-ENCODING: [0x21,0xc8,0x1a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 1a e0 <unknown>
+
+ld1b    za0v.b[w12, #13], p2/z, [x22, x30]
+// CHECK-INST: ld1b    {za0v.b[w12, #13]}, p2/z, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x8a,0x1e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 1e e0 <unknown>
+
+ld1b    za0v.b[w15, #2], p5/z, [x9, x1]
+// CHECK-INST: ld1b    {za0v.b[w15, #2]}, p5/z, [x9, x1]
+// CHECK-ENCODING: [0x22,0xf5,0x01,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 01 e0 <unknown>
+
+ld1b    za0v.b[w13, #7], p2/z, [x12, x11]
+// CHECK-INST: ld1b    {za0v.b[w13, #7]}, p2/z, [x12, x11]
+// CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 0b e0 <unknown>

llvm/test/MC/AArch64/SME/ld1d-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za7)
+
+ld1d {za8h.d[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: ld1d {za8h.d[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+ld1d {za0h.d[w11, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d {za0h.d[w11, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {za0h.d[w16, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d {za0h.d[w16, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-1)
+
+ld1d {za0h.d[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: ld1d {za0h.d[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {za0h.d[w12, #2]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: ld1d {za0h.d[w12, #2]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+ld1d {za0h.d[w12, #0]}, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate qualifier (expected: /z)
+
+ld1d {za0h.d[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+ld1d {za0h.d[w12, #0]}, p0/z, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/z, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {za0h.d[w12, #0]}, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK-NEXT: ld1d {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/ld1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+ld1d    {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 c0 e0 <unknown>
+
+ld1d    {za2h.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d    {za2h.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0x55,0xd5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 d5 e0 <unknown>
+
+ld1d    {za3h.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d    {za3h.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d c8 e0 <unknown>
+
+ld1d    {za7h.d[w15, #1]}, p7/z, [sp]
+// CHECK-INST: ld1d    {za7h.d[w15, #1]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f df e0 <unknown>
+
+ld1d    {za2h.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d    {za2h.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e d0 e0 <unknown>
+
+ld1d    {za0h.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x04,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 de e0 <unknown>
+
+ld1d    {za4h.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d    {za4h.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0x56,0xd4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 d4 e0 <unknown>
+
+ld1d    {za0h.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x19,0xc2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 c2 e0 <unknown>
+
+ld1d    {za0h.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0x48,0xda,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 da e0 <unknown>
+
+ld1d    {za6h.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d    {za6h.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a de e0 <unknown>
+
+ld1d    {za1h.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d    {za1h.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0x75,0xc1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 c1 e0 <unknown>
+
+ld1d    {za3h.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d    {za3h.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0x29,0xcb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 cb e0 <unknown>
+
+ld1d    za0h.d[w12, #0], p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 c0 e0 <unknown>
+
+ld1d    za2h.d[w14, #1], p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d    {za2h.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0x55,0xd5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 d5 e0 <unknown>
+
+ld1d    za3h.d[w15, #1], p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d    {za3h.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d c8 e0 <unknown>
+
+ld1d    za7h.d[w15, #1], p7/z, [sp]
+// CHECK-INST: ld1d    {za7h.d[w15, #1]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f df e0 <unknown>
+
+ld1d    za2h.d[w12, #1], p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d    {za2h.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e d0 e0 <unknown>
+
+ld1d    za0h.d[w12, #1], p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x04,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 de e0 <unknown>
+
+ld1d    za4h.d[w14, #0], p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d    {za4h.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0x56,0xd4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 d4 e0 <unknown>
+
+ld1d    za0h.d[w12, #0], p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x19,0xc2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 c2 e0 <unknown>
+
+ld1d    za0h.d[w14, #1], p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d    {za0h.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0x48,0xda,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 da e0 <unknown>
+
+ld1d    za6h.d[w12, #1], p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d    {za6h.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a de e0 <unknown>
+
+ld1d    za1h.d[w15, #0], p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d    {za1h.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0x75,0xc1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 c1 e0 <unknown>
+
+ld1d    za3h.d[w13, #1], p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d    {za3h.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0x29,0xcb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 cb e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+ld1d    {za0v.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x80,0xc0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 c0 e0 <unknown>
+
+ld1d    {za2v.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d    {za2v.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 d5 e0 <unknown>
+
+ld1d    {za3v.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d    {za3v.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed c8 e0 <unknown>
+
+ld1d    {za7v.d[w15, #1]}, p7/z, [sp]
+// CHECK-INST: ld1d    {za7v.d[w15, #1]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xdf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff df e0 <unknown>
+
+ld1d    {za2v.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d    {za2v.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e d0 e0 <unknown>
+
+ld1d    {za0v.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x84,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 de e0 <unknown>
+
+ld1d    {za4v.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d    {za4v.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 d4 e0 <unknown>
+
+ld1d    {za0v.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x99,0xc2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 c2 e0 <unknown>
+
+ld1d    {za0v.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0xc8,0xda,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 da e0 <unknown>
+
+ld1d    {za6v.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d    {za6v.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a de e0 <unknown>
+
+ld1d    {za1v.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d    {za1v.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 c1 e0 <unknown>
+
+ld1d    {za3v.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d    {za3v.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 cb e0 <unknown>
+
+ld1d    za0v.d[w12, #0], p0/z, [x0, x0, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x80,0xc0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 c0 e0 <unknown>
+
+ld1d    za2v.d[w14, #1], p5/z, [x10, x21, lsl #3]
+// CHECK-INST: ld1d    {za2v.d[w14, #1]}, p5/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 d5 e0 <unknown>
+
+ld1d    za3v.d[w15, #1], p3/z, [x13, x8, lsl #3]
+// CHECK-INST: ld1d    {za3v.d[w15, #1]}, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed c8 e0 <unknown>
+
+ld1d    za7v.d[w15, #1], p7/z, [sp]
+// CHECK-INST: ld1d    {za7v.d[w15, #1]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xdf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff df e0 <unknown>
+
+ld1d    za2v.d[w12, #1], p3/z, [x17, x16, lsl #3]
+// CHECK-INST: ld1d    {za2v.d[w12, #1]}, p3/z, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e d0 e0 <unknown>
+
+ld1d    za0v.d[w12, #1], p1/z, [x1, x30, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w12, #1]}, p1/z, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x84,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 de e0 <unknown>
+
+ld1d    za4v.d[w14, #0], p5/z, [x19, x20, lsl #3]
+// CHECK-INST: ld1d    {za4v.d[w14, #0]}, p5/z, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 d4 e0 <unknown>
+
+ld1d    za0v.d[w12, #0], p6/z, [x12, x2, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w12, #0]}, p6/z, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x99,0xc2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 c2 e0 <unknown>
+
+ld1d    za0v.d[w14, #1], p2/z, [x1, x26, lsl #3]
+// CHECK-INST: ld1d    {za0v.d[w14, #1]}, p2/z, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0xc8,0xda,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 da e0 <unknown>
+
+ld1d    za6v.d[w12, #1], p2/z, [x22, x30, lsl #3]
+// CHECK-INST: ld1d    {za6v.d[w12, #1]}, p2/z, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a de e0 <unknown>
+
+ld1d    za1v.d[w15, #0], p5/z, [x9, x1, lsl #3]
+// CHECK-INST: ld1d    {za1v.d[w15, #0]}, p5/z, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 c1 e0 <unknown>
+
+ld1d    za3v.d[w13, #1], p2/z, [x12, x11, lsl #3]
+// CHECK-INST: ld1d    {za3v.d[w13, #1]}, p2/z, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 cb e0 <unknown>

llvm/test/MC/AArch64/SME/ld1h-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za1)
+
+ld1h {za2h.h[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: ld1h {za2h.h[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+ld1h {za0h.h[w11, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1h {za0h.h[w11, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {za0h.h[w16, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1h {za0h.h[w16, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-7)
+
+ld1h {za0h.h[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: ld1h {za0h.h[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {za0h.h[w12, #8]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: ld1h {za0h.h[w12, #8]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+ld1h {za0h.h[w12, #0]}, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate qualifier (expected: /z)
+
+ld1h {za0h.h[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+ld1h {za0h.h[w12, #0]}, p0/z, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/z, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {za0h.h[w12, #0]}, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK-NEXT: ld1h {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/ld1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+ld1h    {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x00,0x40,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 40 e0 <unknown>
+
+ld1h    {za0h.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0x55,0x55,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 55 e0 <unknown>
+
+ld1h    {za0h.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0x6d,0x48,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 48 e0 <unknown>
+
+ld1h    {za1h.h[w15, #7]}, p7/z, [sp]
+// CHECK-INST: ld1h    {za1h.h[w15, #7]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x5f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 5f e0 <unknown>
+
+ld1h    {za0h.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x0e,0x50,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 50 e0 <unknown>
+
+ld1h    {za0h.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x04,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 5e e0 <unknown>
+
+ld1h    {za1h.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h    {za1h.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0x56,0x54,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 54 e0 <unknown>
+
+ld1h    {za0h.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x19,0x42,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 42 e0 <unknown>
+
+ld1h    {za0h.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0x48,0x5a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 5a e0 <unknown>
+
+ld1h    {za1h.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h    {za1h.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x0a,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 5e e0 <unknown>
+
+ld1h    {za0h.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0x75,0x41,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 41 e0 <unknown>
+
+ld1h    {za0h.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0x29,0x4b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 4b e0 <unknown>
+
+ld1h    za0h.h[w12, #0], p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x00,0x40,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 40 e0 <unknown>
+
+ld1h    za0h.h[w14, #5], p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0x55,0x55,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 55 e0 <unknown>
+
+ld1h    za0h.h[w15, #7], p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0x6d,0x48,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 48 e0 <unknown>
+
+ld1h    za1h.h[w15, #7], p7/z, [sp]
+// CHECK-INST: ld1h    {za1h.h[w15, #7]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x5f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 5f e0 <unknown>
+
+ld1h    za0h.h[w12, #5], p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x0e,0x50,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 50 e0 <unknown>
+
+ld1h    za0h.h[w12, #1], p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x04,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 5e e0 <unknown>
+
+ld1h    za1h.h[w14, #0], p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h    {za1h.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0x56,0x54,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 54 e0 <unknown>
+
+ld1h    za0h.h[w12, #0], p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x19,0x42,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 42 e0 <unknown>
+
+ld1h    za0h.h[w14, #1], p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0x48,0x5a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 5a e0 <unknown>
+
+ld1h    za1h.h[w12, #5], p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h    {za1h.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x0a,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 5e e0 <unknown>
+
+ld1h    za0h.h[w15, #2], p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0x75,0x41,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 41 e0 <unknown>
+
+ld1h    za0h.h[w13, #7], p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h    {za0h.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0x29,0x4b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 4b e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+ld1h    {za0v.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x80,0x40,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 40 e0 <unknown>
+
+ld1h    {za0v.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0xd5,0x55,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 55 e0 <unknown>
+
+ld1h    {za0v.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0xed,0x48,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 48 e0 <unknown>
+
+ld1h    {za1v.h[w15, #7]}, p7/z, [sp]
+// CHECK-INST: ld1h    {za1v.h[w15, #7]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x5f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 5f e0 <unknown>
+
+ld1h    {za0v.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x8e,0x50,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 50 e0 <unknown>
+
+ld1h    {za0v.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x84,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 5e e0 <unknown>
+
+ld1h    {za1v.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h    {za1v.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0xd6,0x54,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 54 e0 <unknown>
+
+ld1h    {za0v.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x99,0x42,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 42 e0 <unknown>
+
+ld1h    {za0v.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0xc8,0x5a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 5a e0 <unknown>
+
+ld1h    {za1v.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h    {za1v.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x8a,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 5e e0 <unknown>
+
+ld1h    {za0v.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0xf5,0x41,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 41 e0 <unknown>
+
+ld1h    {za0v.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0xa9,0x4b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 4b e0 <unknown>
+
+ld1h    za0v.h[w12, #0], p0/z, [x0, x0, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #0]}, p0/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x80,0x40,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 40 e0 <unknown>
+
+ld1h    za0v.h[w14, #5], p5/z, [x10, x21, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w14, #5]}, p5/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0xd5,0x55,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 55 e0 <unknown>
+
+ld1h    za0v.h[w15, #7], p3/z, [x13, x8, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w15, #7]}, p3/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0xed,0x48,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 48 e0 <unknown>
+
+ld1h    za1v.h[w15, #7], p7/z, [sp]
+// CHECK-INST: ld1h    {za1v.h[w15, #7]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x5f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 5f e0 <unknown>
+
+ld1h    za0v.h[w12, #5], p3/z, [x17, x16, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #5]}, p3/z, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x8e,0x50,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 50 e0 <unknown>
+
+ld1h    za0v.h[w12, #1], p1/z, [x1, x30, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #1]}, p1/z, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x84,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 5e e0 <unknown>
+
+ld1h    za1v.h[w14, #0], p5/z, [x19, x20, lsl #1]
+// CHECK-INST: ld1h    {za1v.h[w14, #0]}, p5/z, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0xd6,0x54,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 54 e0 <unknown>
+
+ld1h    za0v.h[w12, #0], p6/z, [x12, x2, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w12, #0]}, p6/z, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x99,0x42,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 42 e0 <unknown>
+
+ld1h    za0v.h[w14, #1], p2/z, [x1, x26, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w14, #1]}, p2/z, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0xc8,0x5a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 5a e0 <unknown>
+
+ld1h    za1v.h[w12, #5], p2/z, [x22, x30, lsl #1]
+// CHECK-INST: ld1h    {za1v.h[w12, #5]}, p2/z, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x8a,0x5e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 5e e0 <unknown>
+
+ld1h    za0v.h[w15, #2], p5/z, [x9, x1, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w15, #2]}, p5/z, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0xf5,0x41,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 41 e0 <unknown>
+
+ld1h    za0v.h[w13, #7], p2/z, [x12, x11, lsl #1]
+// CHECK-INST: ld1h    {za0v.h[w13, #7]}, p2/z, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0xa9,0x4b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 4b e0 <unknown>

llvm/test/MC/AArch64/SME/ld1q-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za15)
+
+ld1q {za16h.q[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: ld1q {za16h.q[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+ld1q {za0h.q[w11]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {za0h.q[w11]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1q {za0h.q[w16]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {za0h.q[w16]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+ld1q {za0h.q[w12]}, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1q {za0h.q[w12]}, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate qualifier (expected: /z)
+
+ld1q {za0h.q[w12]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+ld1q {za0h.q[w12]}, p0/z, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1q {za0h.q[w12]}, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
+// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #5]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
+// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [x0, x0, lsl #5]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/ld1q.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+ld1q    {za0h.q[w12]}, p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q    {za0h.q[w12]}, p0/z, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 c0 e1 <unknown>
+
+ld1q    {za5h.q[w14]}, p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q    {za5h.q[w14]}, p5/z, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0x55,0xd5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 d5 e1 <unknown>
+
+ld1q    {za7h.q[w15]}, p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q    {za7h.q[w15]}, p3/z, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d c8 e1 <unknown>
+
+ld1q    {za15h.q[w15]}, p7/z, [sp]
+// CHECK-INST: ld1q    {za15h.q[w15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f df e1 <unknown>
+
+ld1q    {za5h.q[w12]}, p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q    {za5h.q[w12]}, p3/z, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e d0 e1 <unknown>
+
+ld1q    {za1h.q[w12]}, p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q    {za1h.q[w12]}, p1/z, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x04,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 de e1 <unknown>
+
+ld1q    {za8h.q[w14]}, p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q    {za8h.q[w14]}, p5/z, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0x56,0xd4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 d4 e1 <unknown>
+
+ld1q    {za0h.q[w12]}, p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q    {za0h.q[w12]}, p6/z, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x19,0xc2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 c2 e1 <unknown>
+
+ld1q    {za1h.q[w14]}, p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q    {za1h.q[w14]}, p2/z, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0x48,0xda,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 da e1 <unknown>
+
+ld1q    {za13h.q[w12]}, p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q    {za13h.q[w12]}, p2/z, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a de e1 <unknown>
+
+ld1q    {za2h.q[w15]}, p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q    {za2h.q[w15]}, p5/z, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0x75,0xc1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 c1 e1 <unknown>
+
+ld1q    {za7h.q[w13]}, p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q    {za7h.q[w13]}, p2/z, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0x29,0xcb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 cb e1 <unknown>
+
+ld1q    za0h.q[w12], p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q    {za0h.q[w12]}, p0/z, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 c0 e1 <unknown>
+
+ld1q    za5h.q[w14], p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q    {za5h.q[w14]}, p5/z, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0x55,0xd5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 d5 e1 <unknown>
+
+ld1q    za7h.q[w15], p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q    {za7h.q[w15]}, p3/z, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d c8 e1 <unknown>
+
+ld1q    za15h.q[w15], p7/z, [sp]
+// CHECK-INST: ld1q    {za15h.q[w15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xdf,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f df e1 <unknown>
+
+ld1q    za5h.q[w12], p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q    {za5h.q[w12]}, p3/z, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x0e,0xd0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e d0 e1 <unknown>
+
+ld1q    za1h.q[w12], p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q    {za1h.q[w12]}, p1/z, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x04,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 de e1 <unknown>
+
+ld1q    za8h.q[w14], p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q    {za8h.q[w14]}, p5/z, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0x56,0xd4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 d4 e1 <unknown>
+
+ld1q    za0h.q[w12], p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q    {za0h.q[w12]}, p6/z, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x19,0xc2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 c2 e1 <unknown>
+
+ld1q    za1h.q[w14], p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q    {za1h.q[w14]}, p2/z, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0x48,0xda,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 da e1 <unknown>
+
+ld1q    za13h.q[w12], p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q    {za13h.q[w12]}, p2/z, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x0a,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a de e1 <unknown>
+
+ld1q    za2h.q[w15], p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q    {za2h.q[w15]}, p5/z, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0x75,0xc1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 c1 e1 <unknown>
+
+ld1q    za7h.q[w13], p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q    {za7h.q[w13]}, p2/z, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0x29,0xcb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 cb e1 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+ld1q    {za0v.q[w12]}, p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q    {za0v.q[w12]}, p0/z, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x80,0xc0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 c0 e1 <unknown>
+
+ld1q    {za5v.q[w14]}, p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q    {za5v.q[w14]}, p5/z, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 d5 e1 <unknown>
+
+ld1q    {za7v.q[w15]}, p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q    {za7v.q[w15]}, p3/z, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed c8 e1 <unknown>
+
+ld1q    {za15v.q[w15]}, p7/z, [sp]
+// CHECK-INST: ld1q    {za15v.q[w15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xdf,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff df e1 <unknown>
+
+ld1q    {za5v.q[w12]}, p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q    {za5v.q[w12]}, p3/z, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e d0 e1 <unknown>
+
+ld1q    {za1v.q[w12]}, p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q    {za1v.q[w12]}, p1/z, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x84,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 de e1 <unknown>
+
+ld1q    {za8v.q[w14]}, p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q    {za8v.q[w14]}, p5/z, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 d4 e1 <unknown>
+
+ld1q    {za0v.q[w12]}, p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q    {za0v.q[w12]}, p6/z, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x99,0xc2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 c2 e1 <unknown>
+
+ld1q    {za1v.q[w14]}, p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q    {za1v.q[w14]}, p2/z, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0xc8,0xda,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 da e1 <unknown>
+
+ld1q    {za13v.q[w12]}, p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q    {za13v.q[w12]}, p2/z, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a de e1 <unknown>
+
+ld1q    {za2v.q[w15]}, p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q    {za2v.q[w15]}, p5/z, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 c1 e1 <unknown>
+
+ld1q    {za7v.q[w13]}, p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q    {za7v.q[w13]}, p2/z, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 cb e1 <unknown>
+
+ld1q    za0v.q[w12], p0/z, [x0, x0, lsl #4]
+// CHECK-INST: ld1q    {za0v.q[w12]}, p0/z, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x80,0xc0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 c0 e1 <unknown>
+
+ld1q    za5v.q[w14], p5/z, [x10, x21, lsl #4]
+// CHECK-INST: ld1q    {za5v.q[w14]}, p5/z, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0xd5,0xd5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 d5 e1 <unknown>
+
+ld1q    za7v.q[w15], p3/z, [x13, x8, lsl #4]
+// CHECK-INST: ld1q    {za7v.q[w15]}, p3/z, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0xed,0xc8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed c8 e1 <unknown>
+
+ld1q    za15v.q[w15], p7/z, [sp]
+// CHECK-INST: ld1q    {za15v.q[w15]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xdf,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff df e1 <unknown>
+
+ld1q    za5v.q[w12], p3/z, [x17, x16, lsl #4]
+// CHECK-INST: ld1q    {za5v.q[w12]}, p3/z, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x8e,0xd0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e d0 e1 <unknown>
+
+ld1q    za1v.q[w12], p1/z, [x1, x30, lsl #4]
+// CHECK-INST: ld1q    {za1v.q[w12]}, p1/z, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x84,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 de e1 <unknown>
+
+ld1q    za8v.q[w14], p5/z, [x19, x20, lsl #4]
+// CHECK-INST: ld1q    {za8v.q[w14]}, p5/z, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0xd6,0xd4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 d4 e1 <unknown>
+
+ld1q    za0v.q[w12], p6/z, [x12, x2, lsl #4]
+// CHECK-INST: ld1q    {za0v.q[w12]}, p6/z, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x99,0xc2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 c2 e1 <unknown>
+
+ld1q    za1v.q[w14], p2/z, [x1, x26, lsl #4]
+// CHECK-INST: ld1q    {za1v.q[w14]}, p2/z, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0xc8,0xda,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 da e1 <unknown>
+
+ld1q    za13v.q[w12], p2/z, [x22, x30, lsl #4]
+// CHECK-INST: ld1q    {za13v.q[w12]}, p2/z, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x8a,0xde,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a de e1 <unknown>
+
+ld1q    za2v.q[w15], p5/z, [x9, x1, lsl #4]
+// CHECK-INST: ld1q    {za2v.q[w15]}, p5/z, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0xf5,0xc1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 c1 e1 <unknown>
+
+ld1q    za7v.q[w13], p2/z, [x12, x11, lsl #4]
+// CHECK-INST: ld1q    {za7v.q[w13]}, p2/z, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0xa9,0xcb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 cb e1 <unknown>

llvm/test/MC/AArch64/SME/ld1w-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za3)
+
+ld1w {za4h.s[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: ld1w {za4h.s[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+ld1w {za0h.s[w11, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1w {za0h.s[w11, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {za0h.s[w16, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1w {za0h.s[w16, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-3)
+
+ld1w {za0h.s[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
+// CHECK-NEXT: ld1w {za0h.s[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {za0h.s[w12, #4]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
+// CHECK-NEXT: ld1w {za0h.s[w12, #4]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+ld1w {za0h.s[w12, #0]}, p8/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p8/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate qualifier (expected: /z)
+
+ld1w {za0h.s[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+ld1w {za0h.s[w12, #0]}, p0/z, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/z, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {za0h.s[w12, #0]}, p0/z, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/z, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK-NEXT: ld1w {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/ld1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+ld1w    {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x00,0x80,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 80 e0 <unknown>
+
+ld1w    {za1h.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0x55,0x95,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 95 e0 <unknown>
+
+ld1w    {za1h.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0x6d,0x88,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 88 e0 <unknown>
+
+ld1w    {za3h.s[w15, #3]}, p7/z, [sp]
+// CHECK-INST: ld1w    {za3h.s[w15, #3]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x9f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 9f e0 <unknown>
+
+ld1w    {za1h.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x0e,0x90,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 90 e0 <unknown>
+
+ld1w    {za0h.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x04,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 9e e0 <unknown>
+
+ld1w    {za2h.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w    {za2h.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0x56,0x94,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 94 e0 <unknown>
+
+ld1w    {za0h.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x19,0x82,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 82 e0 <unknown>
+
+ld1w    {za0h.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0x48,0x9a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 9a e0 <unknown>
+
+ld1w    {za3h.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w    {za3h.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x0a,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 9e e0 <unknown>
+
+ld1w    {za0h.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0x75,0x81,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 81 e0 <unknown>
+
+ld1w    {za1h.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0x29,0x8b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 8b e0 <unknown>
+
+ld1w    za0h.s[w12, #0], p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x00,0x80,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 80 e0 <unknown>
+
+ld1w    za1h.s[w14, #1], p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0x55,0x95,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 95 e0 <unknown>
+
+ld1w    za1h.s[w15, #3], p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0x6d,0x88,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 88 e0 <unknown>
+
+ld1w    za3h.s[w15, #3], p7/z, [sp]
+// CHECK-INST: ld1w    {za3h.s[w15, #3]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x9f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 9f e0 <unknown>
+
+ld1w    za1h.s[w12, #1], p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x0e,0x90,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 90 e0 <unknown>
+
+ld1w    za0h.s[w12, #1], p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x04,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 9e e0 <unknown>
+
+ld1w    za2h.s[w14, #0], p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w    {za2h.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0x56,0x94,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 94 e0 <unknown>
+
+ld1w    za0h.s[w12, #0], p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x19,0x82,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 82 e0 <unknown>
+
+ld1w    za0h.s[w14, #1], p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0x48,0x9a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 9a e0 <unknown>
+
+ld1w    za3h.s[w12, #1], p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w    {za3h.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x0a,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 9e e0 <unknown>
+
+ld1w    za0h.s[w15, #2], p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w    {za0h.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0x75,0x81,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 81 e0 <unknown>
+
+ld1w    za1h.s[w13, #3], p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w    {za1h.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0x29,0x8b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 8b e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+ld1w    {za0v.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x80,0x80,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 80 e0 <unknown>
+
+ld1w    {za1v.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0xd5,0x95,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 95 e0 <unknown>
+
+ld1w    {za1v.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0xed,0x88,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 88 e0 <unknown>
+
+ld1w    {za3v.s[w15, #3]}, p7/z, [sp]
+// CHECK-INST: ld1w    {za3v.s[w15, #3]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x9f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 9f e0 <unknown>
+
+ld1w    {za1v.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x8e,0x90,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 90 e0 <unknown>
+
+ld1w    {za0v.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x84,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 9e e0 <unknown>
+
+ld1w    {za2v.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w    {za2v.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0xd6,0x94,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 94 e0 <unknown>
+
+ld1w    {za0v.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x99,0x82,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 82 e0 <unknown>
+
+ld1w    {za0v.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0xc8,0x9a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 9a e0 <unknown>
+
+ld1w    {za3v.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w    {za3v.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x8a,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 9e e0 <unknown>
+
+ld1w    {za0v.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0xf5,0x81,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 81 e0 <unknown>
+
+ld1w    {za1v.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0xa9,0x8b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 8b e0 <unknown>
+
+ld1w    za0v.s[w12, #0], p0/z, [x0, x0, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w12, #0]}, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x80,0x80,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 80 e0 <unknown>
+
+ld1w    za1v.s[w14, #1], p5/z, [x10, x21, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w14, #1]}, p5/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0xd5,0x95,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 95 e0 <unknown>
+
+ld1w    za1v.s[w15, #3], p3/z, [x13, x8, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w15, #3]}, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0xed,0x88,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 88 e0 <unknown>
+
+ld1w    za3v.s[w15, #3], p7/z, [sp]
+// CHECK-INST: ld1w    {za3v.s[w15, #3]}, p7/z, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x9f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 9f e0 <unknown>
+
+ld1w    za1v.s[w12, #1], p3/z, [x17, x16, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w12, #1]}, p3/z, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x8e,0x90,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 90 e0 <unknown>
+
+ld1w    za0v.s[w12, #1], p1/z, [x1, x30, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w12, #1]}, p1/z, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x84,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 9e e0 <unknown>
+
+ld1w    za2v.s[w14, #0], p5/z, [x19, x20, lsl #2]
+// CHECK-INST: ld1w    {za2v.s[w14, #0]}, p5/z, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0xd6,0x94,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 94 e0 <unknown>
+
+ld1w    za0v.s[w12, #0], p6/z, [x12, x2, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w12, #0]}, p6/z, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x99,0x82,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 82 e0 <unknown>
+
+ld1w    za0v.s[w14, #1], p2/z, [x1, x26, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w14, #1]}, p2/z, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0xc8,0x9a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 9a e0 <unknown>
+
+ld1w    za3v.s[w12, #1], p2/z, [x22, x30, lsl #2]
+// CHECK-INST: ld1w    {za3v.s[w12, #1]}, p2/z, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x8a,0x9e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 9e e0 <unknown>
+
+ld1w    za0v.s[w15, #2], p5/z, [x9, x1, lsl #2]
+// CHECK-INST: ld1w    {za0v.s[w15, #2]}, p5/z, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0xf5,0x81,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 81 e0 <unknown>
+
+ld1w    za1v.s[w13, #3], p2/z, [x12, x11, lsl #2]
+// CHECK-INST: ld1w    {za1v.s[w13, #3]}, p2/z, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0xa9,0x8b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 8b e0 <unknown>

llvm/test/MC/AArch64/SME/st1b-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0)
+
+st1b {za1h.b[w12, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: st1b {za1h.b[w12, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+st1b {za0h.b[w11, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1b {za0h.b[w11, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b {za0h.b[w16, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1b {za0h.b[w16, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-15)
+
+st1b {za0h.b[w12]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
+// CHECK-NEXT: st1b {za0h.b[w12]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b {za0h.b[w12, #16]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
+// CHECK-NEXT: st1b {za0h.b[w12, #16]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+st1b {za0h.b[w12, #0]}, p8, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p8, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Unexpected predicate qualifier
+
+st1b {za0h.b[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b {za0h.b[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+st1b {za0h.b[w12, #0]}, p0, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b {za0h.b[w12, #0]}, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
+// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b {za0h.b[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
+// CHECK-NEXT: st1b {za0h.b[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/st1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+st1b    {za0h.b[w12, #0]}, p0, [x0, x0]
+// CHECK-INST: st1b    {za0h.b[w12, #0]}, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x20,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 20 e0 <unknown>
+
+st1b    {za0h.b[w14, #5]}, p5, [x10, x21]
+// CHECK-INST: st1b    {za0h.b[w14, #5]}, p5, [x10, x21]
+// CHECK-ENCODING: [0x45,0x55,0x35,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 35 e0 <unknown>
+
+st1b    {za0h.b[w15, #7]}, p3, [x13, x8]
+// CHECK-INST: st1b    {za0h.b[w15, #7]}, p3, [x13, x8]
+// CHECK-ENCODING: [0xa7,0x6d,0x28,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 28 e0 <unknown>
+
+st1b    {za0h.b[w15, #15]}, p7, [sp]
+// CHECK-INST: st1b    {za0h.b[w15, #15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x3f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 3f e0 <unknown>
+
+st1b    {za0h.b[w12, #5]}, p3, [x17, x16]
+// CHECK-INST: st1b    {za0h.b[w12, #5]}, p3, [x17, x16]
+// CHECK-ENCODING: [0x25,0x0e,0x30,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 30 e0 <unknown>
+
+st1b    {za0h.b[w12, #1]}, p1, [x1, x30]
+// CHECK-INST: st1b    {za0h.b[w12, #1]}, p1, [x1, x30]
+// CHECK-ENCODING: [0x21,0x04,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 3e e0 <unknown>
+
+st1b    {za0h.b[w14, #8]}, p5, [x19, x20]
+// CHECK-INST: st1b    {za0h.b[w14, #8]}, p5, [x19, x20]
+// CHECK-ENCODING: [0x68,0x56,0x34,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 34 e0 <unknown>
+
+st1b    {za0h.b[w12, #0]}, p6, [x12, x2]
+// CHECK-INST: st1b    {za0h.b[w12, #0]}, p6, [x12, x2]
+// CHECK-ENCODING: [0x80,0x19,0x22,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 22 e0 <unknown>
+
+st1b    {za0h.b[w14, #1]}, p2, [x1, x26]
+// CHECK-INST: st1b    {za0h.b[w14, #1]}, p2, [x1, x26]
+// CHECK-ENCODING: [0x21,0x48,0x3a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 3a e0 <unknown>
+
+st1b    {za0h.b[w12, #13]}, p2, [x22, x30]
+// CHECK-INST: st1b    {za0h.b[w12, #13]}, p2, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x0a,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 3e e0 <unknown>
+
+st1b    {za0h.b[w15, #2]}, p5, [x9, x1]
+// CHECK-INST: st1b    {za0h.b[w15, #2]}, p5, [x9, x1]
+// CHECK-ENCODING: [0x22,0x75,0x21,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 21 e0 <unknown>
+
+st1b    {za0h.b[w13, #7]}, p2, [x12, x11]
+// CHECK-INST: st1b    {za0h.b[w13, #7]}, p2, [x12, x11]
+// CHECK-ENCODING: [0x87,0x29,0x2b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 2b e0 <unknown>
+
+st1b    za0h.b[w12, #0], p0, [x0, x0]
+// CHECK-INST: st1b    {za0h.b[w12, #0]}, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x20,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 20 e0 <unknown>
+
+st1b    za0h.b[w14, #5], p5, [x10, x21]
+// CHECK-INST: st1b    {za0h.b[w14, #5]}, p5, [x10, x21]
+// CHECK-ENCODING: [0x45,0x55,0x35,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 35 e0 <unknown>
+
+st1b    za0h.b[w15, #7], p3, [x13, x8]
+// CHECK-INST: st1b    {za0h.b[w15, #7]}, p3, [x13, x8]
+// CHECK-ENCODING: [0xa7,0x6d,0x28,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 28 e0 <unknown>
+
+st1b    za0h.b[w15, #15], p7, [sp]
+// CHECK-INST: st1b    {za0h.b[w15, #15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x3f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 3f e0 <unknown>
+
+st1b    za0h.b[w12, #5], p3, [x17, x16]
+// CHECK-INST: st1b    {za0h.b[w12, #5]}, p3, [x17, x16]
+// CHECK-ENCODING: [0x25,0x0e,0x30,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 30 e0 <unknown>
+
+st1b    za0h.b[w12, #1], p1, [x1, x30]
+// CHECK-INST: st1b    {za0h.b[w12, #1]}, p1, [x1, x30]
+// CHECK-ENCODING: [0x21,0x04,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 3e e0 <unknown>
+
+st1b    za0h.b[w14, #8], p5, [x19, x20]
+// CHECK-INST: st1b    {za0h.b[w14, #8]}, p5, [x19, x20]
+// CHECK-ENCODING: [0x68,0x56,0x34,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 34 e0 <unknown>
+
+st1b    za0h.b[w12, #0], p6, [x12, x2]
+// CHECK-INST: st1b    {za0h.b[w12, #0]}, p6, [x12, x2]
+// CHECK-ENCODING: [0x80,0x19,0x22,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 22 e0 <unknown>
+
+st1b    za0h.b[w14, #1], p2, [x1, x26]
+// CHECK-INST: st1b    {za0h.b[w14, #1]}, p2, [x1, x26]
+// CHECK-ENCODING: [0x21,0x48,0x3a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 3a e0 <unknown>
+
+st1b    za0h.b[w12, #13], p2, [x22, x30]
+// CHECK-INST: st1b    {za0h.b[w12, #13]}, p2, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x0a,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 3e e0 <unknown>
+
+st1b    za0h.b[w15, #2], p5, [x9, x1]
+// CHECK-INST: st1b    {za0h.b[w15, #2]}, p5, [x9, x1]
+// CHECK-ENCODING: [0x22,0x75,0x21,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 21 e0 <unknown>
+
+st1b    za0h.b[w13, #7], p2, [x12, x11]
+// CHECK-INST: st1b    {za0h.b[w13, #7]}, p2, [x12, x11]
+// CHECK-ENCODING: [0x87,0x29,0x2b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 2b e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+st1b    {za0v.b[w12, #0]}, p0, [x0, x0]
+// CHECK-INST: st1b    {za0v.b[w12, #0]}, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 20 e0 <unknown>
+
+st1b    {za0v.b[w14, #5]}, p5, [x10, x21]
+// CHECK-INST: st1b    {za0v.b[w14, #5]}, p5, [x10, x21]
+// CHECK-ENCODING: [0x45,0xd5,0x35,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 35 e0 <unknown>
+
+st1b    {za0v.b[w15, #7]}, p3, [x13, x8]
+// CHECK-INST: st1b    {za0v.b[w15, #7]}, p3, [x13, x8]
+// CHECK-ENCODING: [0xa7,0xed,0x28,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 28 e0 <unknown>
+
+st1b    {za0v.b[w15, #15]}, p7, [sp]
+// CHECK-INST: st1b    {za0v.b[w15, #15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x3f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 3f e0 <unknown>
+
+st1b    {za0v.b[w12, #5]}, p3, [x17, x16]
+// CHECK-INST: st1b    {za0v.b[w12, #5]}, p3, [x17, x16]
+// CHECK-ENCODING: [0x25,0x8e,0x30,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 30 e0 <unknown>
+
+st1b    {za0v.b[w12, #1]}, p1, [x1, x30]
+// CHECK-INST: st1b    {za0v.b[w12, #1]}, p1, [x1, x30]
+// CHECK-ENCODING: [0x21,0x84,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 3e e0 <unknown>
+
+st1b    {za0v.b[w14, #8]}, p5, [x19, x20]
+// CHECK-INST: st1b    {za0v.b[w14, #8]}, p5, [x19, x20]
+// CHECK-ENCODING: [0x68,0xd6,0x34,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 34 e0 <unknown>
+
+st1b    {za0v.b[w12, #0]}, p6, [x12, x2]
+// CHECK-INST: st1b    {za0v.b[w12, #0]}, p6, [x12, x2]
+// CHECK-ENCODING: [0x80,0x99,0x22,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 22 e0 <unknown>
+
+st1b    {za0v.b[w14, #1]}, p2, [x1, x26]
+// CHECK-INST: st1b    {za0v.b[w14, #1]}, p2, [x1, x26]
+// CHECK-ENCODING: [0x21,0xc8,0x3a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 3a e0 <unknown>
+
+st1b    {za0v.b[w12, #13]}, p2, [x22, x30]
+// CHECK-INST: st1b    {za0v.b[w12, #13]}, p2, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x8a,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 3e e0 <unknown>
+
+st1b    {za0v.b[w15, #2]}, p5, [x9, x1]
+// CHECK-INST: st1b    {za0v.b[w15, #2]}, p5, [x9, x1]
+// CHECK-ENCODING: [0x22,0xf5,0x21,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 21 e0 <unknown>
+
+st1b    {za0v.b[w13, #7]}, p2, [x12, x11]
+// CHECK-INST: st1b    {za0v.b[w13, #7]}, p2, [x12, x11]
+// CHECK-ENCODING: [0x87,0xa9,0x2b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 2b e0 <unknown>
+
+st1b    za0v.b[w12, #0], p0, [x0, x0]
+// CHECK-INST: st1b    {za0v.b[w12, #0]}, p0, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 20 e0 <unknown>
+
+st1b    za0v.b[w14, #5], p5, [x10, x21]
+// CHECK-INST: st1b    {za0v.b[w14, #5]}, p5, [x10, x21]
+// CHECK-ENCODING: [0x45,0xd5,0x35,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 35 e0 <unknown>
+
+st1b    za0v.b[w15, #7], p3, [x13, x8]
+// CHECK-INST: st1b    {za0v.b[w15, #7]}, p3, [x13, x8]
+// CHECK-ENCODING: [0xa7,0xed,0x28,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 28 e0 <unknown>
+
+st1b    za0v.b[w15, #15], p7, [sp]
+// CHECK-INST: st1b    {za0v.b[w15, #15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x3f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 3f e0 <unknown>
+
+st1b    za0v.b[w12, #5], p3, [x17, x16]
+// CHECK-INST: st1b    {za0v.b[w12, #5]}, p3, [x17, x16]
+// CHECK-ENCODING: [0x25,0x8e,0x30,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 30 e0 <unknown>
+
+st1b    za0v.b[w12, #1], p1, [x1, x30]
+// CHECK-INST: st1b    {za0v.b[w12, #1]}, p1, [x1, x30]
+// CHECK-ENCODING: [0x21,0x84,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 3e e0 <unknown>
+
+st1b    za0v.b[w14, #8], p5, [x19, x20]
+// CHECK-INST: st1b    {za0v.b[w14, #8]}, p5, [x19, x20]
+// CHECK-ENCODING: [0x68,0xd6,0x34,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 34 e0 <unknown>
+
+st1b    za0v.b[w12, #0], p6, [x12, x2]
+// CHECK-INST: st1b    {za0v.b[w12, #0]}, p6, [x12, x2]
+// CHECK-ENCODING: [0x80,0x99,0x22,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 22 e0 <unknown>
+
+st1b    za0v.b[w14, #1], p2, [x1, x26]
+// CHECK-INST: st1b    {za0v.b[w14, #1]}, p2, [x1, x26]
+// CHECK-ENCODING: [0x21,0xc8,0x3a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 3a e0 <unknown>
+
+st1b    za0v.b[w12, #13], p2, [x22, x30]
+// CHECK-INST: st1b    {za0v.b[w12, #13]}, p2, [x22, x30]
+// CHECK-ENCODING: [0xcd,0x8a,0x3e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 3e e0 <unknown>
+
+st1b    za0v.b[w15, #2], p5, [x9, x1]
+// CHECK-INST: st1b    {za0v.b[w15, #2]}, p5, [x9, x1]
+// CHECK-ENCODING: [0x22,0xf5,0x21,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 21 e0 <unknown>
+
+st1b    za0v.b[w13, #7], p2, [x12, x11]
+// CHECK-INST: st1b    {za0v.b[w13, #7]}, p2, [x12, x11]
+// CHECK-ENCODING: [0x87,0xa9,0x2b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 2b e0 <unknown>

llvm/test/MC/AArch64/SME/st1d-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za7)
+
+st1d {za8h.d[w12, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: st1d {za8h.d[w12, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+st1d {za0h.d[w11, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1d {za0h.d[w11, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {za0h.d[w16, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1d {za0h.d[w16, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-1)
+
+st1d {za0h.d[w12]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: st1d {za0h.d[w12]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {za0h.d[w12, #2]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: st1d {za0h.d[w12, #2]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+st1d {za0h.d[w12, #0]}, p8, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p8, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Unexpected predicate qualifier
+
+st1d {za0h.d[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {za0h.d[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+st1d {za0h.d[w12, #0]}, p0, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {za0h.d[w12, #0]}, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK-NEXT: st1d {za0h.d[w12, #0]}, p0, [x0, x0, lsl #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/st1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+st1d    {za0h.d[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x00,0xe0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 e0 e0 <unknown>
+
+st1d    {za2h.d[w14, #1]}, p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d    {za2h.d[w14, #1]}, p5, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0x55,0xf5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 f5 e0 <unknown>
+
+st1d    {za3h.d[w15, #1]}, p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d    {za3h.d[w15, #1]}, p3, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d e8 e0 <unknown>
+
+st1d    {za7h.d[w15, #1]}, p7, [sp]
+// CHECK-INST: st1d    {za7h.d[w15, #1]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xff,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f ff e0 <unknown>
+
+st1d    {za2h.d[w12, #1]}, p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d    {za2h.d[w12, #1]}, p3, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e f0 e0 <unknown>
+
+st1d    {za0h.d[w12, #1]}, p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w12, #1]}, p1, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x04,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 fe e0 <unknown>
+
+st1d    {za4h.d[w14, #0]}, p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d    {za4h.d[w14, #0]}, p5, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0x56,0xf4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 f4 e0 <unknown>
+
+st1d    {za0h.d[w12, #0]}, p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w12, #0]}, p6, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x19,0xe2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 e2 e0 <unknown>
+
+st1d    {za0h.d[w14, #1]}, p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w14, #1]}, p2, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0x48,0xfa,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 fa e0 <unknown>
+
+st1d    {za6h.d[w12, #1]}, p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d    {za6h.d[w12, #1]}, p2, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a fe e0 <unknown>
+
+st1d    {za1h.d[w15, #0]}, p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d    {za1h.d[w15, #0]}, p5, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0x75,0xe1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 e1 e0 <unknown>
+
+st1d    {za3h.d[w13, #1]}, p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d    {za3h.d[w13, #1]}, p2, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0x29,0xeb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 eb e0 <unknown>
+
+st1d    za0h.d[w12, #0], p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x00,0xe0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 e0 e0 <unknown>
+
+st1d    za2h.d[w14, #1], p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d    {za2h.d[w14, #1]}, p5, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0x55,0xf5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 f5 e0 <unknown>
+
+st1d    za3h.d[w15, #1], p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d    {za3h.d[w15, #1]}, p3, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d e8 e0 <unknown>
+
+st1d    za7h.d[w15, #1], p7, [sp]
+// CHECK-INST: st1d    {za7h.d[w15, #1]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xff,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f ff e0 <unknown>
+
+st1d    za2h.d[w12, #1], p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d    {za2h.d[w12, #1]}, p3, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e f0 e0 <unknown>
+
+st1d    za0h.d[w12, #1], p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w12, #1]}, p1, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x04,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 fe e0 <unknown>
+
+st1d    za4h.d[w14, #0], p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d    {za4h.d[w14, #0]}, p5, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0x56,0xf4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 f4 e0 <unknown>
+
+st1d    za0h.d[w12, #0], p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w12, #0]}, p6, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x19,0xe2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 e2 e0 <unknown>
+
+st1d    za0h.d[w14, #1], p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d    {za0h.d[w14, #1]}, p2, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0x48,0xfa,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 fa e0 <unknown>
+
+st1d    za6h.d[w12, #1], p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d    {za6h.d[w12, #1]}, p2, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a fe e0 <unknown>
+
+st1d    za1h.d[w15, #0], p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d    {za1h.d[w15, #0]}, p5, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0x75,0xe1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 e1 e0 <unknown>
+
+st1d    za3h.d[w13, #1], p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d    {za3h.d[w13, #1]}, p2, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0x29,0xeb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 eb e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+st1d    {za0v.d[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x80,0xe0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 e0 e0 <unknown>
+
+st1d    {za2v.d[w14, #1]}, p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d    {za2v.d[w14, #1]}, p5, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 f5 e0 <unknown>
+
+st1d    {za3v.d[w15, #1]}, p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d    {za3v.d[w15, #1]}, p3, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed e8 e0 <unknown>
+
+st1d    {za7v.d[w15, #1]}, p7, [sp]
+// CHECK-INST: st1d    {za7v.d[w15, #1]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xff,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff ff e0 <unknown>
+
+st1d    {za2v.d[w12, #1]}, p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d    {za2v.d[w12, #1]}, p3, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e f0 e0 <unknown>
+
+st1d    {za0v.d[w12, #1]}, p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w12, #1]}, p1, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x84,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 fe e0 <unknown>
+
+st1d    {za4v.d[w14, #0]}, p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d    {za4v.d[w14, #0]}, p5, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 f4 e0 <unknown>
+
+st1d    {za0v.d[w12, #0]}, p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w12, #0]}, p6, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x99,0xe2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 e2 e0 <unknown>
+
+st1d    {za0v.d[w14, #1]}, p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w14, #1]}, p2, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 fa e0 <unknown>
+
+st1d    {za6v.d[w12, #1]}, p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d    {za6v.d[w12, #1]}, p2, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a fe e0 <unknown>
+
+st1d    {za1v.d[w15, #0]}, p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d    {za1v.d[w15, #0]}, p5, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 e1 e0 <unknown>
+
+st1d    {za3v.d[w13, #1]}, p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d    {za3v.d[w13, #1]}, p2, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 eb e0 <unknown>
+
+st1d    za0v.d[w12, #0], p0, [x0, x0, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x80,0xe0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 e0 e0 <unknown>
+
+st1d    za2v.d[w14, #1], p5, [x10, x21, lsl #3]
+// CHECK-INST: st1d    {za2v.d[w14, #1]}, p5, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 f5 e0 <unknown>
+
+st1d    za3v.d[w15, #1], p3, [x13, x8, lsl #3]
+// CHECK-INST: st1d    {za3v.d[w15, #1]}, p3, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed e8 e0 <unknown>
+
+st1d    za7v.d[w15, #1], p7, [sp]
+// CHECK-INST: st1d    {za7v.d[w15, #1]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xff,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff ff e0 <unknown>
+
+st1d    za2v.d[w12, #1], p3, [x17, x16, lsl #3]
+// CHECK-INST: st1d    {za2v.d[w12, #1]}, p3, [x17, x16, lsl #3]
+// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e f0 e0 <unknown>
+
+st1d    za0v.d[w12, #1], p1, [x1, x30, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w12, #1]}, p1, [x1, x30, lsl #3]
+// CHECK-ENCODING: [0x21,0x84,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 fe e0 <unknown>
+
+st1d    za4v.d[w14, #0], p5, [x19, x20, lsl #3]
+// CHECK-INST: st1d    {za4v.d[w14, #0]}, p5, [x19, x20, lsl #3]
+// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 f4 e0 <unknown>
+
+st1d    za0v.d[w12, #0], p6, [x12, x2, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w12, #0]}, p6, [x12, x2, lsl #3]
+// CHECK-ENCODING: [0x80,0x99,0xe2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 e2 e0 <unknown>
+
+st1d    za0v.d[w14, #1], p2, [x1, x26, lsl #3]
+// CHECK-INST: st1d    {za0v.d[w14, #1]}, p2, [x1, x26, lsl #3]
+// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 fa e0 <unknown>
+
+st1d    za6v.d[w12, #1], p2, [x22, x30, lsl #3]
+// CHECK-INST: st1d    {za6v.d[w12, #1]}, p2, [x22, x30, lsl #3]
+// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a fe e0 <unknown>
+
+st1d    za1v.d[w15, #0], p5, [x9, x1, lsl #3]
+// CHECK-INST: st1d    {za1v.d[w15, #0]}, p5, [x9, x1, lsl #3]
+// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 e1 e0 <unknown>
+
+st1d    za3v.d[w13, #1], p2, [x12, x11, lsl #3]
+// CHECK-INST: st1d    {za3v.d[w13, #1]}, p2, [x12, x11, lsl #3]
+// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 eb e0 <unknown>

llvm/test/MC/AArch64/SME/st1h-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za1)
+
+st1h {za2h.h[w12, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: st1h {za2h.h[w12, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+st1h {za0h.h[w11, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1h {za0h.h[w11, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h {za0h.h[w16, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1h {za0h.h[w16, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-7)
+
+st1h {za0h.h[w12]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: st1h {za0h.h[w12]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h {za0h.h[w12, #8]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: st1h {za0h.h[w12, #8]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+st1h {za0h.h[w12, #0]}, p8, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p8, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Unexpected predicate qualifier
+
+st1h {za0h.h[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h {za0h.h[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+st1h {za0h.h[w12, #0]}, p0, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h {za0h.h[w12, #0]}, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK-NEXT: st1h {za0h.h[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/st1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+st1h    {za0h.h[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x00,0x60,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 60 e0 <unknown>
+
+st1h    {za0h.h[w14, #5]}, p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w14, #5]}, p5, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0x55,0x75,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 75 e0 <unknown>
+
+st1h    {za0h.h[w15, #7]}, p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w15, #7]}, p3, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0x6d,0x68,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 68 e0 <unknown>
+
+st1h    {za1h.h[w15, #7]}, p7, [sp]
+// CHECK-INST: st1h    {za1h.h[w15, #7]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x7f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 7f e0 <unknown>
+
+st1h    {za0h.h[w12, #5]}, p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #5]}, p3, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x0e,0x70,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 70 e0 <unknown>
+
+st1h    {za0h.h[w12, #1]}, p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #1]}, p1, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x04,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 7e e0 <unknown>
+
+st1h    {za1h.h[w14, #0]}, p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h    {za1h.h[w14, #0]}, p5, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0x56,0x74,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 74 e0 <unknown>
+
+st1h    {za0h.h[w12, #0]}, p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #0]}, p6, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x19,0x62,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 62 e0 <unknown>
+
+st1h    {za0h.h[w14, #1]}, p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w14, #1]}, p2, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0x48,0x7a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 7a e0 <unknown>
+
+st1h    {za1h.h[w12, #5]}, p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h    {za1h.h[w12, #5]}, p2, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x0a,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 7e e0 <unknown>
+
+st1h    {za0h.h[w15, #2]}, p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w15, #2]}, p5, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0x75,0x61,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 61 e0 <unknown>
+
+st1h    {za0h.h[w13, #7]}, p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w13, #7]}, p2, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0x29,0x6b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 6b e0 <unknown>
+
+st1h    za0h.h[w12, #0], p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x00,0x60,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 60 e0 <unknown>
+
+st1h    za0h.h[w14, #5], p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w14, #5]}, p5, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0x55,0x75,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 75 e0 <unknown>
+
+st1h    za0h.h[w15, #7], p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w15, #7]}, p3, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0x6d,0x68,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d 68 e0 <unknown>
+
+st1h    za1h.h[w15, #7], p7, [sp]
+// CHECK-INST: st1h    {za1h.h[w15, #7]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0x7f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f 7f e0 <unknown>
+
+st1h    za0h.h[w12, #5], p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #5]}, p3, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x0e,0x70,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e 70 e0 <unknown>
+
+st1h    za0h.h[w12, #1], p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #1]}, p1, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x04,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 7e e0 <unknown>
+
+st1h    za1h.h[w14, #0], p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h    {za1h.h[w14, #0]}, p5, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0x56,0x74,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 74 e0 <unknown>
+
+st1h    za0h.h[w12, #0], p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w12, #0]}, p6, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x19,0x62,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 62 e0 <unknown>
+
+st1h    za0h.h[w14, #1], p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w14, #1]}, p2, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0x48,0x7a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 7a e0 <unknown>
+
+st1h    za1h.h[w12, #5], p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h    {za1h.h[w12, #5]}, p2, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x0a,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a 7e e0 <unknown>
+
+st1h    za0h.h[w15, #2], p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w15, #2]}, p5, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0x75,0x61,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 61 e0 <unknown>
+
+st1h    za0h.h[w13, #7], p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h    {za0h.h[w13, #7]}, p2, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0x29,0x6b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 6b e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+st1h    {za0v.h[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x80,0x60,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 60 e0 <unknown>
+
+st1h    {za0v.h[w14, #5]}, p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w14, #5]}, p5, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0xd5,0x75,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 75 e0 <unknown>
+
+st1h    {za0v.h[w15, #7]}, p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w15, #7]}, p3, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0xed,0x68,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 68 e0 <unknown>
+
+st1h    {za1v.h[w15, #7]}, p7, [sp]
+// CHECK-INST: st1h    {za1v.h[w15, #7]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x7f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 7f e0 <unknown>
+
+st1h    {za0v.h[w12, #5]}, p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #5]}, p3, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x8e,0x70,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 70 e0 <unknown>
+
+st1h    {za0v.h[w12, #1]}, p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #1]}, p1, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x84,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 7e e0 <unknown>
+
+st1h    {za1v.h[w14, #0]}, p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h    {za1v.h[w14, #0]}, p5, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0xd6,0x74,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 74 e0 <unknown>
+
+st1h    {za0v.h[w12, #0]}, p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #0]}, p6, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x99,0x62,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 62 e0 <unknown>
+
+st1h    {za0v.h[w14, #1]}, p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w14, #1]}, p2, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0xc8,0x7a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 7a e0 <unknown>
+
+st1h    {za1v.h[w12, #5]}, p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h    {za1v.h[w12, #5]}, p2, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x8a,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 7e e0 <unknown>
+
+st1h    {za0v.h[w15, #2]}, p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w15, #2]}, p5, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0xf5,0x61,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 61 e0 <unknown>
+
+st1h    {za0v.h[w13, #7]}, p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w13, #7]}, p2, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0xa9,0x6b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 6b e0 <unknown>
+
+st1h    za0v.h[w12, #0], p0, [x0, x0, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #0]}, p0, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x80,0x60,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 60 e0 <unknown>
+
+st1h    za0v.h[w14, #5], p5, [x10, x21, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w14, #5]}, p5, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x45,0xd5,0x75,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 75 e0 <unknown>
+
+st1h    za0v.h[w15, #7], p3, [x13, x8, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w15, #7]}, p3, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xa7,0xed,0x68,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed 68 e0 <unknown>
+
+st1h    za1v.h[w15, #7], p7, [sp]
+// CHECK-INST: st1h    {za1v.h[w15, #7]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0x7f,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff 7f e0 <unknown>
+
+st1h    za0v.h[w12, #5], p3, [x17, x16, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #5]}, p3, [x17, x16, lsl #1]
+// CHECK-ENCODING: [0x25,0x8e,0x70,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e 70 e0 <unknown>
+
+st1h    za0v.h[w12, #1], p1, [x1, x30, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #1]}, p1, [x1, x30, lsl #1]
+// CHECK-ENCODING: [0x21,0x84,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 7e e0 <unknown>
+
+st1h    za1v.h[w14, #0], p5, [x19, x20, lsl #1]
+// CHECK-INST: st1h    {za1v.h[w14, #0]}, p5, [x19, x20, lsl #1]
+// CHECK-ENCODING: [0x68,0xd6,0x74,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 74 e0 <unknown>
+
+st1h    za0v.h[w12, #0], p6, [x12, x2, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w12, #0]}, p6, [x12, x2, lsl #1]
+// CHECK-ENCODING: [0x80,0x99,0x62,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 62 e0 <unknown>
+
+st1h    za0v.h[w14, #1], p2, [x1, x26, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w14, #1]}, p2, [x1, x26, lsl #1]
+// CHECK-ENCODING: [0x21,0xc8,0x7a,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 7a e0 <unknown>
+
+st1h    za1v.h[w12, #5], p2, [x22, x30, lsl #1]
+// CHECK-INST: st1h    {za1v.h[w12, #5]}, p2, [x22, x30, lsl #1]
+// CHECK-ENCODING: [0xcd,0x8a,0x7e,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a 7e e0 <unknown>
+
+st1h    za0v.h[w15, #2], p5, [x9, x1, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w15, #2]}, p5, [x9, x1, lsl #1]
+// CHECK-ENCODING: [0x22,0xf5,0x61,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 61 e0 <unknown>
+
+st1h    za0v.h[w13, #7], p2, [x12, x11, lsl #1]
+// CHECK-INST: st1h    {za0v.h[w13, #7]}, p2, [x12, x11, lsl #1]
+// CHECK-ENCODING: [0x87,0xa9,0x6b,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 6b e0 <unknown>

llvm/test/MC/AArch64/SME/st1q-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za15)
+
+st1q {za16h.q[w12]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: st1q {za16h.q[w12]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+st1q {za0h.q[w11]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {za0h.q[w11]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {za0h.q[w16]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {za0h.q[w16]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+st1q {za0h.q[w12]}, p8, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1q {za0h.q[w12]}, p8, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Unexpected predicate qualifier
+
+st1q {za0h.q[w12]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {za0h.q[w12]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {za0h.q[w12]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {za0h.q[w12]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+st1q {za0h.q[w12]}, p0, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {za0h.q[w12]}, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
+// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {za0h.q[w12]}, p0, [x0, x0, lsl #5]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #4'
+// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [x0, x0, lsl #5]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/st1q.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+st1q    {za0h.q[w12]}, p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q    {za0h.q[w12]}, p0, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x00,0xe0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 e0 e1 <unknown>
+
+st1q    {za5h.q[w14]}, p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q    {za5h.q[w14]}, p5, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0x55,0xf5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 f5 e1 <unknown>
+
+st1q    {za7h.q[w15]}, p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q    {za7h.q[w15]}, p3, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d e8 e1 <unknown>
+
+st1q    {za15h.q[w15]}, p7, [sp]
+// CHECK-INST: st1q    {za15h.q[w15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xff,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f ff e1 <unknown>
+
+st1q    {za5h.q[w12]}, p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q    {za5h.q[w12]}, p3, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e f0 e1 <unknown>
+
+st1q    {za1h.q[w12]}, p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q    {za1h.q[w12]}, p1, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x04,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 fe e1 <unknown>
+
+st1q    {za8h.q[w14]}, p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q    {za8h.q[w14]}, p5, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0x56,0xf4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 f4 e1 <unknown>
+
+st1q    {za0h.q[w12]}, p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q    {za0h.q[w12]}, p6, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x19,0xe2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 e2 e1 <unknown>
+
+st1q    {za1h.q[w14]}, p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q    {za1h.q[w14]}, p2, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0x48,0xfa,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 fa e1 <unknown>
+
+st1q    {za13h.q[w12]}, p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q    {za13h.q[w12]}, p2, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a fe e1 <unknown>
+
+st1q    {za2h.q[w15]}, p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q    {za2h.q[w15]}, p5, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0x75,0xe1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 e1 e1 <unknown>
+
+st1q    {za7h.q[w13]}, p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q    {za7h.q[w13]}, p2, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0x29,0xeb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 eb e1 <unknown>
+
+st1q    za0h.q[w12], p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q    {za0h.q[w12]}, p0, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x00,0xe0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 e0 e1 <unknown>
+
+st1q    za5h.q[w14], p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q    {za5h.q[w14]}, p5, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0x55,0xf5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 f5 e1 <unknown>
+
+st1q    za7h.q[w15], p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q    {za7h.q[w15]}, p3, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d e8 e1 <unknown>
+
+st1q    za15h.q[w15], p7, [sp]
+// CHECK-INST: st1q    {za15h.q[w15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xff,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f ff e1 <unknown>
+
+st1q    za5h.q[w12], p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q    {za5h.q[w12]}, p3, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x0e,0xf0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e f0 e1 <unknown>
+
+st1q    za1h.q[w12], p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q    {za1h.q[w12]}, p1, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x04,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 fe e1 <unknown>
+
+st1q    za8h.q[w14], p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q    {za8h.q[w14]}, p5, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0x56,0xf4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 f4 e1 <unknown>
+
+st1q    za0h.q[w12], p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q    {za0h.q[w12]}, p6, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x19,0xe2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 e2 e1 <unknown>
+
+st1q    za1h.q[w14], p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q    {za1h.q[w14]}, p2, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0x48,0xfa,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 fa e1 <unknown>
+
+st1q    za13h.q[w12], p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q    {za13h.q[w12]}, p2, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a fe e1 <unknown>
+
+st1q    za2h.q[w15], p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q    {za2h.q[w15]}, p5, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0x75,0xe1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 e1 e1 <unknown>
+
+st1q    za7h.q[w13], p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q    {za7h.q[w13]}, p2, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0x29,0xeb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 eb e1 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+st1q    {za0v.q[w12]}, p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q    {za0v.q[w12]}, p0, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x80,0xe0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 e0 e1 <unknown>
+
+st1q    {za5v.q[w14]}, p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q    {za5v.q[w14]}, p5, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 f5 e1 <unknown>
+
+st1q    {za7v.q[w15]}, p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q    {za7v.q[w15]}, p3, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed e8 e1 <unknown>
+
+st1q    {za15v.q[w15]}, p7, [sp]
+// CHECK-INST: st1q    {za15v.q[w15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xff,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff ff e1 <unknown>
+
+st1q    {za5v.q[w12]}, p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q    {za5v.q[w12]}, p3, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e f0 e1 <unknown>
+
+st1q    {za1v.q[w12]}, p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q    {za1v.q[w12]}, p1, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x84,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 fe e1 <unknown>
+
+st1q    {za8v.q[w14]}, p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q    {za8v.q[w14]}, p5, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 f4 e1 <unknown>
+
+st1q    {za0v.q[w12]}, p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q    {za0v.q[w12]}, p6, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x99,0xe2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 e2 e1 <unknown>
+
+st1q    {za1v.q[w14]}, p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q    {za1v.q[w14]}, p2, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 fa e1 <unknown>
+
+st1q    {za13v.q[w12]}, p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q    {za13v.q[w12]}, p2, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a fe e1 <unknown>
+
+st1q    {za2v.q[w15]}, p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q    {za2v.q[w15]}, p5, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 e1 e1 <unknown>
+
+st1q    {za7v.q[w13]}, p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q    {za7v.q[w13]}, p2, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 eb e1 <unknown>
+
+st1q    za0v.q[w12], p0, [x0, x0, lsl #4]
+// CHECK-INST: st1q    {za0v.q[w12]}, p0, [x0, x0, lsl #4]
+// CHECK-ENCODING: [0x00,0x80,0xe0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 e0 e1 <unknown>
+
+st1q    za5v.q[w14], p5, [x10, x21, lsl #4]
+// CHECK-INST: st1q    {za5v.q[w14]}, p5, [x10, x21, lsl #4]
+// CHECK-ENCODING: [0x45,0xd5,0xf5,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 f5 e1 <unknown>
+
+st1q    za7v.q[w15], p3, [x13, x8, lsl #4]
+// CHECK-INST: st1q    {za7v.q[w15]}, p3, [x13, x8, lsl #4]
+// CHECK-ENCODING: [0xa7,0xed,0xe8,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed e8 e1 <unknown>
+
+st1q    za15v.q[w15], p7, [sp]
+// CHECK-INST: st1q    {za15v.q[w15]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xff,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff ff e1 <unknown>
+
+st1q    za5v.q[w12], p3, [x17, x16, lsl #4]
+// CHECK-INST: st1q    {za5v.q[w12]}, p3, [x17, x16, lsl #4]
+// CHECK-ENCODING: [0x25,0x8e,0xf0,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e f0 e1 <unknown>
+
+st1q    za1v.q[w12], p1, [x1, x30, lsl #4]
+// CHECK-INST: st1q    {za1v.q[w12]}, p1, [x1, x30, lsl #4]
+// CHECK-ENCODING: [0x21,0x84,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 fe e1 <unknown>
+
+st1q    za8v.q[w14], p5, [x19, x20, lsl #4]
+// CHECK-INST: st1q    {za8v.q[w14]}, p5, [x19, x20, lsl #4]
+// CHECK-ENCODING: [0x68,0xd6,0xf4,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 f4 e1 <unknown>
+
+st1q    za0v.q[w12], p6, [x12, x2, lsl #4]
+// CHECK-INST: st1q    {za0v.q[w12]}, p6, [x12, x2, lsl #4]
+// CHECK-ENCODING: [0x80,0x99,0xe2,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 e2 e1 <unknown>
+
+st1q    za1v.q[w14], p2, [x1, x26, lsl #4]
+// CHECK-INST: st1q    {za1v.q[w14]}, p2, [x1, x26, lsl #4]
+// CHECK-ENCODING: [0x21,0xc8,0xfa,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 fa e1 <unknown>
+
+st1q    za13v.q[w12], p2, [x22, x30, lsl #4]
+// CHECK-INST: st1q    {za13v.q[w12]}, p2, [x22, x30, lsl #4]
+// CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a fe e1 <unknown>
+
+st1q    za2v.q[w15], p5, [x9, x1, lsl #4]
+// CHECK-INST: st1q    {za2v.q[w15]}, p5, [x9, x1, lsl #4]
+// CHECK-ENCODING: [0x22,0xf5,0xe1,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 e1 e1 <unknown>
+
+st1q    za7v.q[w13], p2, [x12, x11, lsl #4]
+// CHECK-INST: st1q    {za7v.q[w13]}, p2, [x12, x11, lsl #4]
+// CHECK-ENCODING: [0x87,0xa9,0xeb,0xe1]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 eb e1 <unknown>

llvm/test/MC/AArch64/SME/st1w-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid tile (expected: za0-za3)
+
+st1w {za4h.s[w12, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
+// CHECK-NEXT: st1w {za4h.s[w12, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select register (expected: w12-w15)
+
+st1w {za0h.s[w11, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1w {za0h.s[w11, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {za0h.s[w16, #0]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1w {za0h.s[w16, #0]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid vector select offset (expected: 0-3)
+
+st1w {za0h.s[w12]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
+// CHECK-NEXT: st1w {za0h.s[w12]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {za0h.s[w12, #4]}, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
+// CHECK-NEXT: st1w {za0h.s[w12, #4]}, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate (expected: p0-p7)
+
+st1w {za0h.s[w12, #0]}, p8, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p8, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Unexpected predicate qualifier
+
+st1w {za0h.s[w12, #0]}, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {za0h.s[w12, #0]}, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid memory operands
+
+st1w {za0h.s[w12, #0]}, p0, [w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0, [w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {za0h.s[w12, #0]}, p0, [x0, w0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0, [x0, w0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK-NEXT: st1w {za0h.s[w12, #0]}, p0, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/st1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// --------------------------------------------------------------------------//
+// Horizontal
+
+st1w    {za0h.s[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x00,0xa0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 a0 e0 <unknown>
+
+st1w    {za1h.s[w14, #1]}, p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w14, #1]}, p5, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0x55,0xb5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 b5 e0 <unknown>
+
+st1w    {za1h.s[w15, #3]}, p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w15, #3]}, p3, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0x6d,0xa8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d a8 e0 <unknown>
+
+st1w    {za3h.s[w15, #3]}, p7, [sp]
+// CHECK-INST: st1w    {za3h.s[w15, #3]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xbf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f bf e0 <unknown>
+
+st1w    {za1h.s[w12, #1]}, p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w12, #1]}, p3, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x0e,0xb0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e b0 e0 <unknown>
+
+st1w    {za0h.s[w12, #1]}, p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w12, #1]}, p1, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x04,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 be e0 <unknown>
+
+st1w    {za2h.s[w14, #0]}, p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w    {za2h.s[w14, #0]}, p5, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0x56,0xb4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 b4 e0 <unknown>
+
+st1w    {za0h.s[w12, #0]}, p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w12, #0]}, p6, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x19,0xa2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 a2 e0 <unknown>
+
+st1w    {za0h.s[w14, #1]}, p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w14, #1]}, p2, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0x48,0xba,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 ba e0 <unknown>
+
+st1w    {za3h.s[w12, #1]}, p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w    {za3h.s[w12, #1]}, p2, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x0a,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a be e0 <unknown>
+
+st1w    {za0h.s[w15, #2]}, p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w15, #2]}, p5, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0x75,0xa1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 a1 e0 <unknown>
+
+st1w    {za1h.s[w13, #3]}, p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w13, #3]}, p2, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0x29,0xab,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 ab e0 <unknown>
+
+st1w    za0h.s[w12, #0], p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x00,0xa0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 00 a0 e0 <unknown>
+
+st1w    za1h.s[w14, #1], p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w14, #1]}, p5, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0x55,0xb5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 55 b5 e0 <unknown>
+
+st1w    za1h.s[w15, #3], p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w15, #3]}, p3, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0x6d,0xa8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 6d a8 e0 <unknown>
+
+st1w    za3h.s[w15, #3], p7, [sp]
+// CHECK-INST: st1w    {za3h.s[w15, #3]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0x7f,0xbf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef 7f bf e0 <unknown>
+
+st1w    za1h.s[w12, #1], p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w12, #1]}, p3, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x0e,0xb0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 0e b0 e0 <unknown>
+
+st1w    za0h.s[w12, #1], p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w12, #1]}, p1, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x04,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 04 be e0 <unknown>
+
+st1w    za2h.s[w14, #0], p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w    {za2h.s[w14, #0]}, p5, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0x56,0xb4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 56 b4 e0 <unknown>
+
+st1w    za0h.s[w12, #0], p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w12, #0]}, p6, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x19,0xa2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 19 a2 e0 <unknown>
+
+st1w    za0h.s[w14, #1], p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w14, #1]}, p2, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0x48,0xba,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 48 ba e0 <unknown>
+
+st1w    za3h.s[w12, #1], p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w    {za3h.s[w12, #1]}, p2, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x0a,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 0a be e0 <unknown>
+
+st1w    za0h.s[w15, #2], p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w    {za0h.s[w15, #2]}, p5, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0x75,0xa1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 75 a1 e0 <unknown>
+
+st1w    za1h.s[w13, #3], p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w    {za1h.s[w13, #3]}, p2, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0x29,0xab,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 29 ab e0 <unknown>
+
+// --------------------------------------------------------------------------//
+// Vertical
+
+st1w    {za0v.s[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x80,0xa0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 a0 e0 <unknown>
+
+st1w    {za1v.s[w14, #1]}, p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w14, #1]}, p5, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0xd5,0xb5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 b5 e0 <unknown>
+
+st1w    {za1v.s[w15, #3]}, p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w15, #3]}, p3, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0xed,0xa8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed a8 e0 <unknown>
+
+st1w    {za3v.s[w15, #3]}, p7, [sp]
+// CHECK-INST: st1w    {za3v.s[w15, #3]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xbf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff bf e0 <unknown>
+
+st1w    {za1v.s[w12, #1]}, p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w12, #1]}, p3, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x8e,0xb0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e b0 e0 <unknown>
+
+st1w    {za0v.s[w12, #1]}, p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w12, #1]}, p1, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x84,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 be e0 <unknown>
+
+st1w    {za2v.s[w14, #0]}, p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w    {za2v.s[w14, #0]}, p5, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0xd6,0xb4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 b4 e0 <unknown>
+
+st1w    {za0v.s[w12, #0]}, p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w12, #0]}, p6, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x99,0xa2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 a2 e0 <unknown>
+
+st1w    {za0v.s[w14, #1]}, p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w14, #1]}, p2, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0xc8,0xba,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 ba e0 <unknown>
+
+st1w    {za3v.s[w12, #1]}, p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w    {za3v.s[w12, #1]}, p2, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x8a,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a be e0 <unknown>
+
+st1w    {za0v.s[w15, #2]}, p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w15, #2]}, p5, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0xf5,0xa1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 a1 e0 <unknown>
+
+st1w    {za1v.s[w13, #3]}, p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w13, #3]}, p2, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0xa9,0xab,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 ab e0 <unknown>
+
+st1w    za0v.s[w12, #0], p0, [x0, x0, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w12, #0]}, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x80,0xa0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 80 a0 e0 <unknown>
+
+st1w    za1v.s[w14, #1], p5, [x10, x21, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w14, #1]}, p5, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x45,0xd5,0xb5,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 45 d5 b5 e0 <unknown>
+
+st1w    za1v.s[w15, #3], p3, [x13, x8, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w15, #3]}, p3, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xa7,0xed,0xa8,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: a7 ed a8 e0 <unknown>
+
+st1w    za3v.s[w15, #3], p7, [sp]
+// CHECK-INST: st1w    {za3v.s[w15, #3]}, p7, [sp]
+// CHECK-ENCODING: [0xef,0xff,0xbf,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ef ff bf e0 <unknown>
+
+st1w    za1v.s[w12, #1], p3, [x17, x16, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w12, #1]}, p3, [x17, x16, lsl #2]
+// CHECK-ENCODING: [0x25,0x8e,0xb0,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25 8e b0 e0 <unknown>
+
+st1w    za0v.s[w12, #1], p1, [x1, x30, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w12, #1]}, p1, [x1, x30, lsl #2]
+// CHECK-ENCODING: [0x21,0x84,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 84 be e0 <unknown>
+
+st1w    za2v.s[w14, #0], p5, [x19, x20, lsl #2]
+// CHECK-INST: st1w    {za2v.s[w14, #0]}, p5, [x19, x20, lsl #2]
+// CHECK-ENCODING: [0x68,0xd6,0xb4,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 68 d6 b4 e0 <unknown>
+
+st1w    za0v.s[w12, #0], p6, [x12, x2, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w12, #0]}, p6, [x12, x2, lsl #2]
+// CHECK-ENCODING: [0x80,0x99,0xa2,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 80 99 a2 e0 <unknown>
+
+st1w    za0v.s[w14, #1], p2, [x1, x26, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w14, #1]}, p2, [x1, x26, lsl #2]
+// CHECK-ENCODING: [0x21,0xc8,0xba,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 21 c8 ba e0 <unknown>
+
+st1w    za3v.s[w12, #1], p2, [x22, x30, lsl #2]
+// CHECK-INST: st1w    {za3v.s[w12, #1]}, p2, [x22, x30, lsl #2]
+// CHECK-ENCODING: [0xcd,0x8a,0xbe,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: cd 8a be e0 <unknown>
+
+st1w    za0v.s[w15, #2], p5, [x9, x1, lsl #2]
+// CHECK-INST: st1w    {za0v.s[w15, #2]}, p5, [x9, x1, lsl #2]
+// CHECK-ENCODING: [0x22,0xf5,0xa1,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 22 f5 a1 e0 <unknown>
+
+st1w    za1v.s[w13, #3], p2, [x12, x11, lsl #2]
+// CHECK-INST: st1w    {za1v.s[w13, #3]}, p2, [x12, x11, lsl #2]
+// CHECK-ENCODING: [0x87,0xa9,0xab,0xe0]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 87 a9 ab e0 <unknown>

llvm/test/MC/AArch64/neon-diagnostics.s

// CHECK-ERROR:                       ^
          ld1 {v15.8h-v17.4h}, [x15]
          ld1 {v0.8b-v2.8b, [x0]
 // CHECK-ERROR: error: registers must be sequential
 // CHECK-ERROR:        ld1 {v0.16b, v2.16b}, [x0]
 // CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
 // CHECK-ERROR:                                         ^
-// CHECK-ERROR: error: unexpected token in argument list
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ld1 v0.8b, v1.8b}, [x0]
 // CHECK-ERROR:            ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        ld1 {v0.8h-v4.8h}, [x0]
 // CHECK-ERROR:                   ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        ld1 {v1.8h-v1.8h}, [x0]
 // CHECK-ERROR:                   ^
// CHECK-ERROR:                       ^
          st1 {v15.8h-v17.4h}, [x15]
          st1 {v0.8b-v2.8b, [x0]
 // CHECK-ERROR: error: registers must be sequential
 // CHECK-ERROR:        st1 {v0.16b, v2.16b}, [x0]
 // CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
 // CHECK-ERROR:                                         ^
-// CHECK-ERROR: error: unexpected token in argument list
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st1 v0.8b, v1.8b}, [x0]
 // CHECK-ERROR:            ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        st1 {v0.8h-v4.8h}, [x0]
 // CHECK-ERROR:                   ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        st1 {v1.8h-v1.8h}, [x0]
 // CHECK-ERROR:                   ^