[AArch64] Use TargetRegisterClass::hasSubClassEq in tryToFindRegisterToRename

[c-rhodes]

Summary

When renaming store operands for pairing in the load/store optimizer it
tries to find an available register from the minimal physical register
class of the original register. For each register it compares the
equality of minimal physical register class of all sub/super registers
with the minimal physical register class of the original register.

Simply checking for register class equality can break once additional
register classes are added, as was the case when adding:

def foo : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>

which broke:

CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
CodeGen/AArch64/stp-opt-with-renaming.mir

Since the introduction of the register class above, the rename register
in test1 of the reserved regs test changed from x12 to x18. The reason
for this is the minimal physical register class of x12 (as well as
x13-x15) and its sub/super registers no longer matches that of x9
(GPR64noip_and_tcGPR64).

Rather than selecting a matching register based on a comparison of the minimal
physical register classes of the original and rename registers, this patch
selects based on MachineInstr::getRegClassConstraint for the original
register.

It's worth mentioning the parameter passing registers (r0-r7) could be now be
used as rename registers since the GPR32arg and GPR64arg register classes are
subclasses of the minimal physical register class for x8 for example. I'm not
entirely sure if we want to exclude those registers, if so maybe we could
explicitly exclude those register classes.

[efriedma]

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

885

I don't think this does what you want. Suppose we had a separate register class for every single AArch64 register. Then this would fail unless OriginalReg and SubOrSuper are equal, I think.

Maybe instead of TRI->getMinimalPhysRegClass(OriginalReg), we can use MachineInstr::getRegClassConstraint?

1553

C->hasSubClassEq(TRI->getMinimalPhysRegClass(SubOrSuper)); seems like a really awkward way to write C->contains(SubOrSuper)

[c-rhodes]

Address Eli's comments

[c-rhodes]

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

885

Maybe instead of TRI->getMinimalPhysRegClass(OriginalReg), we can use MachineInstr::getRegClassConstraint?

Took me a while to figure out how to use it but I've updated it. An issue I found was for some machine instrs the number of operands was different to the MCInstrDesc so it couldn't find a regclass when OpIdx >= MCID.getNumOperands(). This caused a difference in test8 of llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir since the implicit-def at the end of the ORR no longer uses the rename register.

[efriedma]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

260

This seems wrong: we shouldn't skip renaming implicit defs. Probably we should bail out of the transform if we see an implicit def we can't understand.

The test input is a little weird, though; I'm not sure it's legal to mark the result of the ORRWrs renamable given the relationship between the result and the implicit def.

[c-rhodes]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

260

This seems wrong: we shouldn't skip renaming implicit defs. Probably we should bail out of the transform if we see an implicit def we can't understand.

The test input is a little weird, though; I'm not sure it's legal to mark the result of the ORRWrs renamable given the relationship between the result and the implicit def.

I'm not very familiar with this so I'm not sure what the right thing to do is to be honest. The optimization could handle these implicit-defs before using MachineInstr::getRegClassConstraint, so I guess it's a question of whether the input was right in the first place or if it can be extended to not bail out for these operands.

I grepped on ORRWrs and found a few uses similar to this, although that doesn't necessarily means it valid I suppose.

[efriedma]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

260

Thinking about it a bit more, I guess you could argue the renamable marking is correct. Just say that that if there's an overlapping implicit def, we have to follow some some target-specific rule to perform the rewrite.

The problem with rewriting implicit defs, in general, is that the target-independent instruction definition doesn't naturally encode any information about them. If we're looking at ORRWrs specifically, sure, we can say that the implicit def corresponds to the result register. But in general, it's an arbitrary register with unknown register allocation constraints. Some can't be rewritten at all; for example, something like TLSDESC_CALLSEQ. (Not sure we have those specifically this late, but there are a bunch of similar sorts of instructions.)

I think what should be happening here is that canRenameMOP() shouldn't accept arbitrary implciit defs. If it's going to accept any, it needs to be ones where we know the specific rule required to rewrite them.

@fhahn Any thoughts?

[fhahn]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

260

@fhahn Any thoughts?

Just coming back to this now, sorry!

I think renaming implicit defs like in the ORRWrs case is quite valuable, because those are quite common.

Not sure how to best encode it, but teaching canRenameMOP about them might be the best way forward for now. I don't think there's any existing info that we can use.

[c-rhodes]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

260

Thinking about it a bit more, I guess you could argue the renamable marking is correct. Just say that that if there's an overlapping implicit def, we have to follow some some target-specific rule to perform the rewrite.

The problem with rewriting implicit defs, in general, is that the target-independent instruction definition doesn't naturally encode any information about them. If we're looking at ORRWrs specifically, sure, we can say that the implicit def corresponds to the result register. But in general, it's an arbitrary register with unknown register allocation constraints. Some can't be rewritten at all; for example, something like TLSDESC_CALLSEQ. (Not sure we have those specifically this late, but there are a bunch of similar sorts of instructions.)

I think what should be happening here is that canRenameMOP() shouldn't accept arbitrary implciit defs. If it's going to accept any, it needs to be ones where we know the specific rule required to rewrite them.

Sorry just coming back to this myself. Restricting the opcode to ORRWrs for implicit defs in canRenameMOP should be straightforward enough, but supporting the rename in UpdateMIs will still need fixing. I feel like most of the complexity there now stems from the use of MachineInstr::getRegClassConstraint, how necessary is it to use this and would it be possible to revert that change to getMinimalPhysRegClass?

[c-rhodes]

Fix renaming of implicit-defs but only allow it for certain opcodes.

[c-rhodes]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

260

Thinking about it a bit more, I guess you could argue the renamable marking is correct. Just say that that if there's an overlapping implicit def, we have to follow some some target-specific rule to perform the rewrite.

The problem with rewriting implicit defs, in general, is that the target-independent instruction definition doesn't naturally encode any information about them. If we're looking at ORRWrs specifically, sure, we can say that the implicit def corresponds to the result register. But in general, it's an arbitrary register with unknown register allocation constraints. Some can't be rewritten at all; for example, something like TLSDESC_CALLSEQ. (Not sure we have those specifically this late, but there are a bunch of similar sorts of instructions.)

I think what should be happening here is that canRenameMOP() shouldn't accept arbitrary implciit defs. If it's going to accept any, it needs to be ones where we know the specific rule required to rewrite them.

Sorry just coming back to this myself. Restricting the opcode to ORRWrs for implicit defs in canRenameMOP should be straightforward enough, but supporting the rename in UpdateMIs will still need fixing. I feel like most of the complexity there now stems from the use of MachineInstr::getRegClassConstraint, how necessary is it to use this and would it be possible to revert that change to getMinimalPhysRegClass?

I've implemented an opcode whitelist for renaming implicit-defs and fixed the issue I mentioned in test8 by choosing the destination register for ORRWrs. Let us know if this is along the right lines and apologies for the delay in updating this patch.

[c-rhodes]

I know this patch has stalled but it would be good to revive the discussion in the context of D105572, which adds MC layer support for load/store instructions in the Arm Scalable Matrix Extension (SME). These instructions (e.g. [1]) have a 32-bit slice index register in the range W12-W15 that's defined as:

def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>;
def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
  let EncoderMethod = "EncodeMatrixIndexGPR32";
}

Adding this class is affecting the ld/st optimizer and causing differences in the tests listed here. For now I've just re-generated the tests in D105572 but it would be good if this issue can be resolved.

[1] https://developer.arm.com/documentation/ddi0602/2021-06/SME-Instructions/LD1B--Contiguous-load-of-bytes-to-8-bit-element-ZA-tile-slice-

[efriedma]

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

914

We don't want to repeat this list of opcodes in multiple places.

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

258

Somehow the implicit-def is getting rewritten from an x register to a w register?

If the implicit-def is dead, we can just drop it from the operand list. If it's not, rewriting like this is going to mess with liveness computation.

[c-rhodes]

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

914

Makes sense, I'll create a function.

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

258

Somehow the implicit-def is getting rewritten from an x register to a w register?

Ah, that'll be because in UpdateMIs when getRegClassConstraint returns NULL for the implicit-def register it uses the result register, assuming the opcode is in the whitelist. I don't think getRegClassConstraint will work for this implicit-def operand, I suppose getMinimalPhysRegClass could be called instead if register class can't be determined by getRegClassConstraint?

[c-rhodes]

• Moved opcode whitelist to function.
• Use getMinimalPhysRegClass for implicit-def operand when getRegClassConstraint returns NULL.

[c-rhodes]

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

258

Somehow the implicit-def is getting rewritten from an x register to a w register?

Ah, that'll be because in UpdateMIs when getRegClassConstraint returns NULL for the implicit-def register it uses the result register, assuming the opcode is in the whitelist. I don't think getRegClassConstraint will work for this implicit-def operand, I suppose getMinimalPhysRegClass could be called instead if register class can't be determined by getRegClassConstraint?

I've updated the patch to use getMinimalPhysRegClass for the implicit-def operand RC when getRegClassConstraint returns NULL, rather than copying the result register. The implicit-def is no longer getting rewritten from an x register to a w register, hopefully the fix is ok?

[c-rhodes]

ping

[aemerson]

@efriedma Could you take another look at this?

[aemerson]

Another ping.

[efriedma]

LGTM

Sorry about the delay, I completely forgot about this.

Renamable implicit defs still feel little weird, but what this patch is doing seems self-consistent, at least. Maybe we should consider factoring out helper functions for some of register handling stuff.

[c-rhodes]

In D88663#3869433, @efriedma wrote:

LGTM

Sorry about the delay, I completely forgot about this.

Renamable implicit defs still feel little weird, but what this patch is doing seems self-consistent, at least. Maybe we should consider factoring out helper functions for some of register handling stuff.

thanks for accepting. It's been a long time since I've looked at this and I'm not familiar with it anymore but I'll rebase and see if it still works.

[c-rhodes]

Rebase. Reviving this as it's apparently come up again when adding a new register class.

[paulwalker-arm]

That's for resurrecting this fix @c-rhodes.

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

case AArch64::STPXi:
     // Make sure this is a reg+imm (as opposed to an address reloc).
     if (!AArch64InstrInfo::getLdStOffsetOp(MI).isImm())
       return false;
 
     return true;
   }
 }
 
+static bool isRewritableImplicitDef(unsigned Opc) {
+  switch (Opc) {
+  default:
+    return false;
+  case AArch64::ORRWrs:
+  case AArch64::ADDWri:
+    return true;
+  }
+}
+
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
                                            MachineBasicBlock::iterator MergeMI,
                                            const LdStPairFlags &Flags) {
   assert(isPromotableZeroStoreInst(*I) && isPromotableZeroStoreInst(*MergeMI) &&
          "Expected promotable zero stores.");
 
   MachineBasicBlock::iterator E = I->getParent()->end();
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
 
   std::optional<MCPhysReg> RenameReg = Flags.getRenameReg();
   if (MergeForward && RenameReg) {
     MCRegister RegToRename = getLdStRegOp(*I).getReg();
     DefinedInBB.addReg(*RenameReg);
 
     // Return the sub/super register for RenameReg, matching the size of
     // OriginalReg.
-    auto GetMatchingSubReg = [this,
-                              RenameReg](MCPhysReg OriginalReg) -> MCPhysReg {
-      for (MCPhysReg SubOrSuper : TRI->sub_and_superregs_inclusive(*RenameReg))
-        if (TRI->getMinimalPhysRegClass(OriginalReg) ==
-            TRI->getMinimalPhysRegClass(SubOrSuper))
+    auto GetMatchingSubReg =
+        [this, RenameReg](const TargetRegisterClass *C) -> MCPhysReg {
+      for (MCPhysReg SubOrSuper :
+           TRI->sub_and_superregs_inclusive(*RenameReg)) {
+        if (C->contains(SubOrSuper))
           return SubOrSuper;
+      }
       llvm_unreachable("Should have found matching sub or super register!");
     };
 
     std::function<bool(MachineInstr &, bool)> UpdateMIs =
         [this, RegToRename, GetMatchingSubReg](MachineInstr &MI, bool IsDef) {
           if (IsDef) {
             bool SeenDef = false;
-            for (auto &MOP : MI.operands()) {
+            for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); ++OpIdx) {
+              MachineOperand &MOP = MI.getOperand(OpIdx);
               // Rename the first explicit definition and all implicit
               // definitions matching RegToRename.
               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
                   (!SeenDef || (MOP.isDef() && MOP.isImplicit())) &&
                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {
                 assert((MOP.isImplicit() ||
                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
                        "Need renamable operands");
-                MOP.setReg(GetMatchingSubReg(MOP.getReg()));
+                Register MatchingReg;
+                if (const TargetRegisterClass *RC =
+                        MI.getRegClassConstraint(OpIdx, TII, TRI))
+                  MatchingReg = GetMatchingSubReg(RC);
+                else {
+                  if (!isRewritableImplicitDef(MI.getOpcode()))
+                    continue;
+                  MatchingReg = GetMatchingSubReg(
+                      TRI->getMinimalPhysRegClass(MOP.getReg()));
+                }
+                MOP.setReg(MatchingReg);
                 SeenDef = true;
               }
             }
           } else {
-            for (auto &MOP : MI.operands()) {
+            for (unsigned OpIdx = 0; OpIdx < MI.getNumOperands(); ++OpIdx) {
+              MachineOperand &MOP = MI.getOperand(OpIdx);
               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {
                 assert((MOP.isImplicit() ||
                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
                            "Need renamable operands");
-                MOP.setReg(GetMatchingSubReg(MOP.getReg()));
+                const TargetRegisterClass *RC =
+                    MI.getRegClassConstraint(OpIdx, TII, TRI);
+                if (!RC)
+                  continue;
+                MOP.setReg(GetMatchingSubReg(RC));
               }
             }
           }
           LLVM_DEBUG(dbgs() << "Renamed " << MI << "\n");
           return true;
         };
     forAllMIsUntilDef(*I, RegToRename, TRI, LdStLimit, UpdateMIs);
 
if (MOP.isReg()) {
       // whole register.
       if (RegClass->HasDisjunctSubRegs) {
         LLVM_DEBUG(
             dbgs()
             << "  Cannot rename operands with multiple disjunct subregisters ("
             << MOP << ")\n");
         return false;
       }
+
+      // We cannot rename arbitrary implicit-defs, the specific rule to rewrite
+      // them must be known. For example, in ORRWrs the implicit-def
+      // corresponds to the result register.
+      if (MOP.isImplicit() && MOP.isDef()) {
+        if (!isRewritableImplicitDef(MOP.getParent()->getOpcode()))
+          return false;
+        return TRI->isSuperOrSubRegisterEq(
+            MOP.getParent()->getOperand(0).getReg(), MOP.getReg());
+      }
     }
     return MOP.isImplicit() ||
            (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());
   };
 
   bool FoundDef = false;
 
   // For each instruction between FirstMI and the previous def for RegToRename,
return any_of(TRI->sub_and_superregs_inclusive(PR),
                     return TRI->isCalleeSavedPhysReg(SubOrSuper, MF);
                   });
   };
 
   // Check if PR or one of its sub- or super-registers can be used for all
   // required register classes.
   auto CanBeUsedForAllClasses = [&RequiredClasses, TRI](MCPhysReg PR) {
     return all_of(RequiredClasses, [PR, TRI](const TargetRegisterClass *C) {
-      return any_of(TRI->sub_and_superregs_inclusive(PR),
-                    [C, TRI](MCPhysReg SubOrSuper) {
-                      return C == TRI->getMinimalPhysRegClass(SubOrSuper);
-                    });
+      return any_of(
+          TRI->sub_and_superregs_inclusive(PR),
+          [C](MCPhysReg SubOrSuper) { return C->contains(SubOrSuper); });
     });
   };
 
   auto *RegClass = TRI->getMinimalPhysRegClass(Reg);
   for (const MCPhysReg &PR : *RegClass) {
     if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
         !RegInfo.isReserved(PR) && !AnySubOrSuperRegCalleePreserved(PR) &&
         CanBeUsedForAllClasses(PR)) {

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir

bb.0:
     STRXui renamable $x9, renamable $x0, 100 :: (store (s64), align 4)
     renamable $x8 = ADDXrr $x8, $x8
     STRXui renamable $x8, renamable $x0, 10 :: (store (s64), align 4)
     RET undef $lr
 
 ...
 # CHECK-LABEL: name: test2
 # CHECK:       bb.0:
-# CHECK-NEXT:     liveins: $x0, $x1, $x10, $x11, $x12, $x13
+# CHECK-NEXT:     liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13
 # CHECK:          renamable $w19 = LDRWui renamable $x0, 0 :: (load (s64))
 # PRESERVED-NEXT: renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
 # NOPRES-NEXT:    renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
 # CHECK-NEXT:     STRXui killed renamable $x9, renamable $x0, 11 :: (store (s64), align 4)
 # CHECK-NEXT:     renamable $x9 = LDRXui renamable $x0, 3 :: (load (s64))
 # CHECK-NEXT:     renamable $x14 = LDRXui renamable $x0, 5 :: (load (s64))
 # PRESERVED-NEXT: STRXui renamable $x9, renamable $x0, 10 :: (store (s64), align 4)
 # NOPRES-NEXT:    STRXui renamable $x9, renamable $x0, 10 :: (store (s64), align 4)
liveins:
   - { reg: '$x1' }
   - { reg: '$x8' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
-    liveins: $x0, $x1, $x10, $x11, $x12, $x13
+    liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13
     renamable $w19 = LDRWui renamable $x0, 0 :: (load (s64))
     renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
     STRXui renamable killed $x9, renamable $x0, 11 :: (store (s64), align 4)
     renamable $x9 = LDRXui renamable $x0, 3 :: (load (s64))
     renamable $x14 = LDRXui renamable $x0, 5 :: (load (s64))
     STRXui renamable $x9, renamable $x0, 10 :: (store (s64), align 4)
     STRXui renamable killed $x14, renamable $x0, 200 :: (store (s64), align 4)
     renamable $w8 = ADDWrr $w19, $w19
     STRWui renamable $w8, renamable $x0, 100 :: (store (s64), align 4)
     RET undef $lr
 
 ...
 ---

llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir

 
 # This test also checks that pairwise store STP is generated.
 
 # CHECK-LABLE: test
 # CHECK: bb.0:
 # CHECK-NEXT: liveins: $x0, $x17, $x18
 # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
 # CHECK-NEXT: renamable $q23_q24_q25 = LD3Threev16b undef renamable $x18 :: (load (s384) from `ptr undef`, align 64)
-# CHECK-NEXT: $q16 = EXTv16i8 renamable $q23, renamable $q23, 8
+# CHECK-NEXT: $q0 = EXTv16i8 renamable $q23, renamable $q23, 8
 # CHECK-NEXT: renamable $q20 = EXTv16i8 renamable $q14, renamable $q14, 8
 # CHECK-NEXT: STRQui killed renamable $q20, $sp, 4 :: (store (s128))
 # CHECK-NEXT: renamable $d6 = ZIP2v8i8 renamable $d23, undef renamable $d16
 # CHECK-NEXT: STRDui killed renamable $d6, $sp, 11 :: (store (s64))
 # CHECK-NEXT: renamable $q6 = EXTv16i8 renamable $q13, renamable $q13, 8
-# CHECK-NEXT: STPQi killed renamable $q6, killed $q16, $sp, 6 :: (store (s128))
+# CHECK-NEXT: STPQi killed renamable $q6, killed $q0, $sp, 6 :: (store (s128))
 # CHECK-NEXT: RET undef $lr
 
 ---
 name:            test
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0', virtual-reg: '' }

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

bb.0:
     RET undef $lr
 ...
 ---
 # CHECK-LABEL: name: test8
 # CHECK-LABEL:  bb.0:
 # CHECK-NEXT:    liveins: $x0, $x1
 
 # CHECK:         renamable $x8 = MRS 58880
 # CHECK-NEXT:    $w9 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x9
 # CHECK-NEXT:    renamable $x8 = MRS 55840
 # CHECK-NEXT:    STPWi $w9, killed renamable $w8, killed renamable $x0, 0 :: (store (s32))
 # CHECK-NEXT:    RET undef $lr
 
 name:            test8
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
bb.0:
     RET undef $lr
 
 ...
 ---
 # Make sure we do not use any registers that are defined between paired candidates
 # ($x14 in this example)
 # CHECK-LABEL: name: test11
 # CHECK: bb.0:
-# CHECK-NEXT: liveins: $x0, $x1, $x11, $x12, $x13
+# CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x11, $x12, $x13
 
 # CHECK:         renamable $w10 = LDRWui renamable $x0, 0 :: (load (s64))
 # CHECK-NEXT:    renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
 # CHECK-NEXT:    STRXui killed renamable $x9, renamable $x0, 11 :: (store (s64), align 4)
 # CHECK-NEXT:    renamable $x9 = LDRXui renamable $x0, 3 :: (load (s64))
 # CHECK-NEXT:    renamable $x14 = LDRXui renamable $x0, 5 :: (load (s64))
 # CHECK-NEXT:    STRXui renamable $x9, renamable $x0, 10 :: (store (s64), align 4)
 # CHECK-NEXT:    STRXui killed renamable $x14, renamable $x0, 200 :: (store (s64), align 4)
liveins:
   - { reg: '$x1' }
   - { reg: '$x8' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
-    liveins: $x0, $x1, $x11, $x12, $x13
+    liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x11, $x12, $x13
     renamable $w10 = LDRWui renamable $x0, 0 :: (load (s64))
     renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load (s64))
     STRXui renamable killed $x9, renamable $x0, 11 :: (store (s64), align 4)
     renamable $x9 = LDRXui renamable $x0, 3 :: (load (s64))
     renamable $x14 = LDRXui renamable $x0, 5 :: (load (s64))
     STRXui renamable $x9, renamable $x0, 10 :: (store (s64), align 4)
     STRXui renamable killed $x14, renamable $x0, 200 :: (store (s64), align 4)
     renamable $w8 = ADDWrr $w10, $w10
bb.0:
     RET undef $lr
 
 ...
 ---
 # Make sure we do not use any registers that are defined between def to rename and the first
 # paired store. ($x14 in this example)
 # CHECK-LABEL: name: test13
 # CHECK: bb.0:
-# CHECK-NEXT: liveins: $x0, $x1, $x10, $x11, $x12, $x13
+# CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x10, $x11, $x12, $x13
 # CHECK:    renamable $x9, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
 # CHECK-NEXT:    renamable $x14 = LDRXui renamable $x0, 4 :: (load (s64))
 # CHECK-NEXT:    STRXui killed renamable $x14, renamable $x0, 100 :: (store (s64), align 4)
 # CHECK-NEXT:    STRXui killed renamable $x9, renamable $x0, 11 :: (store (s64), align 4)
 # CHECK-NEXT:    renamable $x9 = LDRXui renamable $x0, 2 :: (load (s64))
 # CHECK-NEXT:    STRXui renamable $x9, renamable $x0, 10 :: (store (s64))
 # CHECK-NEXT:    RET undef $lr
 #
 name:            test13
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
   - { reg: '$x8' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
-    liveins: $x0, $x1, $x10, $x11, $x12, $x13
+    liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x10, $x11, $x12, $x13
     renamable $x9, renamable $x8 = LDPXi renamable $x0, 0 :: (load (s64))
     renamable $x14 = LDRXui renamable $x0, 4 :: (load (s64))
     STRXui renamable killed $x14, renamable $x0, 100 :: (store (s64), align 4)
     STRXui renamable killed $x9, renamable $x0, 11 :: (store (s64), align 4)
     renamable $x9 = LDRXui renamable $x0, 2 :: (load (s64))
     STRXui renamable $x9, renamable $x0, 10 :: (store (s64))
     RET undef $lr