[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

[craig.topper]

Summary

This is a replacement for D101938 for inserting vsetvli
instructions where needed. This new version changes how
we track the information in such a way that we can extend
it to be aware of VL/VTYPE changes in other blocks. Given
how much it changes the previous patch, I've decided to
abandon the previous patch and post this from scratch.

The pass now consists of 3 phases. The first phase inserts
intra block vsetvlis and collects the requirements for the
first instruction in the block. The second phase calculates
the incoming value for each block. The third phase checks
the requirements against the incoming value and inserts a
vsetvli if needed.

For now I've stubbed out phase 2 to make it equivalent to
D101938. The only change from the tests in D101938 is the
numbering of virtual registers in one test in vsetvli-insert.mir.

[rogfer01]

This is looking great.

I was wondering if we can delay all the insertions to phase 3. I understand this would require keep tracking the insertion points. I mention that because it could help if we want to be able to simplify further the insertion points after phase1 or phase2. In that setting, phase 1 could be named something like computeDemandedVSETVL, phase 2 could be computeIncomingVLVTYPE and then phase 3 emitVSETVL

An example of possible optimization, could be a loop that loads SEW=32 vectors and does a widening operation (say vfwmac) and stores the resulting SEW=64 (without further processing that vector) using vse64. Looks to me we could just go with a single vsetvl here with SEW=32.

What do you think?

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

318

Not sure what this RequirePending refers to?

[arcbbb]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

302

is the assertion avoidable by doing setAVLReg(RISCV::NoRegister) for vtype-only change, and something like
BBInfo.change = Merge(BBInfo.change, getInfoForVSETVLI) to keep the latest VL & vtype change ?

[craig.topper]

Remove reference to RequirePending.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

318

At one point I was using AMDGPUs SIModeRegister pass as a reference for this cross basic block stuff and that got copied from there before I realized I didn't need it.

[craig.topper]

In D102737#2770360, @rogfer01 wrote:

This is looking great.

I was wondering if we can delay all the insertions to phase 3. I understand this would require keep tracking the insertion points. I mention that because it could help if we want to be able to simplify further the insertion points after phase1 or phase2. In that setting, phase 1 could be named something like computeDemandedVSETVL, phase 2 could be computeIncomingVLVTYPE and then phase 3 emitVSETVL

An example of possible optimization, could be a loop that loads SEW=32 vectors and does a widening operation (say vfwmac) and stores the resulting SEW=64 (without further processing that vector) using vse64. Looks to me we could just go with a single vsetvl here with SEW=32.

What do you think?

We can probably do it in phase 1 at least when the previous instruction is in the same block. Harder if the instruction is in a predecessor block. Though if the previous instruction isn't in the same block and there are no instructions after it, I'm not sure what value to propagate to the successors for the data flow.

[craig.topper]

Handle the all insertion in "phase 3" which is the only phase in this patch.

[arcbbb]

LGTM

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

302

Sorry I forgot it was not possible because vsetvli wasn't inserted at this stage. Please ignore it.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

273

"ask" the requirements start "from" this ...?

[HsiangKai]

LGTM.

[craig.topper]

Cleanup a poorly written comment

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

11

Documenting this pass and its phases in line with the commit message would be good.

19

nit: I can imagine this is used by later patches, but it's not used by this one.

llvm/lib/Target/RISCV/CMakeLists.txt

 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
 add_llvm_target(RISCVCodeGen
   RISCVAsmPrinter.cpp
   RISCVCallLowering.cpp
-  RISCVCleanupVSETVLI.cpp
   RISCVExpandAtomicPseudoInsts.cpp
   RISCVExpandPseudoInsts.cpp
   RISCVFrameLowering.cpp
+  RISCVInsertVSETVLI.cpp
   RISCVInstrInfo.cpp
   RISCVInstructionSelector.cpp
   RISCVISelDAGToDAG.cpp
   RISCVISelLowering.cpp
   RISCVLegalizerInfo.cpp
   RISCVMCInstLower.cpp
   RISCVMergeBaseOffset.cpp
   RISCVRegisterBankInfo.cpp

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 // Match with the definitions in RISCVInstrFormatsV.td
 enum VConstraintType {
   NoConstraint = 0,
   VS2Constraint = 0b001,
   VS1Constraint = 0b010,
   VMConstraint = 0b100,
 };
 
-enum VLMUL {
+enum VLMUL : uint8_t {
   LMUL_1 = 0,
   LMUL_2,
   LMUL_4,
   LMUL_8,
   LMUL_RESERVED,
   LMUL_F8,
   LMUL_F4,
   LMUL_F2

llvm/lib/Target/RISCV/RISCV.h

 void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
 
 FunctionPass *createRISCVExpandPseudoPass();
 void initializeRISCVExpandPseudoPass(PassRegistry &);
 
 FunctionPass *createRISCVExpandAtomicPseudoPass();
 void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
 
-FunctionPass *createRISCVCleanupVSETVLIPass();
-void initializeRISCVCleanupVSETVLIPass(PassRegistry &);
+FunctionPass *createRISCVInsertVSETVLIPass();
+void initializeRISCVInsertVSETVLIPass(PassRegistry &);
 
 InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
                                                     RISCVSubtarget &,
                                                     RISCVRegisterBankInfo &);
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp

-//===- RISCVCleanupVSETVLI.cpp - Cleanup unneeded VSETVLI instructions ----===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements a function pass that removes duplicate vsetvli
-// instructions within a basic block.
-//
-//===----------------------------------------------------------------------===//
-
-#include "RISCV.h"
-#include "RISCVSubtarget.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-using namespace llvm;
-
-#define DEBUG_TYPE "riscv-cleanup-vsetvli"
-#define RISCV_CLEANUP_VSETVLI_NAME "RISCV Cleanup VSETVLI pass"
-
-namespace {
-
-class RISCVCleanupVSETVLI : public MachineFunctionPass {
-public:
-  static char ID;
-
-  RISCVCleanupVSETVLI() : MachineFunctionPass(ID) {
-    initializeRISCVCleanupVSETVLIPass(*PassRegistry::getPassRegistry());
-  }
-  bool runOnMachineFunction(MachineFunction &MF) override;
-  bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
-
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
-  }
-
-  // This pass modifies the program, but does not modify the CFG
-  void getAnalysisUsage(AnalysisUsage &AU) const override {
-    AU.setPreservesCFG();
-    MachineFunctionPass::getAnalysisUsage(AU);
-  }
-
-  StringRef getPassName() const override { return RISCV_CLEANUP_VSETVLI_NAME; }
-};
-
-} // end anonymous namespace
-
-char RISCVCleanupVSETVLI::ID = 0;
-
-INITIALIZE_PASS(RISCVCleanupVSETVLI, DEBUG_TYPE,
-                RISCV_CLEANUP_VSETVLI_NAME, false, false)
-
-static bool isRedundantVSETVLI(MachineInstr &MI, MachineInstr *PrevVSETVLI) {
-  // If we don't have a previous VSET{I}VLI or the VL output isn't dead, we
-  // can't remove this VSETVLI.
-  if (!PrevVSETVLI || !MI.getOperand(0).isDead())
-    return false;
-
-  // Does this VSET{I}VLI use the same VTYPE immediate.
-  int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm();
-  int64_t VTYPEImm = MI.getOperand(2).getImm();
-  if (PrevVTYPEImm != VTYPEImm)
-    return false;
-
-  if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
-    // If the previous opcode wasn't vsetivli we can't compare them.
-    if (PrevVSETVLI->getOpcode() != RISCV::PseudoVSETIVLI)
-      return false;
-
-    // For VSETIVLI, we can just compare the immediates.
-    return PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
-  }
-
-  assert(MI.getOpcode() == RISCV::PseudoVSETVLI);
-  Register AVLReg = MI.getOperand(1).getReg();
-  Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg();
-
-  // If this VSETVLI isn't changing VL, it is redundant.
-  if (AVLReg == RISCV::X0 && MI.getOperand(0).getReg() == RISCV::X0)
-    return true;
-
-  // If the previous VSET{I}VLI's output (which isn't X0) is fed into this
-  // VSETVLI, this one isn't changing VL so is redundant.
-  // Only perform this on virtual registers to avoid the complexity of having
-  // to work out if the physical register was clobbered somewhere in between.
-  if (AVLReg.isVirtual() && AVLReg == PrevOutVL)
-    return true;
-
-  // If the previous opcode isn't vsetvli we can't do any more comparison.
-  if (PrevVSETVLI->getOpcode() != RISCV::PseudoVSETVLI)
-    return false;
-
-  // Does this VSETVLI use the same AVL register?
-  if (AVLReg != PrevVSETVLI->getOperand(1).getReg())
-    return false;
-
-  // If the AVLReg is X0 we must be setting VL to VLMAX. Keeping VL unchanged
-  // was handled above.
-  if (AVLReg == RISCV::X0) {
-    // This instruction is setting VL to VLMAX, this is redundant if the
-    // previous VSETVLI was also setting VL to VLMAX. But it is not redundant
-    // if they were setting it to any other value or leaving VL unchanged.
-    return PrevOutVL != RISCV::X0;
-  }
-
-  // This vsetvli is redundant.
-  return true;
-}
-
-bool RISCVCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
-  bool Changed = false;
-  MachineInstr *PrevVSETVLI = nullptr;
-
-  for (auto MII = MBB.begin(), MIE = MBB.end(); MII != MIE;) {
-    MachineInstr &MI = *MII++;
-
-    if (MI.getOpcode() != RISCV::PseudoVSETVLI &&
-        MI.getOpcode() != RISCV::PseudoVSETIVLI) {
-      if (PrevVSETVLI &&
-          (MI.isCall() || MI.modifiesRegister(RISCV::VL) ||
-           MI.modifiesRegister(RISCV::VTYPE))) {
-        // Old VL/VTYPE is overwritten.
-        PrevVSETVLI = nullptr;
-      }
-      continue;
-    }
-
-    if (isRedundantVSETVLI(MI, PrevVSETVLI)) {
-      // This VSETVLI is redundant, remove it.
-      MI.eraseFromParent();
-      Changed = true;
-    } else {
-      // Otherwise update VSET{I}VLI for the next iteration.
-      PrevVSETVLI = &MI;
-    }
-  }
-
-  return Changed;
-}
-
-bool RISCVCleanupVSETVLI::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(MF.getFunction()))
-    return false;
-
-  // Skip if the vector extension is not enabled.
-  const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
-  if (!ST.hasStdExtV())
-    return false;
-
-  bool Changed = false;
-
-  for (MachineBasicBlock &MBB : MF)
-    Changed |= runOnMachineBasicBlock(MBB);
-
-  return Changed;
-}
-
-/// Returns an instance of the Cleanup VSETVLI pass.
-FunctionPass *llvm::createRISCVCleanupVSETVLIPass() {
-  return new RISCVCleanupVSETVLI();
-}

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

bool RISCVExpandPseudo::expandLoadTLSGDAddress(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
   return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
                              RISCV::ADDI);
 }
 
 bool RISCVExpandPseudo::expandVSetVL(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MBBI) {
-  assert(MBBI->getNumOperands() == 5 && "Unexpected instruction format");
+  assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 &&
+         "Unexpected instruction format");
 
   DebugLoc DL = MBBI->getDebugLoc();
 
   assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
           MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&
          "Unexpected pseudo instruction");
   unsigned Opcode;
   if (MBBI->getOpcode() == RISCV::PseudoVSETVLI)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

while (SelectMBBI != SelectEnd) {
     }
     SelectMBBI = Next;
   }
 
   F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
   return TailMBB;
 }
 
-static MachineInstr *elideCopies(MachineInstr *MI,
-                                 const MachineRegisterInfo &MRI) {
-  while (true) {
-    if (!MI->isFullCopy())
-      return MI;
-    if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
-      return nullptr;
-    MI = MRI.getVRegDef(MI->getOperand(1).getReg());
-    if (!MI)
-      return nullptr;
-  }
-}
-
-static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
-                                    int VLIndex, unsigned SEWIndex,
-                                    RISCVII::VLMUL VLMul,
-                                    bool ForceTailAgnostic) {
-  MachineFunction &MF = *BB->getParent();
-  DebugLoc DL = MI.getDebugLoc();
-  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
-
-  unsigned Log2SEW = MI.getOperand(SEWIndex).getImm();
-  unsigned SEW = 1 << Log2SEW;
-  assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
-
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-
-  auto BuildVSETVLI = [&]() {
-    if (VLIndex >= 0) {
-      Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-      const MachineOperand &VLOp = MI.getOperand(VLIndex);
-
-      // VL can be a register or an immediate.
-      if (VLOp.isImm())
-        return BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETIVLI))
-            .addReg(DestReg, RegState::Define | RegState::Dead)
-            .addImm(VLOp.getImm());
-
-      Register VLReg = MI.getOperand(VLIndex).getReg();
-      return BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI))
-          .addReg(DestReg, RegState::Define | RegState::Dead)
-          .addReg(VLReg);
-    }
-
-    // With no VL operator in the pseudo, do not modify VL (rd = X0, rs1 = X0).
-    return BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI))
-        .addReg(RISCV::X0, RegState::Define | RegState::Dead)
-        .addReg(RISCV::X0, RegState::Kill);
-  };
-
-  MachineInstrBuilder MIB = BuildVSETVLI();
-
-  // Default to tail agnostic unless the destination is tied to a source. In
-  // that case the user would have some control over the tail values. The tail
-  // policy is also ignored on instructions that only update element 0 like
-  // vmv.s.x or reductions so use agnostic there to match the common case.
-  // FIXME: This is conservatively correct, but we might want to detect that
-  // the input is undefined.
-  bool TailAgnostic = true;
-  unsigned UseOpIdx;
-  if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
-    TailAgnostic = false;
-    // If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
-    const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
-    MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg());
-    if (UseMI) {
-      UseMI = elideCopies(UseMI, MRI);
-      if (UseMI && UseMI->isImplicitDef())
-        TailAgnostic = true;
-    }
-  }
-
-  // For simplicity we reuse the vtype representation here.
-  MIB.addImm(RISCVVType::encodeVTYPE(VLMul, SEW,
-                                     /*TailAgnostic*/ TailAgnostic,
-                                     /*MaskAgnostic*/ false));
-
-  // Remove (now) redundant operands from pseudo
-  if (VLIndex >= 0 && MI.getOperand(VLIndex).isReg()) {
-    MI.getOperand(VLIndex).setReg(RISCV::NoRegister);
-    MI.getOperand(VLIndex).setIsKill(false);
-  }
-
-  return BB;
-}
-
 MachineBasicBlock *
 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                  MachineBasicBlock *BB) const {
-  uint64_t TSFlags = MI.getDesc().TSFlags;
-
-  if (RISCVII::hasSEWOp(TSFlags)) {
-    unsigned NumOperands = MI.getNumExplicitOperands();
-    int VLIndex = RISCVII::hasVLOp(TSFlags) ? NumOperands - 2 : -1;
-    unsigned SEWIndex = NumOperands - 1;
-    bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
-
-    RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags);
-    return addVSetVL(MI, BB, VLIndex, SEWIndex, VLMul, ForceTailAgnostic);
-  }
-
   switch (MI.getOpcode()) {
   default:
     llvm_unreachable("Unexpected instr type to insert");
   case RISCV::ReadCycleWide:
     assert(!Subtarget.is64Bit() &&
            "ReadCycleWrite is only to be used on riscv32");
     return emitReadCycleWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

+//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function pass that inserts VSETVLI instructions where
+// needed.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include <queue>
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-insert-vsetvli"
+#define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass"
+
+namespace {
+
+class VSETVLIInfo {
+  union {
+    Register AVLReg;
+    unsigned AVLImm;
+  };
+
+  enum : uint8_t {
+    Uninitialized,
+    AVLIsReg,
+    AVLIsImm,
+    Unknown,
+  } State = Uninitialized;
+
+  // Fields from VTYPE.
+  RISCVII::VLMUL VLMul = RISCVII::LMUL_1;
+  uint8_t SEW = 0;
+  bool TailAgnostic = false;
+  bool MaskAgnostic = false;
+
+public:
+  VSETVLIInfo() : AVLImm(0) {}
+
+  bool isValid() const { return State != Uninitialized; }
+  void setUnknown() { State = Unknown; }
+  bool isUnknown() const { return State == Unknown; }
+
+  void setAVLReg(Register Reg) {
+    AVLReg = Reg;
+    State = AVLIsReg;
+  }
+
+  void setAVLImm(unsigned Imm) {
+    AVLImm = Imm;
+    State = AVLIsImm;
+  }
+
+  bool hasAVLImm() const { return State == AVLIsImm; }
+  bool hasAVLReg() const { return State == AVLIsReg; }
+  Register getAVLReg() const {
+    assert(hasAVLReg());
+    return AVLReg;
+  }
+  unsigned getAVLImm() const {
+    assert(hasAVLImm());
+    return AVLImm;
+  }
+
+  bool hasSameAVL(const VSETVLIInfo &Other) const {
+    assert(isValid() && Other.isValid() &&
+           "Can't compare invalid VSETVLIInfos");
+    assert(!isUnknown() && !Other.isUnknown() &&
+           "Can't compare AVL in unknown state");
+    if (hasAVLReg() && Other.hasAVLReg())
+      return getAVLReg() == Other.getAVLReg();
+
+    if (hasAVLImm() && Other.hasAVLImm())
+      return getAVLImm() == Other.getAVLImm();
+
+    return false;
+  }
+
+  void setVTYPE(unsigned VType) {
+    assert(isValid() && !isUnknown() &&
+           "Can't set VTYPE for uninitialized or unknown");
+    VLMul = RISCVVType::getVLMUL(VType);
+    SEW = RISCVVType::getSEW(VType);
+    TailAgnostic = RISCVVType::isTailAgnostic(VType);
+    MaskAgnostic = RISCVVType::isMaskAgnostic(VType);
+  }
+  void setVTYPE(RISCVII::VLMUL L, unsigned S, bool TA, bool MA) {
+    assert(isValid() && !isUnknown() &&
+           "Can't set VTYPE for uninitialized or unknown");
+    VLMul = L;
+    SEW = S;
+    TailAgnostic = TA;
+    MaskAgnostic = MA;
+  }
+
+  unsigned encodeVTYPE() const {
+    return RISCVVType::encodeVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
+  }
+
+  bool hasSameVTYPE(const VSETVLIInfo &Other) const {
+    assert(isValid() && Other.isValid() &&
+           "Can't compare invalid VSETVLIInfos");
+    assert(!isUnknown() && !Other.isUnknown() &&
+           "Can't compare VTYPE in unknown state");
+    return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
+           std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic,
+                    Other.MaskAgnostic);
+  }
+
+  bool isCompatible(const VSETVLIInfo &Other) const {
+    assert(isValid() && Other.isValid() &&
+           "Can't compare invalid VSETVLIInfos");
+    // Nothing is compatible with Unknown.
+    if (isUnknown() || Other.isUnknown())
+      return false;
+
+    // If other doesn't need an AVLReg and the SEW matches, consider it
+    // compatible.
+    if (Other.hasAVLReg() && Other.AVLReg == RISCV::NoRegister) {
+      if (SEW == Other.SEW)
+        return true;
+    }
+
+    // VTypes must match.
+    if (!hasSameVTYPE(Other))
+      return false;
+
+    if (hasAVLImm() != Other.hasAVLImm())
+      return false;
+
+    if (hasAVLImm())
+      return getAVLImm() == Other.getAVLImm();
+
+    return getAVLReg() == Other.getAVLReg();
+  }
+};
+
+struct BlockData {
+  // The VSETVLIInfo that represents the settings required by the
+  // FirstInsertionPoint (if any), in this block. Calculated in Phase 1.
+  VSETVLIInfo Require;
+
+  // The VSETVLIInfo that represents the net changes to the VL/VTYPE registers
+  // made by this block. Calculated in Phase 1.
+  VSETVLIInfo Change;
+
+  // The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
+  // blocks. Calculated in Phase 2, and used by Phase 3.
+  VSETVLIInfo Pred;
+
+  // In Phase 1 we record the first instruction that has a mode requirement,
+  // which is used in Phase3 if we need to insert a mode change.
+  MachineInstr *FirstInsertionPoint = nullptr;
+
+  BlockData() {}
+};
+
+class RISCVInsertVSETVLI : public MachineFunctionPass {
+  const TargetInstrInfo *TII;
+  MachineRegisterInfo *MRI;
+
+  std::vector<BlockData> BlockInfo;
+  std::queue<MachineBasicBlock *> Phase2List;
+
+public:
+  static char ID;
+
+  RISCVInsertVSETVLI() : MachineFunctionPass(ID) {
+    initializeRISCVInsertVSETVLIPass(*PassRegistry::getPassRegistry());
+  }
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_INSERT_VSETVLI_NAME; }
+
+private:
+  void insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
+                     const VSETVLIInfo &Info);
+
+  bool processBlockPhase1(MachineBasicBlock &MBB);
+  void processBlockPhase2(MachineBasicBlock &MBB);
+  void processBlockPhase3(MachineBasicBlock &MBB);
+};
+
+} // end anonymous namespace
+
+char RISCVInsertVSETVLI::ID = 0;
+
+INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
+                false, false)
+
+static MachineInstr *elideCopies(MachineInstr *MI,
+                                 const MachineRegisterInfo *MRI) {
+  while (true) {
+    if (!MI->isFullCopy())
+      return MI;
+    if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
+      return nullptr;
+    MI = MRI->getVRegDef(MI->getOperand(1).getReg());
+    if (!MI)
+      return nullptr;
+  }
+}
+
+static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
+                                       const MachineRegisterInfo *MRI) {
+  VSETVLIInfo InstrInfo;
+  unsigned NumOperands = MI.getNumExplicitOperands();
+
+  RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags);
+
+  unsigned Log2SEW = MI.getOperand(NumOperands - 1).getImm();
+  unsigned SEW = 1 << Log2SEW;
+  assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
+
+  // Default to tail agnostic unless the destination is tied to a source.
+  // Unless the source is undef. In that case the user would have some control
+  // over the tail values. The tail policy is also ignored on instructions
+  // that only update element 0 like vmv.s.x or reductions so use agnostic
+  // there to match the common case.
+  // FIXME: This is conservatively correct, but we might want to detect that
+  // the input is undefined.
+  bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFlags);
+  bool TailAgnostic = true;
+  unsigned UseOpIdx;
+  if (!ForceTailAgnostic && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+    TailAgnostic = false;
+    // If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
+    const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
+    MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
+    if (UseMI) {
+      UseMI = elideCopies(UseMI, MRI);
+      if (UseMI && UseMI->isImplicitDef())
+        TailAgnostic = true;
+    }
+  }
+
+  if (RISCVII::hasVLOp(TSFlags)) {
+    const MachineOperand &VLOp = MI.getOperand(MI.getNumExplicitOperands() - 2);
+    if (VLOp.isImm())
+      InstrInfo.setAVLImm(VLOp.getImm());
+    else
+      InstrInfo.setAVLReg(VLOp.getReg());
+  } else
+    InstrInfo.setAVLReg(RISCV::NoRegister);
+  InstrInfo.setVTYPE(VLMul, SEW, /*TailAgnostic*/ TailAgnostic,
+                     /*MaskAgnostic*/ false);
+
+  return InstrInfo;
+}
+
+void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
+                                       const VSETVLIInfo &Info) {
+  DebugLoc DL = MI.getDebugLoc();
+
+  if (Info.hasAVLImm()) {
+    // TODO: Use X0 as the destination.
+    Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
+    BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETIVLI))
+        .addReg(DestReg, RegState::Define | RegState::Dead)
+        .addImm(Info.getAVLImm())
+        .addImm(Info.encodeVTYPE());
+    return;
+  }
+
+  Register AVLReg = Info.getAVLReg();
+  if (AVLReg == RISCV::NoRegister) {
+    BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETVLI))
+        .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+        .addReg(RISCV::X0, RegState::Kill)
+        .addImm(Info.encodeVTYPE())
+        .addReg(RISCV::VL, RegState::Implicit);
+    return;
+  }
+
+  Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
+  BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETVLI))
+      .addReg(DestReg, RegState::Define | RegState::Dead)
+      .addReg(Info.getAVLReg())
+      .addImm(Info.encodeVTYPE());
+}
+
+VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
+  // If we haven't already set the initial requirements for the block we
+  // don't need to ass the requirements start form this explicit vsetvli.
+  VSETVLIInfo NewInfo;
+  if (MI.getOpcode() == RISCV::PseudoVSETVLI) {
+    Register AVLReg = MI.getOperand(1).getReg();
+    assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
+           "Can't handle X0, X0 vsetvli yet");
+    NewInfo.setAVLReg(AVLReg);
+  } else {
+    assert(MI.getOpcode() == RISCV::PseudoVSETIVLI);
+    NewInfo.setAVLImm(MI.getOperand(1).getImm());
+  }
+  NewInfo.setVTYPE(MI.getOperand(2).getImm());
+
+  return NewInfo;
+}
+
+bool RISCVInsertVSETVLI::processBlockPhase1(MachineBasicBlock &MBB) {
+  bool MadeChange = false;
+
+  BlockData &BBInfo = BlockInfo[MBB.getNumber()];
+  // BBInfo.Change being not valid is used to indicate whether we are collecting
+  // the initial requirements for the block.
+  for (MachineInstr &MI : MBB) {
+    // If this is an explicit VSETVLI or VSETIVLI, update our state.
+    if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
+        MI.getOpcode() == RISCV::PseudoVSETIVLI) {
+      // Conservatively, mark the VL and VTYPE as live.
+      assert(MI.getOperand(3).getReg() == RISCV::VL &&
+             MI.getOperand(4).getReg() == RISCV::VTYPE &&
+             "Unexpected operands where VL and VTYPE should be");
+      MI.getOperand(3).setIsDead(false);
+      MI.getOperand(4).setIsDead(false);
+      MadeChange = true;
+      BBInfo.Change = getInfoForVSETVLI(MI);
+      continue;
+    }
+
+    uint64_t TSFlags = MI.getDesc().TSFlags;
+    if (RISCVII::hasSEWOp(TSFlags)) {
+      VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
+      if (RISCVII::hasVLOp(TSFlags)) {
+        MachineOperand &VLOp = MI.getOperand(MI.getNumExplicitOperands() - 2);
+        if (VLOp.isReg()) {
+          // Erase the AVL operand from the instruction.
+          VLOp.setReg(RISCV::NoRegister);
+          VLOp.setIsKill(false);
+        }
+        MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
+                                                /*isImp*/ true));
+      }
+      MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,
+                                              /*isImp*/ true));
+
+      // If this is the first VL/VTYPE user we found and we haven't found
+      // anything that changes VL/VTYPE either, log the requirements and set the
+      // insertion point. This will be used in Phase 3 where we will know if it
+      // is really needed.
+      if (!BBInfo.Change.isValid()) {
+        BBInfo.FirstInsertionPoint = &MI;
+        BBInfo.Require = NewInfo;
+        BBInfo.Change = NewInfo;
+      } else {
+        bool NeedVSETVLI = true;
+        if (BBInfo.Change.isCompatible(NewInfo))
+          NeedVSETVLI = false;
+
+        // We didn't find a compatible value. If our AVL is a virtual register,
+        // it might be defined by a VSET(I)VLI. If it has the same VTYPE we need
+        // and the last VL/VTYPE we observed is the same, we don't need a
+        // VSETVLI here.
+        if (NeedVSETVLI && !BBInfo.Change.isUnknown() && NewInfo.hasAVLReg() &&
+            NewInfo.getAVLReg().isVirtual() &&
+            NewInfo.hasSameVTYPE(BBInfo.Change)) {
+          if (MachineInstr *DefMI = MRI->getVRegDef(NewInfo.getAVLReg())) {
+            if (DefMI->getOpcode() == RISCV::PseudoVSETVLI ||
+                DefMI->getOpcode() == RISCV::PseudoVSETIVLI) {
+              VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+              if (DefInfo.hasSameAVL(BBInfo.Change) &&
+                  DefInfo.hasSameVTYPE(BBInfo.Change))
+                NeedVSETVLI = false;
+            }
+          }
+        }
+
+        // If this instruction isn't compatible with the previous VL/VTYPE
+        // we need to insert a VSETVLI.
+        if (NeedVSETVLI) {
+          insertVSETVLI(MBB, MI, NewInfo);
+          BBInfo.Change = NewInfo;
+        }
+      }
+
+      // If we find an instruction we at least changed the operands.
+      MadeChange = true;
+    }
+    // If this is something updates VL/VTYPE that we don't know about, set
+    // the state to unknown.
+    if (MI.isCall() || MI.modifiesRegister(RISCV::VL) ||
+        MI.modifiesRegister(RISCV::VTYPE)) {
+      VSETVLIInfo NewInfo;
+      NewInfo.setUnknown();
+      BBInfo.Change = NewInfo;
+    }
+  }
+
+  return MadeChange;
+}
+
+void RISCVInsertVSETVLI::processBlockPhase2(MachineBasicBlock &MBB) {
+  unsigned ThisBlock = MBB.getNumber();
+  // TODO: Add a real global data flow.
+  VSETVLIInfo PredInfo;
+  PredInfo.setUnknown();
+  BlockInfo[ThisBlock].Pred = PredInfo;
+}
+
+void RISCVInsertVSETVLI::processBlockPhase3(MachineBasicBlock &MBB) {
+  unsigned ThisBlock = MBB.getNumber();
+  if (BlockInfo[ThisBlock].FirstInsertionPoint &&
+      !BlockInfo[ThisBlock].Pred.isCompatible(BlockInfo[ThisBlock].Require)) {
+    insertVSETVLI(MBB, *BlockInfo[ThisBlock].FirstInsertionPoint,
+                  BlockInfo[ThisBlock].Require);
+  }
+}
+
+bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
+  // Skip if the vector extension is not enabled.
+  const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
+  if (!ST.hasStdExtV())
+    return false;
+
+  TII = ST.getInstrInfo();
+  MRI = &MF.getRegInfo();
+
+  assert(BlockInfo.size() == 0);
+  BlockInfo.resize(MF.getNumBlockIDs());
+
+  bool Changed = false;
+
+  // Processing is performed in a number of phases
+
+  // Phase 1 - determine the initial VL/VTYPE required by each block, and add
+  // vsetvli instructions for intra block requirements.
+  for (MachineBasicBlock &MBB : MF)
+    Changed |= processBlockPhase1(MBB);
+
+  // If we didn't find any instructions that need VSETVLI, we're done.
+  if (Changed) {
+    // Phase 2 - determine the exit VL/VTYPE from each block. We add all
+    // blocks to the list here, but will also add any that need to be revisited
+    // during Phase 2 processing.
+    for (MachineBasicBlock &MBB : MF)
+      Phase2List.push(&MBB);
+    while (!Phase2List.empty()) {
+      processBlockPhase2(*Phase2List.front());
+      Phase2List.pop();
+    }
+
+    // Phase 3 - add an initial vsetvli to each block where the required entry
+    // VL/VTYPE is not satisfied by the exit VL/VTYPE of all its predecessors.
+    for (MachineBasicBlock &MBB : MF)
+      processBlockPhase3(MBB);
+  }
+
+  BlockInfo.clear();
+
+  return Changed;
+}
+
+/// Returns an instance of the Insert VSETVLI pass.
+FunctionPass *llvm::createRISCVInsertVSETVLIPass() {
+  return new RISCVInsertVSETVLI();
+}

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 class VPseudoUSLoadNoMask<VReg RetClass, bits<7> EEW, bit isFF> :
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSLoadMask<VReg RetClass, bits<7> EEW, bit isFF> :
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1,
                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSLoadNoMask<VReg RetClass, bits<7> EEW>:
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSLoadMask<VReg RetClass, bits<7> EEW>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1, GPR:$rs2,
                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                          bit Ordered, bit EarlyClobber>:
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLX</*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoILoadMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                        bit Ordered, bit EarlyClobber>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1, IdxClass:$rs2,
                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLX</*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSStoreNoMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/0, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSStoreMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/1, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSStoreNoMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/0, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSStoreMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
               (ins StClass:$rd, GPR:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/1, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Unary instruction that is never masked so HasDummyMask=0.
 class VPseudoUnaryNoDummyMask<VReg RetClass,
                               DAGOperand Op2Class> :
         Pseudo<(outs RetClass:$rd),
                (ins Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoNullaryNoMask<VReg RegClass>:
       Pseudo<(outs RegClass:$rd),
              (ins AVL:$vl, ixlenimm:$sew),
              []>, RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoNullaryMask<VReg RegClass>:
       Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
              (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
               ixlenimm:$sew), []>, RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints ="$rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Nullary for pseudo instructions. They are expanded in
 // RISCVExpandPseudoInsts pass.
 class VPseudoNullaryPseudoM<string BaseInst>
        : Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>,
        RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   // BaseInstr is not used in RISCVExpandPseudoInsts pass.
   // Just fill a corresponding real v-inst to pass tablegen check.
   let BaseInstr = !cast<Instruction>(BaseInst);
 }
 
 // RetClass could be GPR or VReg.
 class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
         Pseudo<(outs RetClass:$rd),
                (ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Constraint;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
                (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
                     VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // mask unary operation without maskedoff
 class VPseudoMaskUnarySOutMask:
         Pseudo<(outs GPR:$rd),
                (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Mask can be V0~V31
 class VPseudoUnaryAnyMask<VReg RetClass,
                           VReg Op1Class> :
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$merge,
                   Op1Class:$rs2,
                   VR:$vm, AVL:$vl, ixlenimm:$sew),
              []>,
       RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = "@earlyclobber $rd, $rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoBinaryNoMask<VReg RetClass,
                           VReg Op1Class,
                           DAGOperand Op2Class,
                           string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Constraint;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                           bit Ordered>:
       Pseudo<(outs),
               (ins StClass:$rd, GPR:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSX</*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoIStoreMask<VReg StClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                         bit Ordered>:
       Pseudo<(outs),
               (ins StClass:$rd, GPR:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSX</*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoBinaryMask<VReg RetClass,
                         RegisterClass Op1Class,
                         DAGOperand Op2Class,
                         string Constraint> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
                 (ins GetVRegNoV0<RetClass>.R:$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Like VPseudoBinaryMask, but output can be V0.
 class VPseudoBinaryMOutMask<VReg RetClass,
                             RegisterClass Op1Class,
                             DAGOperand Op2Class,
                             string Constraint> :
         Pseudo<(outs RetClass:$rd),
                 (ins RetClass:$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
                      VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoBinaryCarryIn<VReg RetClass,
                            VReg Op1Class,
                            DAGOperand Op2Class,
                            LMULInfo MInfo,
                            bit CarryIn,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
                !if(CarryIn,
                   (ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, AVL:$vl,
                        ixlenimm:$sew),
                   (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew)), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Constraint;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 0;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
   let VLMul = MInfo.value;
 }
 
 class VPseudoTernaryNoMask<VReg RetClass,
                            RegisterClass Op1Class,
                            DAGOperand Op2Class,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
                     AVL:$vl, ixlenimm:$sew),
                []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoAMOWDNoMask<VReg RetClass,
                          VReg Op1Class> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
                (ins GPR:$rs1,
                     Op1Class:$vs2,
                     GetVRegNoV0<RetClass>.R:$vd,
                     AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 1;
   let mayStore = 1;
   let hasSideEffects = 1;
-  let usesCustomInserter = 1;
   let Constraints = "$vd_wd = $vd";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoAMOWDMask<VReg RetClass,
                        VReg Op1Class> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
                (ins GPR:$rs1,
                     Op1Class:$vs2,
                     GetVRegNoV0<RetClass>.R:$vd,
                     VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 1;
   let mayStore = 1;
   let hasSideEffects = 1;
-  let usesCustomInserter = 1;
   let Constraints = "$vd_wd = $vd";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 multiclass VPseudoAMOEI<int eew> {
   // Standard scalar AMO supports 32, 64, and 128 Mem data bits,
   // and in the base vector "V" extension, only SEW up to ELEN = max(XLEN, FLEN)

 class VPseudoUSSegLoadNoMask<VReg RetClass, bits<7> EEW, bits<4> NF, bit isFF>:
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSSegLoadMask<VReg RetClass, bits<7> EEW, bits<4> NF, bit isFF>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
              (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegLoadNoMask<VReg RetClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegLoadMask<VReg RetClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
              (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
                   GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                             bits<4> NF, bit Ordered>:
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLXSEG<NF, /*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                           bits<4> NF, bit Ordered>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
              (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
                   IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLXSEG<NF, /*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd, $rd = $merge";
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSSegStoreNoMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSSegStoreMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegStoreNoMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, GPR: $offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegStoreMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, GPR: $offset,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                              bits<4> NF, bit Ordered>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, IdxClass: $index,
                   AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSXSEG<NF, /*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                            bits<4> NF, bit Ordered>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, IdxClass: $index,
                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSXSEG<NF, /*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
-  let usesCustomInserter = 1;
-  let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 multiclass VPseudoUSLoad<bit isFF> {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
let Defs = [VXSAT], hasSideEffects = 1 in {
   defm PseudoVSADD       : VPseudoBinaryV_VV_VX_VI;
   defm PseudoVSSUBU      : VPseudoBinaryV_VV_VX;
   defm PseudoVSSUB       : VPseudoBinaryV_VV_VX;
 }
 
 //===----------------------------------------------------------------------===//
 // 13.2. Vector Single-Width Averaging Add and Subtract
 //===----------------------------------------------------------------------===//
-let Uses = [VL, VTYPE, VXRM], hasSideEffects = 1 in {
+let Uses = [VXRM], hasSideEffects = 1 in {
   defm PseudoVAADDU      : VPseudoBinaryV_VV_VX;
   defm PseudoVAADD       : VPseudoBinaryV_VV_VX;
   defm PseudoVASUBU      : VPseudoBinaryV_VV_VX;
   defm PseudoVASUB       : VPseudoBinaryV_VV_VX;
 }
 
 //===----------------------------------------------------------------------===//
 // 13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
 //===----------------------------------------------------------------------===//
-let Uses = [VL, VTYPE, VXRM], Defs = [VXSAT], hasSideEffects = 1 in {
+let Uses = [VXRM], Defs = [VXSAT], hasSideEffects = 1 in {
   defm PseudoVSMUL      : VPseudoBinaryV_VV_VX;
 }
 
 //===----------------------------------------------------------------------===//
 // 13.4. Vector Single-Width Scaling Shift Instructions
 //===----------------------------------------------------------------------===//
-let Uses = [VL, VTYPE, VXRM], hasSideEffects = 1 in {
+let Uses = [VXRM], hasSideEffects = 1 in {
   defm PseudoVSSRL        : VPseudoBinaryV_VV_VX_VI<uimm5>;
   defm PseudoVSSRA        : VPseudoBinaryV_VV_VX_VI<uimm5>;
 }
 
 //===----------------------------------------------------------------------===//
 // 13.5. Vector Narrowing Fixed-Point Clip Instructions
 //===----------------------------------------------------------------------===//
-let Uses = [VL, VTYPE, VXRM], Defs = [VXSAT], hasSideEffects = 1 in {
+let Uses = [VXRM], Defs = [VXSAT], hasSideEffects = 1 in {
   defm PseudoVNCLIP     : VPseudoBinaryV_WV_WX_WI;
   defm PseudoVNCLIPU    : VPseudoBinaryV_WV_WX_WI;
 }
 
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtV, HasStdExtF] in {
 //===----------------------------------------------------------------------===//

 // 17. Vector Permutation Instructions
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // 17.1. Integer Scalar Move Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1,
-    Uses = [VL, VTYPE] in {
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
   foreach m = MxList.m in {
     let VLMul = m.value in {
       let HasSEWOp = 1, BaseInstr = VMV_X_S in
       def PseudoVMV_X_S # "_" # m.MX: Pseudo<(outs GPR:$rd),
                                              (ins m.vrclass:$rs2, ixlenimm:$sew),
                                              []>, RISCVVPseudo;
       let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
           ForceTailAgnostic = true, Constraints = "$rd = $rs1" in
       def PseudoVMV_S_X # "_" # m.MX: Pseudo<(outs m.vrclass:$rd),
                                              (ins m.vrclass:$rs1, GPR:$rs2,
                                                   AVL:$vl, ixlenimm:$sew),
                                              []>, RISCVVPseudo;
     }
   }
 }
 } // Predicates = [HasStdExtV]
 
 //===----------------------------------------------------------------------===//
 // 17.2. Floating-Point Scalar Move Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV, HasStdExtF] in {
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1,
-    Uses = [VL, VTYPE] in {
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
   foreach m = MxList.m in {
     foreach f = FPList.fpinfo in {
       let VLMul = m.value in {
         let HasSEWOp = 1, BaseInstr = VFMV_F_S in
         def "PseudoVFMV_" # f.FX # "_S_" # m.MX :
                                           Pseudo<(outs f.fprclass:$rd),
                                                  (ins m.vrclass:$rs2,
                                                       ixlenimm:$sew),

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
   auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
-  initializeRISCVCleanupVSETVLIPass(*PR);
+  initializeRISCVInsertVSETVLIPass(*PR);
 }
 
 static StringRef computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit())
     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
   return "e-m:e-p:32:32-i64:64-n32-S128";
 }
void RISCVPassConfig::addPreEmitPass2() {
   addPass(createRISCVExpandPseudoPass());
   // Schedule the expansion of AMOs at the last possible moment, avoiding the
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.
   addPass(createRISCVExpandAtomicPseudoPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
-  if (TM->getOptLevel() != CodeGenOpt::None) {
+  if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
-    addPass(createRISCVCleanupVSETVLIPass());
-  }
+  addPass(createRISCVInsertVSETVLIPass());
 }

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir

-# RUN: llc -mtriple riscv64 -mattr=+experimental-v %s  \
-# RUN:     -start-before=finalize-isel -stop-after=finalize-isel -o - \
-# RUN:     | FileCheck --check-prefix=POST-INSERTER %s
-
-# RUN: llc -mtriple riscv64 -mattr=+experimental-v %s  \
-# RUN:     -start-before=finalize-isel -o - \
-# RUN:     | FileCheck --check-prefix=CODEGEN %s
-
---- |
-  define void @vadd_vint64m1(
-            <vscale x 1 x i64> *%pc,
-            <vscale x 1 x i64> *%pa,
-            <vscale x 1 x i64> *%pb,
-            i64 %vl)
-  {
-    ret void
-  }
-...
----
-name: vadd_vint64m1
-tracksRegLiveness: true
-body:             |
-  bb.0 (%ir-block.0):
-    liveins: $x10, $x11, $x12, $x13
-
-    %3:gpr = COPY $x13
-    %2:gpr = COPY $x12
-    %1:gpr = COPY $x11
-    %0:gpr = COPY $x10
-    %4:vr = PseudoVLE64_V_M1 %1, %3, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
-    %5:vr = PseudoVLE64_V_M1 %2, %3, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-    %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, %3, 6, implicit $vl, implicit $vtype
-    PseudoVSE64_V_M1 killed %6, %0, %3, 6, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
-    PseudoRET
-
-...
-
-# POST-INSERTER: %0:gpr = COPY $x13
-# POST-INSERTER: %1:gpr = COPY $x12
-# POST-INSERTER: %2:gpr = COPY $x11
-# POST-INSERTER: %3:gpr = COPY $x10
-# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
-# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %1, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, $noreg, 6, implicit $vl, implicit $vtype
-# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
-# POST-INSERTER: PseudoVSE64_V_M1 killed %6, %3, $noreg, 6, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
-
-# CODEGEN: vsetvli  a3, a3, e64,m1,ta,mu
-# CODEGEN-NEXT: vle64.v v25, (a1)
-# CODEGEN-NEXT: vle64.v v26, (a2)
-# CODEGEN-NEXT: vadd.vv v25, v25, v26
-# CODEGEN-NEXT: vse64.v v25, (a0)
-# CODEGEN-NEXT: ret

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

-; This test shows the evolution of RVV pseudo instructions within isel.
-
-; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o %t.pre.mir \
-; RUN:     -stop-before=finalize-isel
-; RUN: cat %t.pre.mir | FileCheck --check-prefix=PRE-INSERTER %s
-
-; RUN: llc -mtriple riscv64 -mattr=+experimental-v %t.pre.mir -o %t.post.mir \
-; RUN:     -start-before=finalize-isel -stop-after=finalize-isel
-; RUN: cat %t.post.mir | FileCheck --check-prefix=POST-INSERTER %s
-
-define void @vadd_vint64m1(
-          <vscale x 1 x i64> *%pc,
-          <vscale x 1 x i64> *%pa,
-          <vscale x 1 x i64> *%pb)
-{
-  %va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa
-  %vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb
-  %vc = add <vscale x 1 x i64> %va, %vb
-  store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc
-  ret void
-}
-
-; PRE-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8)
-; PRE-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8)
-; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 6, implicit $vl, implicit $vtype
-; PRE-INSERTER:  VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8)
-
-; POST-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8)
-; POST-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8)
-; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
-; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, 6, implicit $vl, implicit $vtype
-; POST-INSERTER: VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8)

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -march=riscv64 -mattr=+experimental-v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
 
 --- |
   define void @add_scalable_offset(
             <vscale x 1 x i64> *%pa,
             i64 %vl)
   {
     ret void
   }
bb.0:
     ; CHECK: $x2 = ADD $x2, killed $x10
     ; CHECK: $x2 = frame-destroy ADDI $x2, 240
     ; CHECK: $x8 = LD $x2, 2016 :: (load 8 from %stack.4)
     ; CHECK: $x1 = LD $x2, 2024 :: (load 8 from %stack.3)
     ; CHECK: $x2 = frame-destroy ADDI $x2, 2032
     ; CHECK: PseudoRET
     %1:gpr = COPY $x11
     %0:gpr = COPY $x10
-    %2:vr = PseudoVLE64_V_M1 %0, %1, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+    %2:vr = PseudoVLE64_V_M1 %0, %1, 6 :: (load unknown-size from %ir.pa, align 8)
     %3:gpr = ADDI %stack.2, 0
     VS1R_V killed %2:vr, %3:gpr
     PseudoRET
 
 ...

llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir

-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-cleanup-vsetvli -o - | FileCheck %s
-
-# Make sure we don't combine these VSET{I}VLIs in the cleanup pass. We could not
-# differentiate AVL values if the opcode of the previous one is different from
-# current one.
-
---- |
-  ; ModuleID = '../llvm/test/CodeGen/RISCV/rvv/add-vsetivli.ll'
-  source_filename = "../llvm/test/CodeGen/RISCV/rvv/add-vsetivli.ll"
-  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
-  target triple = "riscv64"
-
-  define void @cleanup_vsetivli() #0 {
-    ret void
-  }
-
-  attributes #0 = { "target-features"="+experimental-v" }
-
-...
----
-name:            cleanup_vsetivli
-alignment:       4
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr }
-frameInfo:
-  maxAlignment:    1
-machineFunctionInfo: {}
-body:             |
-  bb.0 (%ir-block.0):
-    ; CHECK-LABEL: name: cleanup_vsetivli
-    ; CHECK: dead %0:gpr = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: dead %1:gpr = PseudoVSETIVLI 5, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: dead %3:gpr = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: dead %5:gpr = PseudoVSETIVLI 5, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: PseudoRET
-    dead %0:gpr  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    dead %1:gpr  = PseudoVSETIVLI 5, 12, implicit-def $vl, implicit-def $vtype
-    dead %2:gpr  = PseudoVSETIVLI 5, 12, implicit-def $vl, implicit-def $vtype
-    dead %3:gpr  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    dead %4:gpr  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    dead %5:gpr  = PseudoVSETIVLI 5, 12, implicit-def $vl, implicit-def $vtype
-    PseudoRET
-
-...

llvm/test/CodeGen/RISCV/rvv/cleanup-vsetvli.mir

-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-cleanup-vsetvli -o - | FileCheck %s
-
---- |
-  ; ModuleID = '../llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll'
-  source_filename = "../llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll"
-  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
-  target triple = "riscv64"
-
-  define void @cleanup_vsetvli0() #0 {
-    ret void
-  }
-
-  define void @cleanup_vsetvli1() #0 {
-    ret void
-  }
-
-  attributes #0 = { "target-features"="+experimental-v" }
-
-...
----
-# Make sure we don't combine these two VSETVLIs in the cleanup pass. The first
-# keeps the previous value of VL, the second sets it to VLMAX. We can't remove
-# the first since we can't tell if this is a change of VL.
-name:            cleanup_vsetvli0
-alignment:       4
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr }
-frameInfo:
-  maxAlignment:    1
-machineFunctionInfo: {}
-body:             |
-  bb.0 (%ir-block.0):
-    ; CHECK-LABEL: name: cleanup_vsetvli0
-    ; CHECK: dead $x0 = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: dead %0:gpr = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: PseudoRET
-    dead $x0  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    dead %0:gpr  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    PseudoRET
-
-...
----
-# 1. Ensure we can remove the second VSETVLI which takes its AVL from the first VSETVLI.
-# 2. Ensure we can remove the fourth VSETVLI which takes its AVL from the VSETIVLI.
-# 3. Make sure we don't combine the latter two VSETVLIs; the first outputs to a
-# physical register which is clobbered by a later instruction.
-name:            cleanup_vsetvli1
-alignment:       4
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr }
-frameInfo:
-  maxAlignment:    1
-machineFunctionInfo: {}
-body:             |
-  bb.0 (%ir-block.0):
-    liveins: $x3
-    ; CHECK-LABEL: name: cleanup_vsetvli1
-    ; CHECK: liveins: $x3
-    ; CHECK: [[PseudoVSETVLI:%[0-9]+]]:gpr = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: [[PseudoVSETIVLI:%[0-9]+]]:gpr = PseudoVSETIVLI 4, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: $x1 = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: $x1 = COPY $x3
-    ; CHECK: dead %4:gpr = PseudoVSETVLI $x1, 12, implicit-def $vl, implicit-def $vtype
-    ; CHECK: PseudoRET
-    %0:gpr  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    dead %1:gpr  = PseudoVSETVLI %0, 12, implicit-def $vl, implicit-def $vtype
-
-    %2:gpr  = PseudoVSETIVLI 4, 12, implicit-def $vl, implicit-def $vtype
-    dead %3:gpr  = PseudoVSETVLI %2, 12, implicit-def $vl, implicit-def $vtype
-
-    $x1  = PseudoVSETVLI $x0, 12, implicit-def $vl, implicit-def $vtype
-    $x1 = COPY $x3
-    dead %4:gpr  = PseudoVSETVLI $x1, 12, implicit-def $vl, implicit-def $vtype
-    PseudoRET
-
-...

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

 ; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
 ; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX2-RV32-NEXT:    lui a1, 4112
-; LMULMAX2-RV32-NEXT:    addi a2, a1, 257
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT:    lui a2, 4112
+; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
 ; LMULMAX2-RV32-NEXT:    bnez a5, .LBB3_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
+; LMULMAX2-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB3_3:
 ; LMULMAX2-RV32-NEXT:    sw a5, 0(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v25
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB3_5
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB3_5
 ; LMULMAX2-RV32-NEXT:  # %bb.4:
-; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX2-RV32-NEXT:    or a1, a5, a1
+; LMULMAX2-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a4, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a4
 ; LMULMAX2-RV32-NEXT:    and a4, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a4, a1
 ; LMULMAX2-RV32-NEXT:    srli a3, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB3_6
 ; LMULMAX2-RV32-NEXT:  .LBB3_5:
-; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX2-RV32-NEXT:    or a1, a1, a5
+; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX2-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 349525
 ; LMULMAX1-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX1-RV32-NEXT:    lui a1, 209715
 ; LMULMAX1-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX1-RV32-NEXT:    lui a1, 61681
 ; LMULMAX1-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX1-RV32-NEXT:    lui a1, 4112
-; LMULMAX1-RV32-NEXT:    addi a2, a1, 257
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    lui a2, 4112
+; LMULMAX1-RV32-NEXT:    addi a2, a2, 257
 ; LMULMAX1-RV32-NEXT:    bnez a5, .LBB3_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX1-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB3_3:
 ; LMULMAX1-RV32-NEXT:    sw a5, 0(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v25
-; LMULMAX1-RV32-NEXT:    bnez a1, .LBB3_5
+; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v26
+; LMULMAX1-RV32-NEXT:    bnez a5, .LBB3_5
 ; LMULMAX1-RV32-NEXT:  # %bb.4:
-; LMULMAX1-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX1-RV32-NEXT:    or a1, a5, a1
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    not a1, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a4, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    and a4, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    add a1, a4, a1
 ; LMULMAX1-RV32-NEXT:    srli a3, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB3_6
 ; LMULMAX1-RV32-NEXT:  .LBB3_5:
-; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX1-RV32-NEXT:    or a1, a1, a5
+; LMULMAX1-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX1-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
 ; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX2-RV32-NEXT:    lui a1, 4112
-; LMULMAX2-RV32-NEXT:    addi a2, a1, 257
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT:    lui a2, 4112
+; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
 ; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
+; LMULMAX2-RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB7_3:
 ; LMULMAX2-RV32-NEXT:    sw a5, 0(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v28, v26, 3
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v30, v28, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v30
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB7_5
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v30
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_5
 ; LMULMAX2-RV32-NEXT:  # %bb.4:
-; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX2-RV32-NEXT:    or a1, a5, a1
+; LMULMAX2-RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB7_6
 ; LMULMAX2-RV32-NEXT:  .LBB7_5:
-; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX2-RV32-NEXT:    or a1, a1, a5
+; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX2-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB7_6:
 ; LMULMAX2-RV32-NEXT:    sw a5, 24(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v28, v26, 2
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v30, v28, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v30
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB7_8
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v30
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_8
 ; LMULMAX2-RV32-NEXT:  # %bb.7:
-; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX2-RV32-NEXT:    or a1, a5, a1
+; LMULMAX2-RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB7_9
 ; LMULMAX2-RV32-NEXT:  .LBB7_8:
-; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX2-RV32-NEXT:    or a1, a1, a5
+; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX2-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB7_9:
 ; LMULMAX2-RV32-NEXT:    sw a5, 16(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v26, v26, 1
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB7_11
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_11
 ; LMULMAX2-RV32-NEXT:  # %bb.10:
-; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX2-RV32-NEXT:    or a1, a5, a1
+; LMULMAX2-RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a4, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a4
 ; LMULMAX2-RV32-NEXT:    and a4, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a4, a1
 ; LMULMAX2-RV32-NEXT:    srli a3, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB7_12
 ; LMULMAX2-RV32-NEXT:  .LBB7_11:
-; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX2-RV32-NEXT:    or a1, a1, a5
+; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX2-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v27
 ; LMULMAX1-RV32-NEXT:    lui a2, 349525
 ; LMULMAX1-RV32-NEXT:    addi a5, a2, 1365
 ; LMULMAX1-RV32-NEXT:    lui a2, 209715
 ; LMULMAX1-RV32-NEXT:    addi a4, a2, 819
 ; LMULMAX1-RV32-NEXT:    lui a2, 61681
 ; LMULMAX1-RV32-NEXT:    addi t0, a2, -241
-; LMULMAX1-RV32-NEXT:    lui a2, 4112
-; LMULMAX1-RV32-NEXT:    addi a3, a2, 257
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT:    lui a3, 4112
+; LMULMAX1-RV32-NEXT:    addi a3, a3, 257
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
-; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
-; LMULMAX1-RV32-NEXT:    or a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2

 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_3:
 ; LMULMAX1-RV32-NEXT:    sw a1, 16(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vslidedown.vi v26, v26, 1
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v27
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_5
 ; LMULMAX1-RV32-NEXT:  # %bb.4:
-; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
-; LMULMAX1-RV32-NEXT:    or a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2

 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_6:
 ; LMULMAX1-RV32-NEXT:    sw a1, 24(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a7
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v25
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_8
 ; LMULMAX1-RV32-NEXT:  # %bb.7:
-; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
-; LMULMAX1-RV32-NEXT:    or a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2

 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_9:
 ; LMULMAX1-RV32-NEXT:    sw a1, 0(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a7
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v25
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_11
 ; LMULMAX1-RV32-NEXT:  # %bb.10:
-; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
-; LMULMAX1-RV32-NEXT:    or a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX2-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX2-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 4(sp)
 ; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
 ; LMULMAX2-RV32-NEXT:    lui a2, 4112
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v25
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB3_2
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB3_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
-; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
-; LMULMAX2-RV32-NEXT:    not a5, a5
-; LMULMAX2-RV32-NEXT:    and a1, a5, a1
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
+; LMULMAX2-RV32-NEXT:    not a1, a1
+; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB3_3
 ; LMULMAX2-RV32-NEXT:  .LBB3_2:
-; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
-; LMULMAX2-RV32-NEXT:    not a1, a1
-; LMULMAX2-RV32-NEXT:    and a1, a1, a5
+; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
+; LMULMAX2-RV32-NEXT:    not a5, a5
+; LMULMAX2-RV32-NEXT:    and a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB3_3:
 ; LMULMAX2-RV32-NEXT:    sw a5, 0(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v25
-; LMULMAX2-RV32-NEXT:    vsrl.vx v25, v25, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX2-RV32-NEXT:    bnez a5, .LBB3_5
 ; LMULMAX2-RV32-NEXT:  # %bb.4:
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v25, v25, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a4, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a4
 ; LMULMAX2-RV32-NEXT:    and a4, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2

 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
 ; LMULMAX1-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 349525
 ; LMULMAX1-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX1-RV32-NEXT:    lui a1, 209715
 ; LMULMAX1-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX1-RV32-NEXT:    lui a1, 61681
 ; LMULMAX1-RV32-NEXT:    addi a7, a1, -241
 ; LMULMAX1-RV32-NEXT:    lui a2, 4112
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v25
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, 257
-; LMULMAX1-RV32-NEXT:    bnez a1, .LBB3_2
+; LMULMAX1-RV32-NEXT:    bnez a5, .LBB3_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
-; LMULMAX1-RV32-NEXT:    addi a1, a5, -1
-; LMULMAX1-RV32-NEXT:    not a5, a5
-; LMULMAX1-RV32-NEXT:    and a1, a5, a1
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    addi a5, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB3_3
 ; LMULMAX1-RV32-NEXT:  .LBB3_2:
-; LMULMAX1-RV32-NEXT:    addi a5, a1, -1
-; LMULMAX1-RV32-NEXT:    not a1, a1
-; LMULMAX1-RV32-NEXT:    and a1, a1, a5
+; LMULMAX1-RV32-NEXT:    addi a1, a5, -1
+; LMULMAX1-RV32-NEXT:    not a5, a5
+; LMULMAX1-RV32-NEXT:    and a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB3_3:
 ; LMULMAX1-RV32-NEXT:    sw a5, 0(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v25
-; LMULMAX1-RV32-NEXT:    vsrl.vx v25, v25, a6
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX1-RV32-NEXT:    bnez a5, .LBB3_5
 ; LMULMAX1-RV32-NEXT:  # %bb.4:
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v25, v25, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX1-RV32-NEXT:    addi a5, a1, -1
 ; LMULMAX1-RV32-NEXT:    not a1, a1
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a4, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    and a4, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2

 ; LMULMAX2-RV32-NEXT:    andi sp, sp, -32
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    sw zero, 28(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 20(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 4(sp)
 ; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
 ; LMULMAX2-RV32-NEXT:    lui a2, 4112
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB7_2
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
-; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
-; LMULMAX2-RV32-NEXT:    not a5, a5
-; LMULMAX2-RV32-NEXT:    and a1, a5, a1
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
+; LMULMAX2-RV32-NEXT:    not a1, a1
+; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB7_3
 ; LMULMAX2-RV32-NEXT:  .LBB7_2:
-; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
-; LMULMAX2-RV32-NEXT:    not a1, a1
-; LMULMAX2-RV32-NEXT:    and a1, a1, a5
+; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
+; LMULMAX2-RV32-NEXT:    not a5, a5
+; LMULMAX2-RV32-NEXT:    and a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB7_3:
 ; LMULMAX2-RV32-NEXT:    sw a5, 0(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v28, v26, 3
 ; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
-; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v28, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
 ; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_5
 ; LMULMAX2-RV32-NEXT:  # %bb.4:
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v28, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2

 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB7_6:
 ; LMULMAX2-RV32-NEXT:    sw a5, 24(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v28, v26, 2
 ; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
-; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v28, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
 ; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_8
 ; LMULMAX2-RV32-NEXT:  # %bb.7:
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v28, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2

 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 24
 ; LMULMAX2-RV32-NEXT:  .LBB7_9:
 ; LMULMAX2-RV32-NEXT:    sw a5, 16(sp)
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vslidedown.vi v26, v26, 1
 ; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
-; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v26, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
 ; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_11
 ; LMULMAX2-RV32-NEXT:  # %bb.10:
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v26, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a4, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a4
 ; LMULMAX2-RV32-NEXT:    and a4, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2

 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: cttz_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -32
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 32
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
-; LMULMAX1-RV32-NEXT:    addi a6, a0, 16
-; LMULMAX1-RV32-NEXT:    vle64.v v26, (a6)
+; LMULMAX1-RV32-NEXT:    addi a7, a0, 16
+; LMULMAX1-RV32-NEXT:    vle64.v v26, (a7)
 ; LMULMAX1-RV32-NEXT:    sw zero, 28(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 20(sp)
-; LMULMAX1-RV32-NEXT:    addi a7, zero, 32
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v27
-; LMULMAX1-RV32-NEXT:    lui a2, 349525
-; LMULMAX1-RV32-NEXT:    addi a5, a2, 1365
-; LMULMAX1-RV32-NEXT:    lui a2, 209715
-; LMULMAX1-RV32-NEXT:    addi a4, a2, 819
-; LMULMAX1-RV32-NEXT:    lui a2, 61681
-; LMULMAX1-RV32-NEXT:    addi t0, a2, -241
+; LMULMAX1-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX1-RV32-NEXT:    lui a1, 349525
+; LMULMAX1-RV32-NEXT:    addi a5, a1, 1365
+; LMULMAX1-RV32-NEXT:    lui a1, 209715
+; LMULMAX1-RV32-NEXT:    addi a4, a1, 819
+; LMULMAX1-RV32-NEXT:    lui a1, 61681
+; LMULMAX1-RV32-NEXT:    addi t0, a1, -241
 ; LMULMAX1-RV32-NEXT:    lui a3, 4112
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
 ; LMULMAX1-RV32-NEXT:    addi a3, a3, 257
-; LMULMAX1-RV32-NEXT:    bnez a2, .LBB7_2
+; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v27
 ; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
 ; LMULMAX1-RV32-NEXT:    not a1, a1
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB7_3
 ; LMULMAX1-RV32-NEXT:  .LBB7_2:
-; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
-; LMULMAX1-RV32-NEXT:    not a2, a2
-; LMULMAX1-RV32-NEXT:    and a1, a2, a1
+; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_3:
 ; LMULMAX1-RV32-NEXT:    sw a1, 16(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vslidedown.vi v26, v26, 1
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v26, a7
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_5
 ; LMULMAX1-RV32-NEXT:  # %bb.4:
-; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
-; LMULMAX1-RV32-NEXT:    not a2, a2
-; LMULMAX1-RV32-NEXT:    and a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v26, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4

 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_6:
 ; LMULMAX1-RV32-NEXT:    sw a1, 24(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a7
+; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_8
 ; LMULMAX1-RV32-NEXT:  # %bb.7:
-; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
-; LMULMAX1-RV32-NEXT:    not a2, a2
-; LMULMAX1-RV32-NEXT:    and a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4

 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_9:
 ; LMULMAX1-RV32-NEXT:    sw a1, 0(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vslidedown.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
-; LMULMAX1-RV32-NEXT:    vsrl.vx v25, v25, a7
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v25
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_11
 ; LMULMAX1-RV32-NEXT:  # %bb.10:
-; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
-; LMULMAX1-RV32-NEXT:    not a2, a2
-; LMULMAX1-RV32-NEXT:    and a1, a2, a1
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v25, v25, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4

 ; LMULMAX1-RV32-NEXT:  .LBB7_12:
 ; LMULMAX1-RV32-NEXT:    sw a1, 8(sp)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle32.v v25, (sp)
 ; LMULMAX1-RV32-NEXT:    addi a1, sp, 16
 ; LMULMAX1-RV32-NEXT:    vle32.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT:    vse64.v v26, (a6)
+; LMULMAX1-RV32-NEXT:    vse64.v v26, (a7)
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, 32
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: cttz_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    addi a6, a0, 16
 ; LMULMAX1-RV64-NEXT:    vle64.v v26, (a6)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

 ; CHECK-LABEL: vreduce_ord_fadd_v1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x half>, <1 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
 
 define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
 
 define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)

 ; CHECK-LABEL: vreduce_fadd_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <16 x half>, <16 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v16f16(<16 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x half>, <16 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
 
 define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <32 x half>, <32 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x half>, <32 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
 
 define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v64f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <64 x half>, <64 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v64f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x half>, <64 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.v128f16(half, <128 x half>)
 
 define half @vreduce_fadd_v128f16(<128 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_fadd_v128f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vfadd.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <128 x half>, <128 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_v128f16(<128 x half>* %x, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v128f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, a0, 128
 ; CHECK-NEXT:    addi a2, zero, 64
 ; CHECK-NEXT:    vsetvli a3, a2, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a1)
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v16, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x half>, <128 x half>* %x
   %red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)

 ; CHECK-LABEL: vreduce_ord_fadd_v1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <1 x float>, <1 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
 
 define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)

 ; CHECK-LABEL: vreduce_fadd_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <8 x float>, <8 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v8f32(<8 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x float>, <8 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>)
 
 define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <16 x float>, <16 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v16f32(<16 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x float>, <16 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
 
 define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <32 x float>, <32 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x float>, <32 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.v64f32(float, <64 x float>)
 
 define float @vreduce_fadd_v64f32(<64 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_fadd_v64f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vfadd.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <64 x float>, <64 x float>* %x
   %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_v64f32(<64 x float>* %x, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v64f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, a0, 128
 ; CHECK-NEXT:    addi a2, zero, 32
 ; CHECK-NEXT:    vsetvli a3, a2, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a1)
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v16, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x float>, <64 x float>* %x
   %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>)

 ; CHECK-LABEL: vreduce_fadd_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.d fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v4f64(<4 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>)
 
 define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_fadd_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.d fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <8 x double>, <8 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v8f64(<8 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vle64.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x double>, <8 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>)
 
 define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_fadd_v16f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.d fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <16 x double>, <16 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v16f64(<16 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v16f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x double>, <16 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.v32f64(double, <32 x double>)
 
 define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_fadd_v32f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle64.v v16, (a0)
 ; CHECK-NEXT:    vfadd.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.d fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %v = load <32 x double>, <32 x double>* %x
   %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_v32f64(<32 x double>* %x, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_v32f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, a0, 128
 ; CHECK-NEXT:    vsetivli a2, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vle64.v v8, (a1)
 ; CHECK-NEXT:    vle64.v v16, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v16, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x double>, <32 x double>* %x
   %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
   ret double %red
 }
 
 declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)
 
 define half @vreduce_fmin_v2f16(<2 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI42_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI42_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
 
 define half @vreduce_fmin_v4f16(<4 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI43_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI43_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmin_v4f16_nonans(<4 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v4f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI44_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI44_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmin_v4f16_nonans_noinfs(<4 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI45_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI45_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmin.v128f16(<128 x half>)
 
 define half @vreduce_fmin_v128f16(<128 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v128f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    lui a0, %hi(.LCPI46_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI46_0)(a0)
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x half>, <128 x half>* %x
   %red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
 
 define float @vreduce_fmin_v2f32(<2 x float>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI47_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI47_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)

 ; CHECK-NEXT:    lui a0, %hi(.LCPI51_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI51_0)(a0)
 ; CHECK-NEXT:    vfmin.vv v16, v24, v0
 ; CHECK-NEXT:    vfmin.vv v8, v16, v8
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x float>, <128 x float>* %x
   %red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)

 ; CHECK-NEXT:    lui a1, %hi(.LCPI53_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI53_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fmin_v4f64_nonans(<4 x double>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI54_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI54_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fmin_v4f64_nonans_noinfs(<4 x double>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v4f64_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI55_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI55_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fmin.v32f64(<32 x double>)
 
 define double @vreduce_fmin_v32f64(<32 x double>* %x) {
 ; CHECK-LABEL: vreduce_fmin_v32f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle64.v v16, (a0)
 ; CHECK-NEXT:    lui a0, %hi(.LCPI56_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI56_0)(a0)
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x double>, <32 x double>* %x
   %red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v)
   ret double %red
 }
 
 declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)
 
 define half @vreduce_fmax_v2f16(<2 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI57_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI57_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x half>, <2 x half>* %x
   %red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
 
 define half @vreduce_fmax_v4f16(<4 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI58_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI58_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmax_v4f16_nonans(<4 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v4f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI59_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI59_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmax_v4f16_nonans_noinfs(<4 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI60_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI60_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x half>, <4 x half>* %x
   %red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmax.v128f16(<128 x half>)
 
 define half @vreduce_fmax_v128f16(<128 x half>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v128f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    lui a0, %hi(.LCPI61_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI61_0)(a0)
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x half>, <128 x half>* %x
   %red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
 
 define float @vreduce_fmax_v2f32(<2 x float>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI62_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI62_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v26, ft0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x float>, <2 x float>* %x
   %red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)

 ; CHECK-NEXT:    lui a0, %hi(.LCPI66_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI66_0)(a0)
 ; CHECK-NEXT:    vfmax.vv v16, v24, v0
 ; CHECK-NEXT:    vfmax.vv v8, v16, v8
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x float>, <128 x float>* %x
   %red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)

 ; CHECK-NEXT:    lui a1, %hi(.LCPI68_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI68_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fmax_v4f64_nonans(<4 x double>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v4f64_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI69_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI69_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_fmax_v4f64_nonans_noinfs(<4 x double>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v4f64_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, %hi(.LCPI70_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI70_0)(a1)
 ; CHECK-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vle64.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x double>, <4 x double>* %x
   %red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fmax.v32f64(<32 x double>)
 
 define double @vreduce_fmax_v32f64(<32 x double>* %x) {
 ; CHECK-LABEL: vreduce_fmax_v32f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle64.v v16, (a0)
 ; CHECK-NEXT:    lui a0, %hi(.LCPI71_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI71_0)(a0)
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x double>, <32 x double>* %x
   %red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v)
   ret double %red
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

 ; CHECK-LABEL: vreduce_add_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
 
 define i8 @vreduce_add_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
 
 define i8 @vreduce_add_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8>)
 
 define i8 @vreduce_add_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v128i8(<128 x i8>)
 
 define i8 @vreduce_add_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.v256i8(<256 x i8>)
 
 define i8 @vreduce_add_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_add_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v1i16(<1 x i16>)

 ; CHECK-LABEL: vreduce_add_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
 
 define i16 @vreduce_add_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)

 ; CHECK-LABEL: vreduce_add_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v32i16(<32 x i16>)
 
 define i16 @vreduce_add_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v64i16(<64 x i16>)
 
 define i16 @vreduce_add_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.v128i16(<128 x i16>)
 
 define i16 @vreduce_add_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_add_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32>)

 ; CHECK-LABEL: vreduce_add_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)

 ; CHECK-LABEL: vreduce_add_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
 
 define i32 @vreduce_add_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_add_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>)
 
 define i32 @vreduce_add_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_add_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.v64i32(<64 x i32>)
 
 define i32 @vreduce_add_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_add_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>)

 ; RV32-LABEL: vreduce_add_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredsum.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_add_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredsum.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
 
 define i64 @vreduce_add_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_add_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredsum.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_add_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredsum.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
 
 define i64 @vreduce_add_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_add_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredsum.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_add_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredsum.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.v32i64(<32 x i64>)
 
 define i64 @vreduce_add_v32i64(<32 x i64>* %x) {
 ; RV32-LABEL: vreduce_add_v32i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle64.v v16, (a0)
 ; RV32-NEXT:    vadd.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredsum.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_add_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vadd.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredsum.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.v64i64(<64 x i64>)

 ; RV32-NEXT:    vle64.v v0, (a1)
 ; RV32-NEXT:    vadd.vv v16, v24, v16
 ; RV32-NEXT:    vadd.vv v8, v8, v0
 ; RV32-NEXT:    vadd.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredsum.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_add_v64i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a1, a0, 384
 ; RV64-NEXT:    vle64.v v16, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vadd.vv v16, v24, v16
 ; RV64-NEXT:    vadd.vv v8, v8, v0
 ; RV64-NEXT:    vadd.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredsum.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.add.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)

 ; CHECK-LABEL: vreduce_and_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
 
 define i8 @vreduce_and_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
 
 define i8 @vreduce_and_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v64i8(<64 x i8>)
 
 define i8 @vreduce_and_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v128i8(<128 x i8>)
 
 define i8 @vreduce_and_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.v256i8(<256 x i8>)
 
 define i8 @vreduce_and_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_and_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vand.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16>)

 ; CHECK-LABEL: vreduce_and_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
 
 define i16 @vreduce_and_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)

 ; CHECK-LABEL: vreduce_and_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v32i16(<32 x i16>)
 
 define i16 @vreduce_and_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v64i16(<64 x i16>)
 
 define i16 @vreduce_and_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.v128i16(<128 x i16>)
 
 define i16 @vreduce_and_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_and_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vand.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32>)

 ; CHECK-LABEL: vreduce_and_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)

 ; CHECK-LABEL: vreduce_and_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)
 
 define i32 @vreduce_and_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_and_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v32i32(<32 x i32>)
 
 define i32 @vreduce_and_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_and_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.v64i32(<64 x i32>)
 
 define i32 @vreduce_and_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_and_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vand.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)

 ; RV32-LABEL: vreduce_and_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredand.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_and_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredand.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)
 
 define i64 @vreduce_and_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_and_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredand.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_and_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredand.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)
 
 define i64 @vreduce_and_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_and_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredand.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_and_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredand.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.v32i64(<32 x i64>)
 
 define i64 @vreduce_and_v32i64(<32 x i64>* %x) {
 ; RV32-LABEL: vreduce_and_v32i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle64.v v16, (a0)
 ; RV32-NEXT:    vand.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredand.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_and_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vand.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredand.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.v64i64(<64 x i64>)

 ; RV32-NEXT:    vle64.v v0, (a1)
 ; RV32-NEXT:    vand.vv v16, v24, v16
 ; RV32-NEXT:    vand.vv v8, v8, v0
 ; RV32-NEXT:    vand.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredand.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_and_v64i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a1, a0, 384
 ; RV64-NEXT:    vle64.v v16, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vand.vv v16, v24, v16
 ; RV64-NEXT:    vand.vv v8, v8, v0
 ; RV64-NEXT:    vand.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredand.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.and.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)

 ; CHECK-LABEL: vreduce_or_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
 
 define i8 @vreduce_or_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
 
 define i8 @vreduce_or_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>)
 
 define i8 @vreduce_or_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v128i8(<128 x i8>)
 
 define i8 @vreduce_or_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.v256i8(<256 x i8>)
 
 define i8 @vreduce_or_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_or_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vor.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v1i16(<1 x i16>)

 ; CHECK-LABEL: vreduce_or_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
 
 define i16 @vreduce_or_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)

 ; CHECK-LABEL: vreduce_or_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v32i16(<32 x i16>)
 
 define i16 @vreduce_or_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v64i16(<64 x i16>)
 
 define i16 @vreduce_or_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.v128i16(<128 x i16>)
 
 define i16 @vreduce_or_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_or_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vor.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v1i32(<1 x i32>)

 ; CHECK-LABEL: vreduce_or_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)

 ; CHECK-LABEL: vreduce_or_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>)
 
 define i32 @vreduce_or_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_or_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v32i32(<32 x i32>)
 
 define i32 @vreduce_or_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_or_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.v64i32(<64 x i32>)
 
 define i32 @vreduce_or_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_or_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vor.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)

 ; RV32-LABEL: vreduce_or_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredor.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_or_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredor.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>)
 
 define i64 @vreduce_or_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_or_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredor.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_or_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredor.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>)
 
 define i64 @vreduce_or_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_or_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredor.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_or_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredor.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.v32i64(<32 x i64>)
 
 define i64 @vreduce_or_v32i64(<32 x i64>* %x) {
 ; RV32-LABEL: vreduce_or_v32i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle64.v v16, (a0)
 ; RV32-NEXT:    vor.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredor.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_or_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vor.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredor.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.v64i64(<64 x i64>)

 ; RV32-NEXT:    vle64.v v0, (a1)
 ; RV32-NEXT:    vor.vv v16, v24, v16
 ; RV32-NEXT:    vor.vv v8, v8, v0
 ; RV32-NEXT:    vor.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredor.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_or_v64i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a1, a0, 384
 ; RV64-NEXT:    vle64.v v16, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vor.vv v16, v24, v16
 ; RV64-NEXT:    vor.vv v8, v8, v0
 ; RV64-NEXT:    vor.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredor.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.or.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v1i8(<1 x i8>)

 ; CHECK-LABEL: vreduce_xor_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
 
 define i8 @vreduce_xor_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
 
 define i8 @vreduce_xor_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v64i8(<64 x i8>)
 
 define i8 @vreduce_xor_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v128i8(<128 x i8>)
 
 define i8 @vreduce_xor_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.v256i8(<256 x i8>)
 
 define i8 @vreduce_xor_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_xor_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vxor.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v1i16(<1 x i16>)

 ; CHECK-LABEL: vreduce_xor_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
 
 define i16 @vreduce_xor_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)

 ; CHECK-LABEL: vreduce_xor_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v32i16(<32 x i16>)
 
 define i16 @vreduce_xor_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v64i16(<64 x i16>)
 
 define i16 @vreduce_xor_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.v128i16(<128 x i16>)
 
 define i16 @vreduce_xor_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_xor_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vxor.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v1i32(<1 x i32>)

 ; CHECK-LABEL: vreduce_xor_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)

 ; CHECK-LABEL: vreduce_xor_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)
 
 define i32 @vreduce_xor_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_xor_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v32i32(<32 x i32>)
 
 define i32 @vreduce_xor_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_xor_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.v64i32(<64 x i32>)
 
 define i32 @vreduce_xor_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_xor_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vxor.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)

 ; RV32-LABEL: vreduce_xor_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredxor.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_xor_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredxor.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)
 
 define i64 @vreduce_xor_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_xor_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredxor.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_xor_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredxor.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)
 
 define i64 @vreduce_xor_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_xor_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredxor.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_xor_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredxor.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.v32i64(<32 x i64>)
 
 define i64 @vreduce_xor_v32i64(<32 x i64>* %x) {
 ; RV32-LABEL: vreduce_xor_v32i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle64.v v16, (a0)
 ; RV32-NEXT:    vxor.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredxor.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_xor_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vxor.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredxor.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.v64i64(<64 x i64>)

 ; RV32-NEXT:    vle64.v v0, (a1)
 ; RV32-NEXT:    vxor.vv v16, v24, v16
 ; RV32-NEXT:    vxor.vv v8, v8, v0
 ; RV32-NEXT:    vxor.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredxor.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_xor_v64i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a1, a0, 384
 ; RV64-NEXT:    vle64.v v16, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vxor.vv v16, v24, v16
 ; RV64-NEXT:    vxor.vv v8, v8, v0
 ; RV64-NEXT:    vxor.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredxor.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.xor.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v1i8(<1 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
 
 define i8 @vreduce_smin_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
 
 define i8 @vreduce_smin_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)

 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v64i8(<64 x i8>)
 
 define i8 @vreduce_smin_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v128i8(<128 x i8>)
 
 define i8 @vreduce_smin_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.v256i8(<256 x i8>)
 
 define i8 @vreduce_smin_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smin_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vmin.vv v8, v8, v16
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v1i16(<1 x i16>)

 ; RV32-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a0
 ; RV32-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v25, v26
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vle16.v v25, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
 ; RV64-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)
 
 define i16 @vreduce_smin_v4i16(<4 x i16>* %x) {
 ; RV32-LABEL: vreduce_smin_v4i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a0
 ; RV32-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v25, v26
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v4i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; RV64-NEXT:    vle16.v v25, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
 ; RV64-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)

 ; RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; RV32-NEXT:    vle16.v v26, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v16i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; RV64-NEXT:    vle16.v v26, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v32i16(<32 x i16>)
 
 define i16 @vreduce_smin_v32i16(<32 x i16>* %x) {
 ; RV32-LABEL: vreduce_smin_v32i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; RV32-NEXT:    vle16.v v28, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v32i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 32
 ; RV64-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; RV64-NEXT:    vle16.v v28, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v64i16(<64 x i16>)
 
 define i16 @vreduce_smin_v64i16(<64 x i16>* %x) {
 ; RV32-LABEL: vreduce_smin_v64i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 64
 ; RV32-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; RV32-NEXT:    vle16.v v8, (a0)
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v64i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 64
 ; RV64-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; RV64-NEXT:    vle16.v v8, (a0)
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.v128i16(<128 x i16>)
 
 define i16 @vreduce_smin_v128i16(<128 x i16>* %x) {
 ; RV32-LABEL: vreduce_smin_v128i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 64
 ; RV32-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; RV32-NEXT:    vle16.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle16.v v16, (a0)
 ; RV32-NEXT:    vmin.vv v8, v8, v16
 ; RV32-NEXT:    lui a0, 8
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v128i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 64
 ; RV64-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; RV64-NEXT:    vle16.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle16.v v16, (a0)
 ; RV64-NEXT:    vmin.vv v8, v8, v16
 ; RV64-NEXT:    lui a0, 8
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v1i32(<1 x i32>)

 ; RV32-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vle32.v v25, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a0
 ; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v25, v26
-; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vle32.v v25, (a0)
 ; RV64-NEXT:    lui a0, 524288
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
 ; RV64-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
-; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)

 ; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v26, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v8i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV64-NEXT:    vle32.v v26, (a0)
 ; RV64-NEXT:    lui a0, 524288
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
 
 define i32 @vreduce_smin_v16i32(<16 x i32>* %x) {
 ; RV32-LABEL: vreduce_smin_v16i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; RV32-NEXT:    vle32.v v28, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v16i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; RV64-NEXT:    vle32.v v28, (a0)
 ; RV64-NEXT:    lui a0, 524288
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v32i32(<32 x i32>)
 
 define i32 @vreduce_smin_v32i32(<32 x i32>* %x) {
 ; RV32-LABEL: vreduce_smin_v32i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; RV32-NEXT:    vle32.v v8, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v32i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 32
 ; RV64-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; RV64-NEXT:    vle32.v v8, (a0)
 ; RV64-NEXT:    lui a0, 524288
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.v64i32(<64 x i32>)
 
 define i32 @vreduce_smin_v64i32(<64 x i32>* %x) {
 ; RV32-LABEL: vreduce_smin_v64i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; RV32-NEXT:    vle32.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle32.v v16, (a0)
 ; RV32-NEXT:    vmin.vv v8, v8, v16
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v25, a0
 ; RV32-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v64i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 32
 ; RV64-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; RV64-NEXT:    vle32.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle32.v v16, (a0)
 ; RV64-NEXT:    vmin.vv v8, v8, v16
 ; RV64-NEXT:    lui a0, 524288
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)

 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)

 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.v16i64(<16 x i64>)

 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.v32i64(<32 x i64>)

 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    vmin.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vmin.vv v8, v8, v16
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.v64i64(<64 x i64>)

 ; RV32-NEXT:    vmin.vv v24, v0, v24
 ; RV32-NEXT:    vmin.vv v8, v8, v16
 ; RV32-NEXT:    vmin.vv v8, v8, v24
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmin.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;

 ; RV64-NEXT:    vmin.vv v8, v8, v0
 ; RV64-NEXT:    vmin.vv v8, v8, v16
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smin.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v1i8(<1 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
 
 define i8 @vreduce_smax_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
 
 define i8 @vreduce_smax_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)

 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v64i8(<64 x i8>)
 
 define i8 @vreduce_smax_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v128i8(<128 x i8>)
 
 define i8 @vreduce_smax_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.v256i8(<256 x i8>)
 
 define i8 @vreduce_smax_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_smax_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vmax.vv v8, v8, v16
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v1i16(<1 x i16>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)
 
 define i16 @vreduce_smax_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v32i16(<32 x i16>)
 
 define i16 @vreduce_smax_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v64i16(<64 x i16>)
 
 define i16 @vreduce_smax_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.v128i16(<128 x i16>)
 
 define i16 @vreduce_smax_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_smax_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vmax.vv v8, v8, v16
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v1i32(<1 x i32>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
 
 define i32 @vreduce_smax_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_smax_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v32i32(<32 x i32>)
 
 define i32 @vreduce_smax_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_smax_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.v64i32(<64 x i32>)
 
 define i32 @vreduce_smax_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_smax_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vmax.vv v8, v8, v16
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)

 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    sw zero, 8(sp)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredmax.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smax_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    slli a0, a0, 63
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredmax.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)
 
 define i64 @vreduce_smax_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_smax_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    sw zero, 8(sp)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredmax.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smax_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    slli a0, a0, 63
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredmax.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>)
 
 define i64 @vreduce_smax_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_smax_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    sw zero, 8(sp)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmax.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smax_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    slli a0, a0, 63
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmax.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.v32i64(<32 x i64>)

 ; RV32-NEXT:    sw a0, 12(sp)
 ; RV32-NEXT:    sw zero, 8(sp)
 ; RV32-NEXT:    vmax.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmax.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smax_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vmax.vv v8, v8, v16
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    slli a0, a0, 63
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmax.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.v64i64(<64 x i64>)

 ; RV32-NEXT:    vmax.vv v24, v0, v24
 ; RV32-NEXT:    vmax.vv v8, v8, v16
 ; RV32-NEXT:    vmax.vv v8, v8, v24
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v25, (a0), zero
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmax.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;

 ; RV64-NEXT:    vmax.vv v8, v8, v0
 ; RV64-NEXT:    vmax.vv v8, v8, v16
 ; RV64-NEXT:    addi a0, zero, -1
 ; RV64-NEXT:    slli a0, a0, 63
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmax.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smax.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v1i8(<1 x i8>)

 ; CHECK-LABEL: vreduce_umin_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
 
 define i8 @vreduce_umin_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
 
 define i8 @vreduce_umin_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v64i8(<64 x i8>)
 
 define i8 @vreduce_umin_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v128i8(<128 x i8>)
 
 define i8 @vreduce_umin_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.v256i8(<256 x i8>)
 
 define i8 @vreduce_umin_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umin_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vminu.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v1i16(<1 x i16>)

 ; CHECK-LABEL: vreduce_umin_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)
 
 define i16 @vreduce_umin_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)

 ; CHECK-LABEL: vreduce_umin_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v32i16(<32 x i16>)
 
 define i16 @vreduce_umin_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v64i16(<64 x i16>)
 
 define i16 @vreduce_umin_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.v128i16(<128 x i16>)
 
 define i16 @vreduce_umin_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umin_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vminu.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v1i32(<1 x i32>)

 ; CHECK-LABEL: vreduce_umin_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, -1
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)

 ; CHECK-LABEL: vreduce_umin_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
 
 define i32 @vreduce_umin_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umin_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v32i32(<32 x i32>)
 
 define i32 @vreduce_umin_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umin_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.v64i32(<64 x i32>)
 
 define i32 @vreduce_umin_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umin_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vminu.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)

 ; RV32-LABEL: vreduce_umin_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredminu.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umin_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredminu.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
 
 define i64 @vreduce_umin_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_umin_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredminu.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umin_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredminu.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.v16i64(<16 x i64>)
 
 define i64 @vreduce_umin_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_umin_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredminu.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umin_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredminu.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.v32i64(<32 x i64>)
 
 define i64 @vreduce_umin_v32i64(<32 x i64>* %x) {
 ; RV32-LABEL: vreduce_umin_v32i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle64.v v16, (a0)
 ; RV32-NEXT:    vminu.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredminu.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umin_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vminu.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredminu.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.v64i64(<64 x i64>)

 ; RV32-NEXT:    vle64.v v0, (a1)
 ; RV32-NEXT:    vminu.vv v16, v24, v16
 ; RV32-NEXT:    vminu.vv v8, v8, v0
 ; RV32-NEXT:    vminu.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, -1
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredminu.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umin_v64i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a1, a0, 384
 ; RV64-NEXT:    vle64.v v16, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vminu.vv v16, v24, v16
 ; RV64-NEXT:    vminu.vv v8, v8, v0
 ; RV64-NEXT:    vminu.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, -1
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredminu.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umin.v64i64(<64 x i64> %v)
   ret i64 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8>)

 ; CHECK-LABEL: vreduce_umax_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, <2 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
 
 define i8 @vreduce_umax_v4i8(<4 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i8>, <4 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
 
 define i8 @vreduce_umax_v8i8(<8 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle8.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i8>, <8 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vle8.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i8>, <32 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v64i8(<64 x i8>)
 
 define i8 @vreduce_umax_v64i8(<64 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v64i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vle8.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i8>, <64 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v128i8(<128 x i8>)
 
 define i8 @vreduce_umax_v128i8(<128 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v128i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i8>, <128 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.v256i8(<256 x i8>)
 
 define i8 @vreduce_umax_v256i8(<256 x i8>* %x) {
 ; CHECK-LABEL: vreduce_umax_v256i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 128
 ; CHECK-NEXT:    vsetvli a2, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle8.v v16, (a0)
 ; CHECK-NEXT:    vmaxu.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <256 x i8>, <256 x i8>* %x
   %red = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v1i16(<1 x i16>)

 ; CHECK-LABEL: vreduce_umax_v2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i16>, <2 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)
 
 define i16 @vreduce_umax_v4i16(<4 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, <4 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)

 ; CHECK-LABEL: vreduce_umax_v16i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vle16.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i16>, <16 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v32i16(<32 x i16>)
 
 define i16 @vreduce_umax_v32i16(<32 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v32i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vle16.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i16>, <32 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v64i16(<64 x i16>)
 
 define i16 @vreduce_umax_v64i16(<64 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v64i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i16>, <64 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.v128i16(<128 x i16>)
 
 define i16 @vreduce_umax_v128i16(<128 x i16>* %x) {
 ; CHECK-LABEL: vreduce_umax_v128i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 64
 ; CHECK-NEXT:    vsetvli a2, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle16.v v16, (a0)
 ; CHECK-NEXT:    vmaxu.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <128 x i16>, <128 x i16>* %x
   %red = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %v)
   ret i16 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32>)

 ; CHECK-LABEL: vreduce_umax_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vle32.v v25, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v25, v26
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <2 x i32>, <2 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)

 ; CHECK-LABEL: vreduce_umax_v8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vle32.v v26, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v26, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <8 x i32>, <8 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
 
 define i32 @vreduce_umax_v16i32(<16 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umax_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vle32.v v28, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v28, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <16 x i32>, <16 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v32i32(<32 x i32>)
 
 define i32 @vreduce_umax_v32i32(<32 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umax_v32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <32 x i32>, <32 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.v64i32(<64 x i32>)
 
 define i32 @vreduce_umax_v64i32(<64 x i32>* %x) {
 ; CHECK-LABEL: vreduce_umax_v64i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetvli a2, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    addi a0, a0, 128
 ; CHECK-NEXT:    vle32.v v16, (a0)
 ; CHECK-NEXT:    vmaxu.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %v = load <64 x i32>, <64 x i32>* %x
   %red = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)

 ; RV32-LABEL: vreduce_umax_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vredmaxu.vs v25, v26, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umax_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredmaxu.vs v25, v26, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
 
 define i64 @vreduce_umax_v8i64(<8 x i64>* %x) {
 ; RV32-LABEL: vreduce_umax_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v28, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vredmaxu.vs v25, v28, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umax_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredmaxu.vs v25, v28, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>)
 
 define i64 @vreduce_umax_v16i64(<16 x i64>* %x) {
 ; RV32-LABEL: vreduce_umax_v16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmaxu.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umax_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmaxu.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.v32i64(<32 x i64>)
 
 define i64 @vreduce_umax_v32i64(<32 x i64>* %x) {
 ; RV32-LABEL: vreduce_umax_v32i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    addi a0, a0, 128
 ; RV32-NEXT:    vle64.v v16, (a0)
 ; RV32-NEXT:    vmaxu.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmaxu.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umax_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vmaxu.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmaxu.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.v64i64(<64 x i64>)

 ; RV32-NEXT:    vle64.v v0, (a1)
 ; RV32-NEXT:    vmaxu.vv v16, v24, v16
 ; RV32-NEXT:    vmaxu.vv v8, v8, v0
 ; RV32-NEXT:    vmaxu.vv v8, v8, v16
 ; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vredmaxu.vs v25, v8, v25
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umax_v64i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a1, a0, 384
 ; RV64-NEXT:    vle64.v v16, (a1)
 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vmaxu.vv v16, v24, v16
 ; RV64-NEXT:    vmaxu.vv v8, v8, v0
 ; RV64-NEXT:    vmaxu.vv v8, v8, v16
 ; RV64-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmaxu.vs v25, v8, v25
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x
   %red = call i64 @llvm.vector.reduce.umax.v64i64(<64 x i64> %v)
   ret i64 %red
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) {
 ; CHECK-LABEL: select_v2f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
-; CHECK-NEXT:    vfmv.f.s ft3, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft2, v25
 ; CHECK-NEXT:    bnez a0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.h ft0, ft1
-; CHECK-NEXT:    fmv.h ft2, ft3
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB0_3
 ; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 1
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    vfmv.f.s ft1, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; CHECK-NEXT:    vfmv.v.f v8, ft2
+; CHECK-NEXT:    vfmv.v.f v8, ft1
 ; CHECK-NEXT:    vfmv.s.f v8, ft0
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <2 x half> %a, <2 x half> %b
   ret <2 x half> %v
 }
 
 define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d) {
 ; CHECK-LABEL: selectcc_v2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
+; CHECK-NEXT:    j .LBB1_3
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
+; CHECK-NEXT:  .LBB1_3:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    bnez a0, .LBB1_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.h ft0, ft1
-; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    vsetivli a1, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
-; CHECK-NEXT:    vfmv.f.s ft1, v9
+; CHECK-NEXT:    bnez a0, .LBB1_5
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    j .LBB1_6
+; CHECK-NEXT:  .LBB1_5:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB1_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.h ft0, ft1
-; CHECK-NEXT:  .LBB1_4:
+; CHECK-NEXT:  .LBB1_6:
 ; CHECK-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.s.f v25, ft0
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %cmp = fcmp oeq half %a, %b
   %v = select i1 %cmp, <2 x half> %c, <2 x half> %d
   ret <2 x half> %v
 }
 
 define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: select_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB2_2
+; CHECK-NEXT:    bnez a0, .LBB2_3
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.h ft0, ft1
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    fsh ft0, 8(sp)
+; CHECK-NEXT:    beqz a0, .LBB2_4
 ; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    j .LBB2_5
+; CHECK-NEXT:  .LBB2_3:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fsh ft0, 8(sp)
+; CHECK-NEXT:    bnez a0, .LBB2_2
+; CHECK-NEXT:  .LBB2_4:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 3
+; CHECK-NEXT:  .LBB2_5:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 3
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB2_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB2_4:
-; CHECK-NEXT:    fsh ft1, 14(sp)
+; CHECK-NEXT:    fsh ft0, 14(sp)
+; CHECK-NEXT:    bnez a0, .LBB2_7
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 2
-; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB2_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB2_6:
-; CHECK-NEXT:    fsh ft1, 12(sp)
+; CHECK-NEXT:    j .LBB2_8
+; CHECK-NEXT:  .LBB2_7:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:  .LBB2_8:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 12(sp)
+; CHECK-NEXT:    bnez a0, .LBB2_10
+; CHECK-NEXT:  # %bb.9:
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB2_11
+; CHECK-NEXT:  .LBB2_10:
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB2_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB2_8:
-; CHECK-NEXT:    fsh ft1, 10(sp)
+; CHECK-NEXT:  .LBB2_11:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 10(sp)
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <4 x half> %a, <4 x half> %b
   ret <4 x half> %v
 }
 
 define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d) {
 ; CHECK-LABEL: selectcc_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB3_2
+; CHECK-NEXT:    bnez a0, .LBB3_3
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.h ft0, ft1
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    fsh ft0, 8(sp)
+; CHECK-NEXT:    beqz a0, .LBB3_4
 ; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    j .LBB3_5
+; CHECK-NEXT:  .LBB3_3:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fsh ft0, 8(sp)
+; CHECK-NEXT:    bnez a0, .LBB3_2
+; CHECK-NEXT:  .LBB3_4:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 3
+; CHECK-NEXT:  .LBB3_5:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 3
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB3_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB3_4:
-; CHECK-NEXT:    fsh ft1, 14(sp)
+; CHECK-NEXT:    fsh ft0, 14(sp)
+; CHECK-NEXT:    bnez a0, .LBB3_7
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 2
-; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB3_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB3_6:
-; CHECK-NEXT:    fsh ft1, 12(sp)
+; CHECK-NEXT:    j .LBB3_8
+; CHECK-NEXT:  .LBB3_7:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:  .LBB3_8:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 12(sp)
+; CHECK-NEXT:    bnez a0, .LBB3_10
+; CHECK-NEXT:  # %bb.9:
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB3_11
+; CHECK-NEXT:  .LBB3_10:
+; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB3_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB3_8:
-; CHECK-NEXT:    fsh ft1, 10(sp)
+; CHECK-NEXT:  .LBB3_11:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 10(sp)
 ; CHECK-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %cmp = fcmp oeq half %a, %b
   %v = select i1 %cmp, <4 x half> %c, <4 x half> %d
   ret <4 x half> %v
 }
 
 define <8 x half> @select_v8f16(i1 zeroext %c, <8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: select_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB4_2
+; CHECK-NEXT:    bnez a0, .LBB4_3
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.h ft0, ft1
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    fsh ft0, 0(sp)
+; CHECK-NEXT:    beqz a0, .LBB4_4
 ; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 7
+; CHECK-NEXT:    j .LBB4_5
+; CHECK-NEXT:  .LBB4_3:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fsh ft0, 0(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_2
+; CHECK-NEXT:  .LBB4_4:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 7
+; CHECK-NEXT:  .LBB4_5:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 7
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_4:
-; CHECK-NEXT:    fsh ft1, 14(sp)
+; CHECK-NEXT:    fsh ft0, 14(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_7
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 6
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB4_8
+; CHECK-NEXT:  .LBB4_7:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 6
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_6:
-; CHECK-NEXT:    fsh ft1, 12(sp)
+; CHECK-NEXT:  .LBB4_8:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 12(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_10
+; CHECK-NEXT:  # %bb.9:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 5
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB4_11
+; CHECK-NEXT:  .LBB4_10:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 5
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_8:
-; CHECK-NEXT:    fsh ft1, 10(sp)
+; CHECK-NEXT:  .LBB4_11:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 10(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_13
+; CHECK-NEXT:  # %bb.12:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 4
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB4_14
+; CHECK-NEXT:  .LBB4_13:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 4
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_10
-; CHECK-NEXT:  # %bb.9:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_10:
-; CHECK-NEXT:    fsh ft1, 8(sp)
+; CHECK-NEXT:  .LBB4_14:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 8(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_16
+; CHECK-NEXT:  # %bb.15:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 3
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB4_17
+; CHECK-NEXT:  .LBB4_16:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 3
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_12
-; CHECK-NEXT:  # %bb.11:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_12:
-; CHECK-NEXT:    fsh ft1, 6(sp)
+; CHECK-NEXT:  .LBB4_17:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 6(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_19
+; CHECK-NEXT:  # %bb.18:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 2
-; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_14
-; CHECK-NEXT:  # %bb.13:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_14:
-; CHECK-NEXT:    fsh ft1, 4(sp)
+; CHECK-NEXT:    j .LBB4_20
+; CHECK-NEXT:  .LBB4_19:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:  .LBB4_20:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 4(sp)
+; CHECK-NEXT:    bnez a0, .LBB4_22
+; CHECK-NEXT:  # %bb.21:
+; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB4_23
+; CHECK-NEXT:  .LBB4_22:
+; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB4_16
-; CHECK-NEXT:  # %bb.15:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB4_16:
-; CHECK-NEXT:    fsh ft1, 2(sp)
+; CHECK-NEXT:  .LBB4_23:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 2(sp)
 ; CHECK-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (sp)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <8 x half> %a, <8 x half> %b
   ret <8 x half> %v
 }
 
 define <8 x half> @selectcc_v8f16(half %a, half %b, <8 x half> %c, <8 x half> %d) {
 ; CHECK-LABEL: selectcc_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB5_2
+; CHECK-NEXT:    bnez a0, .LBB5_3
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.h ft0, ft1
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    fsh ft0, 0(sp)
+; CHECK-NEXT:    beqz a0, .LBB5_4
 ; CHECK-NEXT:  .LBB5_2:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 7
+; CHECK-NEXT:    j .LBB5_5
+; CHECK-NEXT:  .LBB5_3:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fsh ft0, 0(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_2
+; CHECK-NEXT:  .LBB5_4:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 7
+; CHECK-NEXT:  .LBB5_5:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 7
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_4:
-; CHECK-NEXT:    fsh ft1, 14(sp)
+; CHECK-NEXT:    fsh ft0, 14(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_7
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 6
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB5_8
+; CHECK-NEXT:  .LBB5_7:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 6
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_6:
-; CHECK-NEXT:    fsh ft1, 12(sp)
+; CHECK-NEXT:  .LBB5_8:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 12(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_10
+; CHECK-NEXT:  # %bb.9:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 5
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB5_11
+; CHECK-NEXT:  .LBB5_10:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 5
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_8:
-; CHECK-NEXT:    fsh ft1, 10(sp)
+; CHECK-NEXT:  .LBB5_11:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 10(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_13
+; CHECK-NEXT:  # %bb.12:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 4
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB5_14
+; CHECK-NEXT:  .LBB5_13:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 4
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_10
-; CHECK-NEXT:  # %bb.9:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_10:
-; CHECK-NEXT:    fsh ft1, 8(sp)
+; CHECK-NEXT:  .LBB5_14:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 8(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_16
+; CHECK-NEXT:  # %bb.15:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 3
-; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    j .LBB5_17
+; CHECK-NEXT:  .LBB5_16:
+; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 3
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_12
-; CHECK-NEXT:  # %bb.11:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_12:
-; CHECK-NEXT:    fsh ft1, 6(sp)
+; CHECK-NEXT:  .LBB5_17:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 6(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_19
+; CHECK-NEXT:  # %bb.18:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 2
-; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_14
-; CHECK-NEXT:  # %bb.13:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_14:
-; CHECK-NEXT:    fsh ft1, 4(sp)
+; CHECK-NEXT:    j .LBB5_20
+; CHECK-NEXT:  .LBB5_19:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:  .LBB5_20:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 4(sp)
+; CHECK-NEXT:    bnez a0, .LBB5_22
+; CHECK-NEXT:  # %bb.21:
+; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB5_23
+; CHECK-NEXT:  .LBB5_22:
+; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB5_16
-; CHECK-NEXT:  # %bb.15:
-; CHECK-NEXT:    fmv.h ft1, ft0
-; CHECK-NEXT:  .LBB5_16:
-; CHECK-NEXT:    fsh ft1, 2(sp)
+; CHECK-NEXT:  .LBB5_23:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsh ft0, 2(sp)
 ; CHECK-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v8, (sp)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %cmp = fcmp oeq half %a, %b
   %v = select i1 %cmp, <8 x half> %c, <8 x half> %d
   ret <8 x half> %v
 }
 
 define <16 x half> @select_v16f16(i1 zeroext %c, <16 x half> %a, <16 x half> %b) {
 ; RV32-LABEL: select_v16f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -64
 ; RV32-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 64
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
-; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB6_2
+; RV32-NEXT:    bnez a0, .LBB6_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.h ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v10
+; RV32-NEXT:    fsh ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB6_4
 ; RV32-NEXT:  .LBB6_2:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v8, 15
+; RV32-NEXT:    j .LBB6_5
+; RV32-NEXT:  .LBB6_3:
+; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsh ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB6_2
+; RV32-NEXT:  .LBB6_4:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 15
+; RV32-NEXT:  .LBB6_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 15
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_4:
-; RV32-NEXT:    fsh ft1, 30(sp)
+; RV32-NEXT:    fsh ft0, 30(sp)
+; RV32-NEXT:    bnez a0, .LBB6_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 14
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_8
+; RV32-NEXT:  .LBB6_7:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 14
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_6:
-; RV32-NEXT:    fsh ft1, 28(sp)
+; RV32-NEXT:  .LBB6_8:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 28(sp)
+; RV32-NEXT:    bnez a0, .LBB6_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 13
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_11
+; RV32-NEXT:  .LBB6_10:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 13
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_8:
-; RV32-NEXT:    fsh ft1, 26(sp)
+; RV32-NEXT:  .LBB6_11:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 26(sp)
+; RV32-NEXT:    bnez a0, .LBB6_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 12
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_14
+; RV32-NEXT:  .LBB6_13:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 12
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_10:
-; RV32-NEXT:    fsh ft1, 24(sp)
+; RV32-NEXT:  .LBB6_14:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB6_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 11
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_17
+; RV32-NEXT:  .LBB6_16:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 11
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_12:
-; RV32-NEXT:    fsh ft1, 22(sp)
+; RV32-NEXT:  .LBB6_17:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 22(sp)
+; RV32-NEXT:    bnez a0, .LBB6_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 10
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_20
+; RV32-NEXT:  .LBB6_19:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 10
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_14:
-; RV32-NEXT:    fsh ft1, 20(sp)
+; RV32-NEXT:  .LBB6_20:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 20(sp)
+; RV32-NEXT:    bnez a0, .LBB6_22
+; RV32-NEXT:  # %bb.21:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 9
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_23
+; RV32-NEXT:  .LBB6_22:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 9
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_16:
-; RV32-NEXT:    fsh ft1, 18(sp)
+; RV32-NEXT:  .LBB6_23:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 18(sp)
+; RV32-NEXT:    bnez a0, .LBB6_25
+; RV32-NEXT:  # %bb.24:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 8
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_26
+; RV32-NEXT:  .LBB6_25:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 8
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_18
-; RV32-NEXT:  # %bb.17:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_18:
-; RV32-NEXT:    fsh ft1, 16(sp)
+; RV32-NEXT:  .LBB6_26:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB6_28
+; RV32-NEXT:  # %bb.27:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 7
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_29
+; RV32-NEXT:  .LBB6_28:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_20
-; RV32-NEXT:  # %bb.19:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_20:
-; RV32-NEXT:    fsh ft1, 14(sp)
+; RV32-NEXT:  .LBB6_29:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 14(sp)
+; RV32-NEXT:    bnez a0, .LBB6_31
+; RV32-NEXT:  # %bb.30:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 6
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_32
+; RV32-NEXT:  .LBB6_31:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_22
-; RV32-NEXT:  # %bb.21:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_22:
-; RV32-NEXT:    fsh ft1, 12(sp)
+; RV32-NEXT:  .LBB6_32:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 12(sp)
+; RV32-NEXT:    bnez a0, .LBB6_34
+; RV32-NEXT:  # %bb.33:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 5
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_35
+; RV32-NEXT:  .LBB6_34:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_24
-; RV32-NEXT:  # %bb.23:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_24:
-; RV32-NEXT:    fsh ft1, 10(sp)
+; RV32-NEXT:  .LBB6_35:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 10(sp)
+; RV32-NEXT:    bnez a0, .LBB6_37
+; RV32-NEXT:  # %bb.36:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 4
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_38
+; RV32-NEXT:  .LBB6_37:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_26
-; RV32-NEXT:  # %bb.25:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_26:
-; RV32-NEXT:    fsh ft1, 8(sp)
+; RV32-NEXT:  .LBB6_38:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 8(sp)
+; RV32-NEXT:    bnez a0, .LBB6_40
+; RV32-NEXT:  # %bb.39:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 3
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB6_41
+; RV32-NEXT:  .LBB6_40:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_28
-; RV32-NEXT:  # %bb.27:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_28:
-; RV32-NEXT:    fsh ft1, 6(sp)
+; RV32-NEXT:  .LBB6_41:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 6(sp)
+; RV32-NEXT:    bnez a0, .LBB6_43
+; RV32-NEXT:  # %bb.42:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 2
-; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_30
-; RV32-NEXT:  # %bb.29:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_30:
-; RV32-NEXT:    fsh ft1, 4(sp)
+; RV32-NEXT:    j .LBB6_44
+; RV32-NEXT:  .LBB6_43:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    vslidedown.vi v26, v8, 2
+; RV32-NEXT:  .LBB6_44:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 4(sp)
+; RV32-NEXT:    bnez a0, .LBB6_46
+; RV32-NEXT:  # %bb.45:
+; RV32-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    j .LBB6_47
+; RV32-NEXT:  .LBB6_46:
+; RV32-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB6_32
-; RV32-NEXT:  # %bb.31:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB6_32:
-; RV32-NEXT:    fsh ft1, 2(sp)
+; RV32-NEXT:  .LBB6_47:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 2(sp)
 ; RV32-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; RV32-NEXT:    vle16.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -64
 ; RV32-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 64
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_v16f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
 ; RV64-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 64
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
-; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB6_2
+; RV64-NEXT:    bnez a0, .LBB6_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.h ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v10
+; RV64-NEXT:    fsh ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB6_4
 ; RV64-NEXT:  .LBB6_2:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v8, 15
+; RV64-NEXT:    j .LBB6_5
+; RV64-NEXT:  .LBB6_3:
+; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsh ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB6_2
+; RV64-NEXT:  .LBB6_4:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 15
+; RV64-NEXT:  .LBB6_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 15
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_4:
-; RV64-NEXT:    fsh ft1, 30(sp)
+; RV64-NEXT:    fsh ft0, 30(sp)
+; RV64-NEXT:    bnez a0, .LBB6_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 14
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_8
+; RV64-NEXT:  .LBB6_7:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 14
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_6:
-; RV64-NEXT:    fsh ft1, 28(sp)
+; RV64-NEXT:  .LBB6_8:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 28(sp)
+; RV64-NEXT:    bnez a0, .LBB6_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 13
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_11
+; RV64-NEXT:  .LBB6_10:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 13
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_8:
-; RV64-NEXT:    fsh ft1, 26(sp)
+; RV64-NEXT:  .LBB6_11:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 26(sp)
+; RV64-NEXT:    bnez a0, .LBB6_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 12
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_14
+; RV64-NEXT:  .LBB6_13:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 12
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_10:
-; RV64-NEXT:    fsh ft1, 24(sp)
+; RV64-NEXT:  .LBB6_14:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB6_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 11
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_17
+; RV64-NEXT:  .LBB6_16:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 11
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_12:
-; RV64-NEXT:    fsh ft1, 22(sp)
+; RV64-NEXT:  .LBB6_17:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 22(sp)
+; RV64-NEXT:    bnez a0, .LBB6_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 10
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_20
+; RV64-NEXT:  .LBB6_19:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 10
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_14:
-; RV64-NEXT:    fsh ft1, 20(sp)
+; RV64-NEXT:  .LBB6_20:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 20(sp)
+; RV64-NEXT:    bnez a0, .LBB6_22
+; RV64-NEXT:  # %bb.21:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 9
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_23
+; RV64-NEXT:  .LBB6_22:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 9
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_16:
-; RV64-NEXT:    fsh ft1, 18(sp)
+; RV64-NEXT:  .LBB6_23:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 18(sp)
+; RV64-NEXT:    bnez a0, .LBB6_25
+; RV64-NEXT:  # %bb.24:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 8
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_26
+; RV64-NEXT:  .LBB6_25:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 8
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_18
-; RV64-NEXT:  # %bb.17:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_18:
-; RV64-NEXT:    fsh ft1, 16(sp)
+; RV64-NEXT:  .LBB6_26:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB6_28
+; RV64-NEXT:  # %bb.27:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 7
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_29
+; RV64-NEXT:  .LBB6_28:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_20
-; RV64-NEXT:  # %bb.19:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_20:
-; RV64-NEXT:    fsh ft1, 14(sp)
+; RV64-NEXT:  .LBB6_29:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 14(sp)
+; RV64-NEXT:    bnez a0, .LBB6_31
+; RV64-NEXT:  # %bb.30:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 6
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_32
+; RV64-NEXT:  .LBB6_31:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_22
-; RV64-NEXT:  # %bb.21:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_22:
-; RV64-NEXT:    fsh ft1, 12(sp)
+; RV64-NEXT:  .LBB6_32:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 12(sp)
+; RV64-NEXT:    bnez a0, .LBB6_34
+; RV64-NEXT:  # %bb.33:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 5
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_35
+; RV64-NEXT:  .LBB6_34:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_24
-; RV64-NEXT:  # %bb.23:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_24:
-; RV64-NEXT:    fsh ft1, 10(sp)
+; RV64-NEXT:  .LBB6_35:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 10(sp)
+; RV64-NEXT:    bnez a0, .LBB6_37
+; RV64-NEXT:  # %bb.36:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 4
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_38
+; RV64-NEXT:  .LBB6_37:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_26
-; RV64-NEXT:  # %bb.25:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_26:
-; RV64-NEXT:    fsh ft1, 8(sp)
+; RV64-NEXT:  .LBB6_38:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 8(sp)
+; RV64-NEXT:    bnez a0, .LBB6_40
+; RV64-NEXT:  # %bb.39:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 3
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB6_41
+; RV64-NEXT:  .LBB6_40:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_28
-; RV64-NEXT:  # %bb.27:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_28:
-; RV64-NEXT:    fsh ft1, 6(sp)
+; RV64-NEXT:  .LBB6_41:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 6(sp)
+; RV64-NEXT:    bnez a0, .LBB6_43
+; RV64-NEXT:  # %bb.42:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 2
-; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_30
-; RV64-NEXT:  # %bb.29:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_30:
-; RV64-NEXT:    fsh ft1, 4(sp)
+; RV64-NEXT:    j .LBB6_44
+; RV64-NEXT:  .LBB6_43:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    vslidedown.vi v26, v8, 2
+; RV64-NEXT:  .LBB6_44:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 4(sp)
+; RV64-NEXT:    bnez a0, .LBB6_46
+; RV64-NEXT:  # %bb.45:
+; RV64-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    j .LBB6_47
+; RV64-NEXT:  .LBB6_46:
+; RV64-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB6_32
-; RV64-NEXT:  # %bb.31:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB6_32:
-; RV64-NEXT:    fsh ft1, 2(sp)
+; RV64-NEXT:  .LBB6_47:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 2(sp)
 ; RV64-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; RV64-NEXT:    vle16.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
   %v = select i1 %c, <16 x half> %a, <16 x half> %b
   ret <16 x half> %v
 }
 
 define <16 x half> @selectcc_v16f16(half %a, half %b, <16 x half> %c, <16 x half> %d) {
 ; RV32-LABEL: selectcc_v16f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -64
 ; RV32-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 64
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
 ; RV32-NEXT:    feq.h a0, fa0, fa1
-; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB7_2
+; RV32-NEXT:    bnez a0, .LBB7_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.h ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v10
+; RV32-NEXT:    fsh ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB7_4
 ; RV32-NEXT:  .LBB7_2:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v8, 15
+; RV32-NEXT:    j .LBB7_5
+; RV32-NEXT:  .LBB7_3:
+; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsh ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB7_2
+; RV32-NEXT:  .LBB7_4:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 15
+; RV32-NEXT:  .LBB7_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 15
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_4:
-; RV32-NEXT:    fsh ft1, 30(sp)
+; RV32-NEXT:    fsh ft0, 30(sp)
+; RV32-NEXT:    bnez a0, .LBB7_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 14
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_8
+; RV32-NEXT:  .LBB7_7:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 14
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_6:
-; RV32-NEXT:    fsh ft1, 28(sp)
+; RV32-NEXT:  .LBB7_8:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 28(sp)
+; RV32-NEXT:    bnez a0, .LBB7_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 13
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_11
+; RV32-NEXT:  .LBB7_10:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 13
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_8:
-; RV32-NEXT:    fsh ft1, 26(sp)
+; RV32-NEXT:  .LBB7_11:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 26(sp)
+; RV32-NEXT:    bnez a0, .LBB7_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 12
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_14
+; RV32-NEXT:  .LBB7_13:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 12
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_10:
-; RV32-NEXT:    fsh ft1, 24(sp)
+; RV32-NEXT:  .LBB7_14:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB7_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 11
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_17
+; RV32-NEXT:  .LBB7_16:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 11
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_12:
-; RV32-NEXT:    fsh ft1, 22(sp)
+; RV32-NEXT:  .LBB7_17:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 22(sp)
+; RV32-NEXT:    bnez a0, .LBB7_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 10
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_20
+; RV32-NEXT:  .LBB7_19:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 10
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_14:
-; RV32-NEXT:    fsh ft1, 20(sp)
+; RV32-NEXT:  .LBB7_20:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 20(sp)
+; RV32-NEXT:    bnez a0, .LBB7_22
+; RV32-NEXT:  # %bb.21:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 9
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_23
+; RV32-NEXT:  .LBB7_22:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 9
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_16:
-; RV32-NEXT:    fsh ft1, 18(sp)
+; RV32-NEXT:  .LBB7_23:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 18(sp)
+; RV32-NEXT:    bnez a0, .LBB7_25
+; RV32-NEXT:  # %bb.24:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 8
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_26
+; RV32-NEXT:  .LBB7_25:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 8
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_18
-; RV32-NEXT:  # %bb.17:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_18:
-; RV32-NEXT:    fsh ft1, 16(sp)
+; RV32-NEXT:  .LBB7_26:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB7_28
+; RV32-NEXT:  # %bb.27:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 7
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_29
+; RV32-NEXT:  .LBB7_28:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_20
-; RV32-NEXT:  # %bb.19:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_20:
-; RV32-NEXT:    fsh ft1, 14(sp)
+; RV32-NEXT:  .LBB7_29:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 14(sp)
+; RV32-NEXT:    bnez a0, .LBB7_31
+; RV32-NEXT:  # %bb.30:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 6
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_32
+; RV32-NEXT:  .LBB7_31:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_22
-; RV32-NEXT:  # %bb.21:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_22:
-; RV32-NEXT:    fsh ft1, 12(sp)
+; RV32-NEXT:  .LBB7_32:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 12(sp)
+; RV32-NEXT:    bnez a0, .LBB7_34
+; RV32-NEXT:  # %bb.33:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 5
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_35
+; RV32-NEXT:  .LBB7_34:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_24
-; RV32-NEXT:  # %bb.23:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_24:
-; RV32-NEXT:    fsh ft1, 10(sp)
+; RV32-NEXT:  .LBB7_35:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 10(sp)
+; RV32-NEXT:    bnez a0, .LBB7_37
+; RV32-NEXT:  # %bb.36:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 4
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_38
+; RV32-NEXT:  .LBB7_37:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_26
-; RV32-NEXT:  # %bb.25:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_26:
-; RV32-NEXT:    fsh ft1, 8(sp)
+; RV32-NEXT:  .LBB7_38:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 8(sp)
+; RV32-NEXT:    bnez a0, .LBB7_40
+; RV32-NEXT:  # %bb.39:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 3
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB7_41
+; RV32-NEXT:  .LBB7_40:
+; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_28
-; RV32-NEXT:  # %bb.27:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_28:
-; RV32-NEXT:    fsh ft1, 6(sp)
+; RV32-NEXT:  .LBB7_41:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 6(sp)
+; RV32-NEXT:    bnez a0, .LBB7_43
+; RV32-NEXT:  # %bb.42:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 2
-; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_30
-; RV32-NEXT:  # %bb.29:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_30:
-; RV32-NEXT:    fsh ft1, 4(sp)
+; RV32-NEXT:    j .LBB7_44
+; RV32-NEXT:  .LBB7_43:
 ; RV32-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    vslidedown.vi v26, v8, 2
+; RV32-NEXT:  .LBB7_44:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 4(sp)
+; RV32-NEXT:    bnez a0, .LBB7_46
+; RV32-NEXT:  # %bb.45:
+; RV32-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    j .LBB7_47
+; RV32-NEXT:  .LBB7_46:
+; RV32-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB7_32
-; RV32-NEXT:  # %bb.31:
-; RV32-NEXT:    fmv.h ft1, ft0
-; RV32-NEXT:  .LBB7_32:
-; RV32-NEXT:    fsh ft1, 2(sp)
+; RV32-NEXT:  .LBB7_47:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsh ft0, 2(sp)
 ; RV32-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; RV32-NEXT:    vle16.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -64
 ; RV32-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 64
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selectcc_v16f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
 ; RV64-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 64
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
 ; RV64-NEXT:    feq.h a0, fa0, fa1
-; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB7_2
+; RV64-NEXT:    bnez a0, .LBB7_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.h ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v10
+; RV64-NEXT:    fsh ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB7_4
 ; RV64-NEXT:  .LBB7_2:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v8, 15
+; RV64-NEXT:    j .LBB7_5
+; RV64-NEXT:  .LBB7_3:
+; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsh ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB7_2
+; RV64-NEXT:  .LBB7_4:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 15
+; RV64-NEXT:  .LBB7_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 15
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_4:
-; RV64-NEXT:    fsh ft1, 30(sp)
+; RV64-NEXT:    fsh ft0, 30(sp)
+; RV64-NEXT:    bnez a0, .LBB7_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 14
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_8
+; RV64-NEXT:  .LBB7_7:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 14
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_6:
-; RV64-NEXT:    fsh ft1, 28(sp)
+; RV64-NEXT:  .LBB7_8:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 28(sp)
+; RV64-NEXT:    bnez a0, .LBB7_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 13
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_11
+; RV64-NEXT:  .LBB7_10:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 13
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_8:
-; RV64-NEXT:    fsh ft1, 26(sp)
+; RV64-NEXT:  .LBB7_11:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 26(sp)
+; RV64-NEXT:    bnez a0, .LBB7_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 12
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_14
+; RV64-NEXT:  .LBB7_13:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 12
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_10:
-; RV64-NEXT:    fsh ft1, 24(sp)
+; RV64-NEXT:  .LBB7_14:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB7_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 11
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_17
+; RV64-NEXT:  .LBB7_16:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 11
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_12:
-; RV64-NEXT:    fsh ft1, 22(sp)
+; RV64-NEXT:  .LBB7_17:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 22(sp)
+; RV64-NEXT:    bnez a0, .LBB7_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 10
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_20
+; RV64-NEXT:  .LBB7_19:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 10
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_14:
-; RV64-NEXT:    fsh ft1, 20(sp)
+; RV64-NEXT:  .LBB7_20:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 20(sp)
+; RV64-NEXT:    bnez a0, .LBB7_22
+; RV64-NEXT:  # %bb.21:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 9
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_23
+; RV64-NEXT:  .LBB7_22:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 9
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_16:
-; RV64-NEXT:    fsh ft1, 18(sp)
+; RV64-NEXT:  .LBB7_23:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 18(sp)
+; RV64-NEXT:    bnez a0, .LBB7_25
+; RV64-NEXT:  # %bb.24:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 8
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_26
+; RV64-NEXT:  .LBB7_25:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 8
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_18
-; RV64-NEXT:  # %bb.17:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_18:
-; RV64-NEXT:    fsh ft1, 16(sp)
+; RV64-NEXT:  .LBB7_26:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB7_28
+; RV64-NEXT:  # %bb.27:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 7
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_29
+; RV64-NEXT:  .LBB7_28:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_20
-; RV64-NEXT:  # %bb.19:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_20:
-; RV64-NEXT:    fsh ft1, 14(sp)
+; RV64-NEXT:  .LBB7_29:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 14(sp)
+; RV64-NEXT:    bnez a0, .LBB7_31
+; RV64-NEXT:  # %bb.30:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 6
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_32
+; RV64-NEXT:  .LBB7_31:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_22
-; RV64-NEXT:  # %bb.21:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_22:
-; RV64-NEXT:    fsh ft1, 12(sp)
+; RV64-NEXT:  .LBB7_32:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 12(sp)
+; RV64-NEXT:    bnez a0, .LBB7_34
+; RV64-NEXT:  # %bb.33:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 5
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_35
+; RV64-NEXT:  .LBB7_34:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_24
-; RV64-NEXT:  # %bb.23:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_24:
-; RV64-NEXT:    fsh ft1, 10(sp)
+; RV64-NEXT:  .LBB7_35:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 10(sp)
+; RV64-NEXT:    bnez a0, .LBB7_37
+; RV64-NEXT:  # %bb.36:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 4
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_38
+; RV64-NEXT:  .LBB7_37:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_26
-; RV64-NEXT:  # %bb.25:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_26:
-; RV64-NEXT:    fsh ft1, 8(sp)
+; RV64-NEXT:  .LBB7_38:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 8(sp)
+; RV64-NEXT:    bnez a0, .LBB7_40
+; RV64-NEXT:  # %bb.39:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 3
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB7_41
+; RV64-NEXT:  .LBB7_40:
+; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_28
-; RV64-NEXT:  # %bb.27:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_28:
-; RV64-NEXT:    fsh ft1, 6(sp)
+; RV64-NEXT:  .LBB7_41:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 6(sp)
+; RV64-NEXT:    bnez a0, .LBB7_43
+; RV64-NEXT:  # %bb.42:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 2
-; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_30
-; RV64-NEXT:  # %bb.29:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_30:
-; RV64-NEXT:    fsh ft1, 4(sp)
+; RV64-NEXT:    j .LBB7_44
+; RV64-NEXT:  .LBB7_43:
 ; RV64-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    vslidedown.vi v26, v8, 2
+; RV64-NEXT:  .LBB7_44:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 4(sp)
+; RV64-NEXT:    bnez a0, .LBB7_46
+; RV64-NEXT:  # %bb.45:
+; RV64-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    j .LBB7_47
+; RV64-NEXT:  .LBB7_46:
+; RV64-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB7_32
-; RV64-NEXT:  # %bb.31:
-; RV64-NEXT:    fmv.h ft1, ft0
-; RV64-NEXT:  .LBB7_32:
-; RV64-NEXT:    fsh ft1, 2(sp)
+; RV64-NEXT:  .LBB7_47:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsh ft0, 2(sp)
 ; RV64-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; RV64-NEXT:    vle16.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
   %cmp = fcmp oeq half %a, %b
   %v = select i1 %cmp, <16 x half> %c, <16 x half> %d
   ret <16 x half> %v
 }
 
 define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b) {
 ; CHECK-LABEL: select_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
-; CHECK-NEXT:    vfmv.f.s ft3, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft2, v25
 ; CHECK-NEXT:    bnez a0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.s ft0, ft1
-; CHECK-NEXT:    fmv.s ft2, ft3
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB8_3
 ; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
+; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 1
+; CHECK-NEXT:  .LBB8_3:
+; CHECK-NEXT:    vfmv.f.s ft1, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; CHECK-NEXT:    vfmv.v.f v8, ft2
+; CHECK-NEXT:    vfmv.v.f v8, ft1
 ; CHECK-NEXT:    vfmv.s.f v8, ft0
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <2 x float> %a, <2 x float> %b
   ret <2 x float> %v
 }
 
 define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d) {
 ; CHECK-LABEL: selectcc_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB9_2
+; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
+; CHECK-NEXT:    j .LBB9_3
+; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
+; CHECK-NEXT:  .LBB9_3:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    bnez a0, .LBB9_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.s ft0, ft1
-; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
-; CHECK-NEXT:    vfmv.f.s ft1, v9
+; CHECK-NEXT:    bnez a0, .LBB9_5
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    j .LBB9_6
+; CHECK-NEXT:  .LBB9_5:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB9_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.s ft0, ft1
-; CHECK-NEXT:  .LBB9_4:
+; CHECK-NEXT:  .LBB9_6:
 ; CHECK-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.s.f v25, ft0
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   %v = select i1 %cmp, <2 x float> %c, <2 x float> %d
   ret <2 x float> %v
 }
 
 define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: select_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB10_2
+; CHECK-NEXT:    bnez a0, .LBB10_3
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.s ft0, ft1
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    fsw ft0, 0(sp)
+; CHECK-NEXT:    beqz a0, .LBB10_4
 ; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    j .LBB10_5
+; CHECK-NEXT:  .LBB10_3:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fsw ft0, 0(sp)
+; CHECK-NEXT:    bnez a0, .LBB10_2
+; CHECK-NEXT:  .LBB10_4:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 3
+; CHECK-NEXT:  .LBB10_5:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 3
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB10_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.s ft1, ft0
-; CHECK-NEXT:  .LBB10_4:
-; CHECK-NEXT:    fsw ft1, 12(sp)
+; CHECK-NEXT:    fsw ft0, 12(sp)
+; CHECK-NEXT:    bnez a0, .LBB10_7
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 2
-; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB10_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    fmv.s ft1, ft0
-; CHECK-NEXT:  .LBB10_6:
-; CHECK-NEXT:    fsw ft1, 8(sp)
+; CHECK-NEXT:    j .LBB10_8
+; CHECK-NEXT:  .LBB10_7:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:  .LBB10_8:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsw ft0, 8(sp)
+; CHECK-NEXT:    bnez a0, .LBB10_10
+; CHECK-NEXT:  # %bb.9:
+; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB10_11
+; CHECK-NEXT:  .LBB10_10:
+; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB10_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    fmv.s ft1, ft0
-; CHECK-NEXT:  .LBB10_8:
-; CHECK-NEXT:    fsw ft1, 4(sp)
+; CHECK-NEXT:  .LBB10_11:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsw ft0, 4(sp)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (sp)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <4 x float> %a, <4 x float> %b
   ret <4 x float> %v
 }
 
 define <4 x float> @selectcc_v4f32(float %a, float %b, <4 x float> %c, <4 x float> %d) {
 ; CHECK-LABEL: selectcc_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    feq.s a0, fa0, fa1
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB11_2
+; CHECK-NEXT:    bnez a0, .LBB11_3
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.s ft0, ft1
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    fsw ft0, 0(sp)
+; CHECK-NEXT:    beqz a0, .LBB11_4
 ; CHECK-NEXT:  .LBB11_2:
+; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    j .LBB11_5
+; CHECK-NEXT:  .LBB11_3:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
 ; CHECK-NEXT:    fsw ft0, 0(sp)
+; CHECK-NEXT:    bnez a0, .LBB11_2
+; CHECK-NEXT:  .LBB11_4:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 3
+; CHECK-NEXT:  .LBB11_5:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 3
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB11_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.s ft1, ft0
-; CHECK-NEXT:  .LBB11_4:
-; CHECK-NEXT:    fsw ft1, 12(sp)
+; CHECK-NEXT:    fsw ft0, 12(sp)
+; CHECK-NEXT:    bnez a0, .LBB11_7
+; CHECK-NEXT:  # %bb.6:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 2
-; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB11_6
-; CHECK-NEXT:  # %bb.5:
-; CHECK-NEXT:    fmv.s ft1, ft0
-; CHECK-NEXT:  .LBB11_6:
-; CHECK-NEXT:    fsw ft1, 8(sp)
+; CHECK-NEXT:    j .LBB11_8
+; CHECK-NEXT:  .LBB11_7:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:  .LBB11_8:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsw ft0, 8(sp)
+; CHECK-NEXT:    bnez a0, .LBB11_10
+; CHECK-NEXT:  # %bb.9:
+; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB11_11
+; CHECK-NEXT:  .LBB11_10:
+; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
-; CHECK-NEXT:    bnez a0, .LBB11_8
-; CHECK-NEXT:  # %bb.7:
-; CHECK-NEXT:    fmv.s ft1, ft0
-; CHECK-NEXT:  .LBB11_8:
-; CHECK-NEXT:    fsw ft1, 4(sp)
+; CHECK-NEXT:  .LBB11_11:
+; CHECK-NEXT:    vfmv.f.s ft0, v25
+; CHECK-NEXT:    fsw ft0, 4(sp)
 ; CHECK-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; CHECK-NEXT:    vle32.v v8, (sp)
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   %v = select i1 %cmp, <4 x float> %c, <4 x float> %d
   ret <4 x float> %v
 }
 
 define <8 x float> @select_v8f32(i1 zeroext %c, <8 x float> %a, <8 x float> %b) {
 ; RV32-LABEL: select_v8f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -64
 ; RV32-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 64
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB12_2
+; RV32-NEXT:    bnez a0, .LBB12_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.s ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v10
+; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB12_4
 ; RV32-NEXT:  .LBB12_2:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v8, 7
+; RV32-NEXT:    j .LBB12_5
+; RV32-NEXT:  .LBB12_3:
+; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB12_2
+; RV32-NEXT:  .LBB12_4:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 7
+; RV32-NEXT:  .LBB12_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_4:
-; RV32-NEXT:    fsw ft1, 28(sp)
+; RV32-NEXT:    fsw ft0, 28(sp)
+; RV32-NEXT:    bnez a0, .LBB12_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 6
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB12_8
+; RV32-NEXT:  .LBB12_7:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_6:
-; RV32-NEXT:    fsw ft1, 24(sp)
+; RV32-NEXT:  .LBB12_8:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB12_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 5
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB12_11
+; RV32-NEXT:  .LBB12_10:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_8:
-; RV32-NEXT:    fsw ft1, 20(sp)
+; RV32-NEXT:  .LBB12_11:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 20(sp)
+; RV32-NEXT:    bnez a0, .LBB12_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 4
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB12_14
+; RV32-NEXT:  .LBB12_13:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_10:
-; RV32-NEXT:    fsw ft1, 16(sp)
+; RV32-NEXT:  .LBB12_14:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB12_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 3
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB12_17
+; RV32-NEXT:  .LBB12_16:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_12:
-; RV32-NEXT:    fsw ft1, 12(sp)
+; RV32-NEXT:  .LBB12_17:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 12(sp)
+; RV32-NEXT:    bnez a0, .LBB12_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 2
-; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_14:
-; RV32-NEXT:    fsw ft1, 8(sp)
+; RV32-NEXT:    j .LBB12_20
+; RV32-NEXT:  .LBB12_19:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    vslidedown.vi v26, v8, 2
+; RV32-NEXT:  .LBB12_20:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 8(sp)
+; RV32-NEXT:    bnez a0, .LBB12_22
+; RV32-NEXT:  # %bb.21:
+; RV32-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    j .LBB12_23
+; RV32-NEXT:  .LBB12_22:
+; RV32-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB12_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB12_16:
-; RV32-NEXT:    fsw ft1, 4(sp)
+; RV32-NEXT:  .LBB12_23:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 4(sp)
 ; RV32-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -64
 ; RV32-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 64
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_v8f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
 ; RV64-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 64
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
-; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB12_2
+; RV64-NEXT:    bnez a0, .LBB12_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.s ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v10
+; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB12_4
 ; RV64-NEXT:  .LBB12_2:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v8, 7
+; RV64-NEXT:    j .LBB12_5
+; RV64-NEXT:  .LBB12_3:
+; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB12_2
+; RV64-NEXT:  .LBB12_4:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 7
+; RV64-NEXT:  .LBB12_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_4:
-; RV64-NEXT:    fsw ft1, 28(sp)
+; RV64-NEXT:    fsw ft0, 28(sp)
+; RV64-NEXT:    bnez a0, .LBB12_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 6
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB12_8
+; RV64-NEXT:  .LBB12_7:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_6:
-; RV64-NEXT:    fsw ft1, 24(sp)
+; RV64-NEXT:  .LBB12_8:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB12_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 5
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB12_11
+; RV64-NEXT:  .LBB12_10:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_8:
-; RV64-NEXT:    fsw ft1, 20(sp)
+; RV64-NEXT:  .LBB12_11:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 20(sp)
+; RV64-NEXT:    bnez a0, .LBB12_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 4
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB12_14
+; RV64-NEXT:  .LBB12_13:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_10:
-; RV64-NEXT:    fsw ft1, 16(sp)
+; RV64-NEXT:  .LBB12_14:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB12_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 3
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB12_17
+; RV64-NEXT:  .LBB12_16:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_12:
-; RV64-NEXT:    fsw ft1, 12(sp)
+; RV64-NEXT:  .LBB12_17:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 12(sp)
+; RV64-NEXT:    bnez a0, .LBB12_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 2
-; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_14:
-; RV64-NEXT:    fsw ft1, 8(sp)
+; RV64-NEXT:    j .LBB12_20
+; RV64-NEXT:  .LBB12_19:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    vslidedown.vi v26, v8, 2
+; RV64-NEXT:  .LBB12_20:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 8(sp)
+; RV64-NEXT:    bnez a0, .LBB12_22
+; RV64-NEXT:  # %bb.21:
+; RV64-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    j .LBB12_23
+; RV64-NEXT:  .LBB12_22:
+; RV64-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB12_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB12_16:
-; RV64-NEXT:    fsw ft1, 4(sp)
+; RV64-NEXT:  .LBB12_23:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 4(sp)
 ; RV64-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV64-NEXT:    vle32.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
   %v = select i1 %c, <8 x float> %a, <8 x float> %b
   ret <8 x float> %v
 }
 
 define <8 x float> @selectcc_v8f32(float %a, float %b, <8 x float> %c, <8 x float> %d) {
 ; RV32-LABEL: selectcc_v8f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -64
 ; RV32-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 64
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
 ; RV32-NEXT:    feq.s a0, fa0, fa1
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB13_2
+; RV32-NEXT:    bnez a0, .LBB13_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.s ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v10
+; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB13_4
 ; RV32-NEXT:  .LBB13_2:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v8, 7
+; RV32-NEXT:    j .LBB13_5
+; RV32-NEXT:  .LBB13_3:
+; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB13_2
+; RV32-NEXT:  .LBB13_4:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 7
+; RV32-NEXT:  .LBB13_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_4:
-; RV32-NEXT:    fsw ft1, 28(sp)
+; RV32-NEXT:    fsw ft0, 28(sp)
+; RV32-NEXT:    bnez a0, .LBB13_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 6
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB13_8
+; RV32-NEXT:  .LBB13_7:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_6:
-; RV32-NEXT:    fsw ft1, 24(sp)
+; RV32-NEXT:  .LBB13_8:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB13_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 5
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB13_11
+; RV32-NEXT:  .LBB13_10:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_8:
-; RV32-NEXT:    fsw ft1, 20(sp)
+; RV32-NEXT:  .LBB13_11:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 20(sp)
+; RV32-NEXT:    bnez a0, .LBB13_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 4
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB13_14
+; RV32-NEXT:  .LBB13_13:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_10:
-; RV32-NEXT:    fsw ft1, 16(sp)
+; RV32-NEXT:  .LBB13_14:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB13_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 3
-; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    j .LBB13_17
+; RV32-NEXT:  .LBB13_16:
+; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_12:
-; RV32-NEXT:    fsw ft1, 12(sp)
+; RV32-NEXT:  .LBB13_17:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 12(sp)
+; RV32-NEXT:    bnez a0, .LBB13_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 2
-; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_14:
-; RV32-NEXT:    fsw ft1, 8(sp)
+; RV32-NEXT:    j .LBB13_20
+; RV32-NEXT:  .LBB13_19:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    vslidedown.vi v26, v8, 2
+; RV32-NEXT:  .LBB13_20:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 8(sp)
+; RV32-NEXT:    bnez a0, .LBB13_22
+; RV32-NEXT:  # %bb.21:
+; RV32-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    j .LBB13_23
+; RV32-NEXT:  .LBB13_22:
+; RV32-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB13_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB13_16:
-; RV32-NEXT:    fsw ft1, 4(sp)
+; RV32-NEXT:  .LBB13_23:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsw ft0, 4(sp)
 ; RV32-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -64
 ; RV32-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 64
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selectcc_v8f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
 ; RV64-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 64
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
 ; RV64-NEXT:    feq.s a0, fa0, fa1
-; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB13_2
+; RV64-NEXT:    bnez a0, .LBB13_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.s ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v10
+; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB13_4
 ; RV64-NEXT:  .LBB13_2:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v8, 7
+; RV64-NEXT:    j .LBB13_5
+; RV64-NEXT:  .LBB13_3:
+; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB13_2
+; RV64-NEXT:  .LBB13_4:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 7
+; RV64-NEXT:  .LBB13_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_4:
-; RV64-NEXT:    fsw ft1, 28(sp)
+; RV64-NEXT:    fsw ft0, 28(sp)
+; RV64-NEXT:    bnez a0, .LBB13_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 6
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB13_8
+; RV64-NEXT:  .LBB13_7:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_6:
-; RV64-NEXT:    fsw ft1, 24(sp)
+; RV64-NEXT:  .LBB13_8:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB13_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 5
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB13_11
+; RV64-NEXT:  .LBB13_10:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_8:
-; RV64-NEXT:    fsw ft1, 20(sp)
+; RV64-NEXT:  .LBB13_11:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 20(sp)
+; RV64-NEXT:    bnez a0, .LBB13_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 4
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB13_14
+; RV64-NEXT:  .LBB13_13:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_10:
-; RV64-NEXT:    fsw ft1, 16(sp)
+; RV64-NEXT:  .LBB13_14:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB13_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 3
-; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    j .LBB13_17
+; RV64-NEXT:  .LBB13_16:
+; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_12:
-; RV64-NEXT:    fsw ft1, 12(sp)
+; RV64-NEXT:  .LBB13_17:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 12(sp)
+; RV64-NEXT:    bnez a0, .LBB13_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 2
-; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_14:
-; RV64-NEXT:    fsw ft1, 8(sp)
+; RV64-NEXT:    j .LBB13_20
+; RV64-NEXT:  .LBB13_19:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    vslidedown.vi v26, v8, 2
+; RV64-NEXT:  .LBB13_20:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 8(sp)
+; RV64-NEXT:    bnez a0, .LBB13_22
+; RV64-NEXT:  # %bb.21:
+; RV64-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    j .LBB13_23
+; RV64-NEXT:  .LBB13_22:
+; RV64-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB13_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB13_16:
-; RV64-NEXT:    fsw ft1, 4(sp)
+; RV64-NEXT:  .LBB13_23:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsw ft0, 4(sp)
 ; RV64-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; RV64-NEXT:    vle32.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   %v = select i1 %cmp, <8 x float> %c, <8 x float> %d
   ret <8 x float> %v
 }
 
 define <16 x float> @select_v16f32(i1 zeroext %c, <16 x float> %a, <16 x float> %b) {
 ; RV32-LABEL: select_v16f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -128
 ; RV32-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 128
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -64
-; RV32-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v12
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB14_2
+; RV32-NEXT:    bnez a0, .LBB14_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.s ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v12
+; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB14_4
 ; RV32-NEXT:  .LBB14_2:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v8, 15
+; RV32-NEXT:    j .LBB14_5
+; RV32-NEXT:  .LBB14_3:
+; RV32-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB14_2
+; RV32-NEXT:  .LBB14_4:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 15
+; RV32-NEXT:  .LBB14_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 15
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_4:
-; RV32-NEXT:    fsw ft1, 60(sp)
+; RV32-NEXT:    fsw ft0, 60(sp)
+; RV32-NEXT:    bnez a0, .LBB14_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 14
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_8
+; RV32-NEXT:  .LBB14_7:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 14
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_6:
-; RV32-NEXT:    fsw ft1, 56(sp)
+; RV32-NEXT:  .LBB14_8:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 56(sp)
+; RV32-NEXT:    bnez a0, .LBB14_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 13
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_11
+; RV32-NEXT:  .LBB14_10:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 13
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_8:
-; RV32-NEXT:    fsw ft1, 52(sp)
+; RV32-NEXT:  .LBB14_11:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 52(sp)
+; RV32-NEXT:    bnez a0, .LBB14_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 12
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_14
+; RV32-NEXT:  .LBB14_13:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 12
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_10:
-; RV32-NEXT:    fsw ft1, 48(sp)
+; RV32-NEXT:  .LBB14_14:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 48(sp)
+; RV32-NEXT:    bnez a0, .LBB14_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 11
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_17
+; RV32-NEXT:  .LBB14_16:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 11
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_12:
-; RV32-NEXT:    fsw ft1, 44(sp)
+; RV32-NEXT:  .LBB14_17:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 44(sp)
+; RV32-NEXT:    bnez a0, .LBB14_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 10
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_20
+; RV32-NEXT:  .LBB14_19:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 10
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_14:
-; RV32-NEXT:    fsw ft1, 40(sp)
+; RV32-NEXT:  .LBB14_20:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 40(sp)
+; RV32-NEXT:    bnez a0, .LBB14_22
+; RV32-NEXT:  # %bb.21:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 9
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_23
+; RV32-NEXT:  .LBB14_22:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 9
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_16:
-; RV32-NEXT:    fsw ft1, 36(sp)
+; RV32-NEXT:  .LBB14_23:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 36(sp)
+; RV32-NEXT:    bnez a0, .LBB14_25
+; RV32-NEXT:  # %bb.24:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 8
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_26
+; RV32-NEXT:  .LBB14_25:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 8
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_18
-; RV32-NEXT:  # %bb.17:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_18:
-; RV32-NEXT:    fsw ft1, 32(sp)
+; RV32-NEXT:  .LBB14_26:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 32(sp)
+; RV32-NEXT:    bnez a0, .LBB14_28
+; RV32-NEXT:  # %bb.27:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 7
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_29
+; RV32-NEXT:  .LBB14_28:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_20
-; RV32-NEXT:  # %bb.19:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_20:
-; RV32-NEXT:    fsw ft1, 28(sp)
+; RV32-NEXT:  .LBB14_29:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 28(sp)
+; RV32-NEXT:    bnez a0, .LBB14_31
+; RV32-NEXT:  # %bb.30:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 6
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_32
+; RV32-NEXT:  .LBB14_31:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_22
-; RV32-NEXT:  # %bb.21:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_22:
-; RV32-NEXT:    fsw ft1, 24(sp)
+; RV32-NEXT:  .LBB14_32:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB14_34
+; RV32-NEXT:  # %bb.33:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 5
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_35
+; RV32-NEXT:  .LBB14_34:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_24
-; RV32-NEXT:  # %bb.23:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_24:
-; RV32-NEXT:    fsw ft1, 20(sp)
+; RV32-NEXT:  .LBB14_35:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 20(sp)
+; RV32-NEXT:    bnez a0, .LBB14_37
+; RV32-NEXT:  # %bb.36:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 4
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_38
+; RV32-NEXT:  .LBB14_37:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_26
-; RV32-NEXT:  # %bb.25:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_26:
-; RV32-NEXT:    fsw ft1, 16(sp)
+; RV32-NEXT:  .LBB14_38:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB14_40
+; RV32-NEXT:  # %bb.39:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 3
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB14_41
+; RV32-NEXT:  .LBB14_40:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_28
-; RV32-NEXT:  # %bb.27:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_28:
-; RV32-NEXT:    fsw ft1, 12(sp)
+; RV32-NEXT:  .LBB14_41:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 12(sp)
+; RV32-NEXT:    bnez a0, .LBB14_43
+; RV32-NEXT:  # %bb.42:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 2
-; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_30
-; RV32-NEXT:  # %bb.29:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_30:
-; RV32-NEXT:    fsw ft1, 8(sp)
+; RV32-NEXT:    j .LBB14_44
+; RV32-NEXT:  .LBB14_43:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
-; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    vslidedown.vi v28, v8, 2
+; RV32-NEXT:  .LBB14_44:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 8(sp)
+; RV32-NEXT:    bnez a0, .LBB14_46
+; RV32-NEXT:  # %bb.45:
+; RV32-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    j .LBB14_47
+; RV32-NEXT:  .LBB14_46:
+; RV32-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB14_32
-; RV32-NEXT:  # %bb.31:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB14_32:
-; RV32-NEXT:    fsw ft1, 4(sp)
+; RV32-NEXT:  .LBB14_47:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 4(sp)
 ; RV32-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV32-NEXT:    vle32.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -128
 ; RV32-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 128
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_v16f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -128
 ; RV64-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 128
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -64
-; RV64-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v12
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB14_2
+; RV64-NEXT:    bnez a0, .LBB14_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.s ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v12
+; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB14_4
 ; RV64-NEXT:  .LBB14_2:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v8, 15
+; RV64-NEXT:    j .LBB14_5
+; RV64-NEXT:  .LBB14_3:
+; RV64-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB14_2
+; RV64-NEXT:  .LBB14_4:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 15
+; RV64-NEXT:  .LBB14_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 15
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_4:
-; RV64-NEXT:    fsw ft1, 60(sp)
+; RV64-NEXT:    fsw ft0, 60(sp)
+; RV64-NEXT:    bnez a0, .LBB14_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 14
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_8
+; RV64-NEXT:  .LBB14_7:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 14
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_6:
-; RV64-NEXT:    fsw ft1, 56(sp)
+; RV64-NEXT:  .LBB14_8:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 56(sp)
+; RV64-NEXT:    bnez a0, .LBB14_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 13
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_11
+; RV64-NEXT:  .LBB14_10:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 13
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_8:
-; RV64-NEXT:    fsw ft1, 52(sp)
+; RV64-NEXT:  .LBB14_11:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 52(sp)
+; RV64-NEXT:    bnez a0, .LBB14_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 12
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_14
+; RV64-NEXT:  .LBB14_13:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 12
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_10:
-; RV64-NEXT:    fsw ft1, 48(sp)
+; RV64-NEXT:  .LBB14_14:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 48(sp)
+; RV64-NEXT:    bnez a0, .LBB14_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 11
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_17
+; RV64-NEXT:  .LBB14_16:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 11
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_12:
-; RV64-NEXT:    fsw ft1, 44(sp)
+; RV64-NEXT:  .LBB14_17:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 44(sp)
+; RV64-NEXT:    bnez a0, .LBB14_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 10
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_20
+; RV64-NEXT:  .LBB14_19:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 10
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_14:
-; RV64-NEXT:    fsw ft1, 40(sp)
+; RV64-NEXT:  .LBB14_20:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 40(sp)
+; RV64-NEXT:    bnez a0, .LBB14_22
+; RV64-NEXT:  # %bb.21:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 9
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_23
+; RV64-NEXT:  .LBB14_22:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 9
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_16:
-; RV64-NEXT:    fsw ft1, 36(sp)
+; RV64-NEXT:  .LBB14_23:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 36(sp)
+; RV64-NEXT:    bnez a0, .LBB14_25
+; RV64-NEXT:  # %bb.24:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 8
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_26
+; RV64-NEXT:  .LBB14_25:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 8
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_18
-; RV64-NEXT:  # %bb.17:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_18:
-; RV64-NEXT:    fsw ft1, 32(sp)
+; RV64-NEXT:  .LBB14_26:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 32(sp)
+; RV64-NEXT:    bnez a0, .LBB14_28
+; RV64-NEXT:  # %bb.27:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 7
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_29
+; RV64-NEXT:  .LBB14_28:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_20
-; RV64-NEXT:  # %bb.19:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_20:
-; RV64-NEXT:    fsw ft1, 28(sp)
+; RV64-NEXT:  .LBB14_29:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 28(sp)
+; RV64-NEXT:    bnez a0, .LBB14_31
+; RV64-NEXT:  # %bb.30:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 6
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_32
+; RV64-NEXT:  .LBB14_31:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_22
-; RV64-NEXT:  # %bb.21:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_22:
-; RV64-NEXT:    fsw ft1, 24(sp)
+; RV64-NEXT:  .LBB14_32:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB14_34
+; RV64-NEXT:  # %bb.33:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 5
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_35
+; RV64-NEXT:  .LBB14_34:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_24
-; RV64-NEXT:  # %bb.23:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_24:
-; RV64-NEXT:    fsw ft1, 20(sp)
+; RV64-NEXT:  .LBB14_35:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 20(sp)
+; RV64-NEXT:    bnez a0, .LBB14_37
+; RV64-NEXT:  # %bb.36:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 4
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_38
+; RV64-NEXT:  .LBB14_37:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_26
-; RV64-NEXT:  # %bb.25:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_26:
-; RV64-NEXT:    fsw ft1, 16(sp)
+; RV64-NEXT:  .LBB14_38:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB14_40
+; RV64-NEXT:  # %bb.39:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 3
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB14_41
+; RV64-NEXT:  .LBB14_40:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_28
-; RV64-NEXT:  # %bb.27:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_28:
-; RV64-NEXT:    fsw ft1, 12(sp)
+; RV64-NEXT:  .LBB14_41:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 12(sp)
+; RV64-NEXT:    bnez a0, .LBB14_43
+; RV64-NEXT:  # %bb.42:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 2
-; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_30
-; RV64-NEXT:  # %bb.29:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_30:
-; RV64-NEXT:    fsw ft1, 8(sp)
+; RV64-NEXT:    j .LBB14_44
+; RV64-NEXT:  .LBB14_43:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
-; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    vslidedown.vi v28, v8, 2
+; RV64-NEXT:  .LBB14_44:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 8(sp)
+; RV64-NEXT:    bnez a0, .LBB14_46
+; RV64-NEXT:  # %bb.45:
+; RV64-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    j .LBB14_47
+; RV64-NEXT:  .LBB14_46:
+; RV64-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB14_32
-; RV64-NEXT:  # %bb.31:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB14_32:
-; RV64-NEXT:    fsw ft1, 4(sp)
+; RV64-NEXT:  .LBB14_47:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 4(sp)
 ; RV64-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV64-NEXT:    vle32.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -128
 ; RV64-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 128
 ; RV64-NEXT:    ret
   %v = select i1 %c, <16 x float> %a, <16 x float> %b
   ret <16 x float> %v
 }
 
 define <16 x float> @selectcc_v16f32(float %a, float %b, <16 x float> %c, <16 x float> %d) {
 ; RV32-LABEL: selectcc_v16f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -128
 ; RV32-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 128
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -64
 ; RV32-NEXT:    feq.s a0, fa0, fa1
-; RV32-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v12
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB15_2
+; RV32-NEXT:    bnez a0, .LBB15_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.s ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v12
+; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB15_4
 ; RV32-NEXT:  .LBB15_2:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v8, 15
+; RV32-NEXT:    j .LBB15_5
+; RV32-NEXT:  .LBB15_3:
+; RV32-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsw ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB15_2
+; RV32-NEXT:  .LBB15_4:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 15
+; RV32-NEXT:  .LBB15_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 15
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_4:
-; RV32-NEXT:    fsw ft1, 60(sp)
+; RV32-NEXT:    fsw ft0, 60(sp)
+; RV32-NEXT:    bnez a0, .LBB15_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 14
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_8
+; RV32-NEXT:  .LBB15_7:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 14
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_6:
-; RV32-NEXT:    fsw ft1, 56(sp)
+; RV32-NEXT:  .LBB15_8:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 56(sp)
+; RV32-NEXT:    bnez a0, .LBB15_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 13
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_11
+; RV32-NEXT:  .LBB15_10:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 13
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_8:
-; RV32-NEXT:    fsw ft1, 52(sp)
+; RV32-NEXT:  .LBB15_11:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 52(sp)
+; RV32-NEXT:    bnez a0, .LBB15_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 12
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_14
+; RV32-NEXT:  .LBB15_13:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 12
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_10:
-; RV32-NEXT:    fsw ft1, 48(sp)
+; RV32-NEXT:  .LBB15_14:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 48(sp)
+; RV32-NEXT:    bnez a0, .LBB15_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 11
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_17
+; RV32-NEXT:  .LBB15_16:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 11
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_12:
-; RV32-NEXT:    fsw ft1, 44(sp)
+; RV32-NEXT:  .LBB15_17:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 44(sp)
+; RV32-NEXT:    bnez a0, .LBB15_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 10
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_20
+; RV32-NEXT:  .LBB15_19:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 10
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_14:
-; RV32-NEXT:    fsw ft1, 40(sp)
+; RV32-NEXT:  .LBB15_20:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 40(sp)
+; RV32-NEXT:    bnez a0, .LBB15_22
+; RV32-NEXT:  # %bb.21:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 9
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_23
+; RV32-NEXT:  .LBB15_22:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 9
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_16:
-; RV32-NEXT:    fsw ft1, 36(sp)
+; RV32-NEXT:  .LBB15_23:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 36(sp)
+; RV32-NEXT:    bnez a0, .LBB15_25
+; RV32-NEXT:  # %bb.24:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 8
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_26
+; RV32-NEXT:  .LBB15_25:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 8
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_18
-; RV32-NEXT:  # %bb.17:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_18:
-; RV32-NEXT:    fsw ft1, 32(sp)
+; RV32-NEXT:  .LBB15_26:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 32(sp)
+; RV32-NEXT:    bnez a0, .LBB15_28
+; RV32-NEXT:  # %bb.27:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 7
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_29
+; RV32-NEXT:  .LBB15_28:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_20
-; RV32-NEXT:  # %bb.19:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_20:
-; RV32-NEXT:    fsw ft1, 28(sp)
+; RV32-NEXT:  .LBB15_29:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 28(sp)
+; RV32-NEXT:    bnez a0, .LBB15_31
+; RV32-NEXT:  # %bb.30:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 6
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_32
+; RV32-NEXT:  .LBB15_31:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_22
-; RV32-NEXT:  # %bb.21:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_22:
-; RV32-NEXT:    fsw ft1, 24(sp)
+; RV32-NEXT:  .LBB15_32:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB15_34
+; RV32-NEXT:  # %bb.33:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 5
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_35
+; RV32-NEXT:  .LBB15_34:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_24
-; RV32-NEXT:  # %bb.23:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_24:
-; RV32-NEXT:    fsw ft1, 20(sp)
+; RV32-NEXT:  .LBB15_35:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 20(sp)
+; RV32-NEXT:    bnez a0, .LBB15_37
+; RV32-NEXT:  # %bb.36:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 4
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_38
+; RV32-NEXT:  .LBB15_37:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_26
-; RV32-NEXT:  # %bb.25:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_26:
-; RV32-NEXT:    fsw ft1, 16(sp)
+; RV32-NEXT:  .LBB15_38:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB15_40
+; RV32-NEXT:  # %bb.39:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 3
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB15_41
+; RV32-NEXT:  .LBB15_40:
+; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_28
-; RV32-NEXT:  # %bb.27:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_28:
-; RV32-NEXT:    fsw ft1, 12(sp)
+; RV32-NEXT:  .LBB15_41:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 12(sp)
+; RV32-NEXT:    bnez a0, .LBB15_43
+; RV32-NEXT:  # %bb.42:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 2
-; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_30
-; RV32-NEXT:  # %bb.29:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_30:
-; RV32-NEXT:    fsw ft1, 8(sp)
+; RV32-NEXT:    j .LBB15_44
+; RV32-NEXT:  .LBB15_43:
 ; RV32-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
-; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    vslidedown.vi v28, v8, 2
+; RV32-NEXT:  .LBB15_44:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 8(sp)
+; RV32-NEXT:    bnez a0, .LBB15_46
+; RV32-NEXT:  # %bb.45:
+; RV32-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    j .LBB15_47
+; RV32-NEXT:  .LBB15_46:
+; RV32-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB15_32
-; RV32-NEXT:  # %bb.31:
-; RV32-NEXT:    fmv.s ft1, ft0
-; RV32-NEXT:  .LBB15_32:
-; RV32-NEXT:    fsw ft1, 4(sp)
+; RV32-NEXT:  .LBB15_47:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsw ft0, 4(sp)
 ; RV32-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV32-NEXT:    vle32.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -128
 ; RV32-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 128
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selectcc_v16f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -128
 ; RV64-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 128
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -64
 ; RV64-NEXT:    feq.s a0, fa0, fa1
-; RV64-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v12
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB15_2
+; RV64-NEXT:    bnez a0, .LBB15_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.s ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v12
+; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB15_4
 ; RV64-NEXT:  .LBB15_2:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v8, 15
+; RV64-NEXT:    j .LBB15_5
+; RV64-NEXT:  .LBB15_3:
+; RV64-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsw ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB15_2
+; RV64-NEXT:  .LBB15_4:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 15
+; RV64-NEXT:  .LBB15_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 15
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_4:
-; RV64-NEXT:    fsw ft1, 60(sp)
+; RV64-NEXT:    fsw ft0, 60(sp)
+; RV64-NEXT:    bnez a0, .LBB15_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 14
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_8
+; RV64-NEXT:  .LBB15_7:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 14
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_6:
-; RV64-NEXT:    fsw ft1, 56(sp)
+; RV64-NEXT:  .LBB15_8:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 56(sp)
+; RV64-NEXT:    bnez a0, .LBB15_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 13
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_11
+; RV64-NEXT:  .LBB15_10:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 13
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_8:
-; RV64-NEXT:    fsw ft1, 52(sp)
+; RV64-NEXT:  .LBB15_11:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 52(sp)
+; RV64-NEXT:    bnez a0, .LBB15_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 12
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_14
+; RV64-NEXT:  .LBB15_13:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 12
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_10:
-; RV64-NEXT:    fsw ft1, 48(sp)
+; RV64-NEXT:  .LBB15_14:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 48(sp)
+; RV64-NEXT:    bnez a0, .LBB15_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 11
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_17
+; RV64-NEXT:  .LBB15_16:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 11
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_12:
-; RV64-NEXT:    fsw ft1, 44(sp)
+; RV64-NEXT:  .LBB15_17:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 44(sp)
+; RV64-NEXT:    bnez a0, .LBB15_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 10
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_20
+; RV64-NEXT:  .LBB15_19:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 10
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_14:
-; RV64-NEXT:    fsw ft1, 40(sp)
+; RV64-NEXT:  .LBB15_20:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 40(sp)
+; RV64-NEXT:    bnez a0, .LBB15_22
+; RV64-NEXT:  # %bb.21:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 9
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_23
+; RV64-NEXT:  .LBB15_22:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 9
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_16:
-; RV64-NEXT:    fsw ft1, 36(sp)
+; RV64-NEXT:  .LBB15_23:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 36(sp)
+; RV64-NEXT:    bnez a0, .LBB15_25
+; RV64-NEXT:  # %bb.24:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 8
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_26
+; RV64-NEXT:  .LBB15_25:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 8
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_18
-; RV64-NEXT:  # %bb.17:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_18:
-; RV64-NEXT:    fsw ft1, 32(sp)
+; RV64-NEXT:  .LBB15_26:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 32(sp)
+; RV64-NEXT:    bnez a0, .LBB15_28
+; RV64-NEXT:  # %bb.27:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 7
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_29
+; RV64-NEXT:  .LBB15_28:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_20
-; RV64-NEXT:  # %bb.19:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_20:
-; RV64-NEXT:    fsw ft1, 28(sp)
+; RV64-NEXT:  .LBB15_29:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 28(sp)
+; RV64-NEXT:    bnez a0, .LBB15_31
+; RV64-NEXT:  # %bb.30:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 6
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_32
+; RV64-NEXT:  .LBB15_31:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_22
-; RV64-NEXT:  # %bb.21:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_22:
-; RV64-NEXT:    fsw ft1, 24(sp)
+; RV64-NEXT:  .LBB15_32:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB15_34
+; RV64-NEXT:  # %bb.33:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 5
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_35
+; RV64-NEXT:  .LBB15_34:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_24
-; RV64-NEXT:  # %bb.23:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_24:
-; RV64-NEXT:    fsw ft1, 20(sp)
+; RV64-NEXT:  .LBB15_35:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 20(sp)
+; RV64-NEXT:    bnez a0, .LBB15_37
+; RV64-NEXT:  # %bb.36:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 4
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_38
+; RV64-NEXT:  .LBB15_37:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_26
-; RV64-NEXT:  # %bb.25:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_26:
-; RV64-NEXT:    fsw ft1, 16(sp)
+; RV64-NEXT:  .LBB15_38:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB15_40
+; RV64-NEXT:  # %bb.39:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 3
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB15_41
+; RV64-NEXT:  .LBB15_40:
+; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_28
-; RV64-NEXT:  # %bb.27:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_28:
-; RV64-NEXT:    fsw ft1, 12(sp)
+; RV64-NEXT:  .LBB15_41:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 12(sp)
+; RV64-NEXT:    bnez a0, .LBB15_43
+; RV64-NEXT:  # %bb.42:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 2
-; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_30
-; RV64-NEXT:  # %bb.29:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_30:
-; RV64-NEXT:    fsw ft1, 8(sp)
+; RV64-NEXT:    j .LBB15_44
+; RV64-NEXT:  .LBB15_43:
 ; RV64-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
-; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    vslidedown.vi v28, v8, 2
+; RV64-NEXT:  .LBB15_44:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 8(sp)
+; RV64-NEXT:    bnez a0, .LBB15_46
+; RV64-NEXT:  # %bb.45:
+; RV64-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    j .LBB15_47
+; RV64-NEXT:  .LBB15_46:
+; RV64-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB15_32
-; RV64-NEXT:  # %bb.31:
-; RV64-NEXT:    fmv.s ft1, ft0
-; RV64-NEXT:  .LBB15_32:
-; RV64-NEXT:    fsw ft1, 4(sp)
+; RV64-NEXT:  .LBB15_47:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsw ft0, 4(sp)
 ; RV64-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV64-NEXT:    vle32.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -128
 ; RV64-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 128
 ; RV64-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   %v = select i1 %cmp, <16 x float> %c, <16 x float> %d
   ret <16 x float> %v
 }
 
 define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: select_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vfmv.f.s ft1, v9
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    vslidedown.vi v25, v9, 1
-; CHECK-NEXT:    vfmv.f.s ft3, v25
-; CHECK-NEXT:    vslidedown.vi v25, v8, 1
-; CHECK-NEXT:    vfmv.f.s ft2, v25
 ; CHECK-NEXT:    bnez a0, .LBB16_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.d ft0, ft1
-; CHECK-NEXT:    fmv.d ft2, ft3
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    vsetivli a0, 1, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v9, 1
+; CHECK-NEXT:    j .LBB16_3
 ; CHECK-NEXT:  .LBB16_2:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
+; CHECK-NEXT:    vsetivli a0, 1, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 1
+; CHECK-NEXT:  .LBB16_3:
+; CHECK-NEXT:    vfmv.f.s ft1, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; CHECK-NEXT:    vfmv.v.f v8, ft2
+; CHECK-NEXT:    vfmv.v.f v8, ft1
 ; CHECK-NEXT:    vfmv.s.f v8, ft0
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <2 x double> %a, <2 x double> %b
   ret <2 x double> %v
 }
 
 define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d) {
 ; CHECK-LABEL: selectcc_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.d a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB17_2
+; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v9, 1
-; CHECK-NEXT:    vfmv.f.s ft1, v25
+; CHECK-NEXT:    j .LBB17_3
+; CHECK-NEXT:  .LBB17_2:
+; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 1
+; CHECK-NEXT:  .LBB17_3:
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
-; CHECK-NEXT:    bnez a0, .LBB17_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    fmv.d ft0, ft1
-; CHECK-NEXT:  .LBB17_2:
 ; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
-; CHECK-NEXT:    vfmv.f.s ft1, v9
+; CHECK-NEXT:    bnez a0, .LBB17_5
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s ft0, v9
+; CHECK-NEXT:    j .LBB17_6
+; CHECK-NEXT:  .LBB17_5:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    bnez a0, .LBB17_4
-; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    fmv.d ft0, ft1
-; CHECK-NEXT:  .LBB17_4:
+; CHECK-NEXT:  .LBB17_6:
 ; CHECK-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.s.f v25, ft0
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   %v = select i1 %cmp, <2 x double> %c, <2 x double> %d
   ret <2 x double> %v
 }
 
 define <4 x double> @select_v4f64(i1 zeroext %c, <4 x double> %a, <4 x double> %b) {
 ; RV32-LABEL: select_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -64
 ; RV32-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 64
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
-; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB18_2
+; RV32-NEXT:    bnez a0, .LBB18_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.d ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v10
+; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB18_4
 ; RV32-NEXT:  .LBB18_2:
+; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v8, 3
+; RV32-NEXT:    j .LBB18_5
+; RV32-NEXT:  .LBB18_3:
+; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB18_2
+; RV32-NEXT:  .LBB18_4:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 3
+; RV32-NEXT:  .LBB18_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB18_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB18_4:
-; RV32-NEXT:    fsd ft1, 24(sp)
+; RV32-NEXT:    fsd ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB18_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 2
-; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB18_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB18_6:
-; RV32-NEXT:    fsd ft1, 16(sp)
+; RV32-NEXT:    j .LBB18_8
+; RV32-NEXT:  .LBB18_7:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    vslidedown.vi v26, v8, 2
+; RV32-NEXT:  .LBB18_8:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsd ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB18_10
+; RV32-NEXT:  # %bb.9:
+; RV32-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    j .LBB18_11
+; RV32-NEXT:  .LBB18_10:
+; RV32-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB18_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB18_8:
-; RV32-NEXT:    fsd ft1, 8(sp)
+; RV32-NEXT:  .LBB18_11:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsd ft0, 8(sp)
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -64
 ; RV32-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 64
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
 ; RV64-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 64
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB18_2
+; RV64-NEXT:    bnez a0, .LBB18_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.d ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v10
+; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB18_4
 ; RV64-NEXT:  .LBB18_2:
+; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v8, 3
+; RV64-NEXT:    j .LBB18_5
+; RV64-NEXT:  .LBB18_3:
+; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB18_2
+; RV64-NEXT:  .LBB18_4:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 3
+; RV64-NEXT:  .LBB18_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB18_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB18_4:
-; RV64-NEXT:    fsd ft1, 24(sp)
+; RV64-NEXT:    fsd ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB18_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 2
-; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB18_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB18_6:
-; RV64-NEXT:    fsd ft1, 16(sp)
+; RV64-NEXT:    j .LBB18_8
+; RV64-NEXT:  .LBB18_7:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    vslidedown.vi v26, v8, 2
+; RV64-NEXT:  .LBB18_8:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsd ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB18_10
+; RV64-NEXT:  # %bb.9:
+; RV64-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    j .LBB18_11
+; RV64-NEXT:  .LBB18_10:
+; RV64-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB18_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB18_8:
-; RV64-NEXT:    fsd ft1, 8(sp)
+; RV64-NEXT:  .LBB18_11:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsd ft0, 8(sp)
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
   %v = select i1 %c, <4 x double> %a, <4 x double> %b
   ret <4 x double> %v
 }
 
 define <4 x double> @selectcc_v4f64(double %a, double %b, <4 x double> %c, <4 x double> %d) {
 ; RV32-LABEL: selectcc_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -64
 ; RV32-NEXT:    .cfi_def_cfa_offset 64
 ; RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 64
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
 ; RV32-NEXT:    feq.d a0, fa0, fa1
-; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v10
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB19_2
+; RV32-NEXT:    bnez a0, .LBB19_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.d ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v10
+; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB19_4
 ; RV32-NEXT:  .LBB19_2:
+; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v8, 3
+; RV32-NEXT:    j .LBB19_5
+; RV32-NEXT:  .LBB19_3:
+; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB19_2
+; RV32-NEXT:  .LBB19_4:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 3
+; RV32-NEXT:  .LBB19_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB19_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB19_4:
-; RV32-NEXT:    fsd ft1, 24(sp)
+; RV32-NEXT:    fsd ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB19_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v10, 2
-; RV32-NEXT:    vfmv.f.s ft0, v26
-; RV32-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB19_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB19_6:
-; RV32-NEXT:    fsd ft1, 16(sp)
+; RV32-NEXT:    j .LBB19_8
+; RV32-NEXT:  .LBB19_7:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    vslidedown.vi v26, v8, 2
+; RV32-NEXT:  .LBB19_8:
 ; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsd ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB19_10
+; RV32-NEXT:  # %bb.9:
+; RV32-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
+; RV32-NEXT:    vslidedown.vi v26, v10, 1
+; RV32-NEXT:    j .LBB19_11
+; RV32-NEXT:  .LBB19_10:
+; RV32-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v26
-; RV32-NEXT:    bnez a0, .LBB19_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB19_8:
-; RV32-NEXT:    fsd ft1, 8(sp)
+; RV32-NEXT:  .LBB19_11:
+; RV32-NEXT:    vfmv.f.s ft0, v26
+; RV32-NEXT:    fsd ft0, 8(sp)
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -64
 ; RV32-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 64
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selectcc_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
 ; RV64-NEXT:    .cfi_def_cfa_offset 64
 ; RV64-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 64
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
 ; RV64-NEXT:    feq.d a0, fa0, fa1
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v10
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB19_2
+; RV64-NEXT:    bnez a0, .LBB19_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.d ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v10
+; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB19_4
 ; RV64-NEXT:  .LBB19_2:
+; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v8, 3
+; RV64-NEXT:    j .LBB19_5
+; RV64-NEXT:  .LBB19_3:
+; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB19_2
+; RV64-NEXT:  .LBB19_4:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 3
+; RV64-NEXT:  .LBB19_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB19_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB19_4:
-; RV64-NEXT:    fsd ft1, 24(sp)
+; RV64-NEXT:    fsd ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB19_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 2
-; RV64-NEXT:    vfmv.f.s ft0, v26
-; RV64-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB19_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB19_6:
-; RV64-NEXT:    fsd ft1, 16(sp)
+; RV64-NEXT:    j .LBB19_8
+; RV64-NEXT:  .LBB19_7:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    vslidedown.vi v26, v8, 2
+; RV64-NEXT:  .LBB19_8:
 ; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsd ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB19_10
+; RV64-NEXT:  # %bb.9:
+; RV64-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
+; RV64-NEXT:    vslidedown.vi v26, v10, 1
+; RV64-NEXT:    j .LBB19_11
+; RV64-NEXT:  .LBB19_10:
+; RV64-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v26
-; RV64-NEXT:    bnez a0, .LBB19_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB19_8:
-; RV64-NEXT:    fsd ft1, 8(sp)
+; RV64-NEXT:  .LBB19_11:
+; RV64-NEXT:    vfmv.f.s ft0, v26
+; RV64-NEXT:    fsd ft0, 8(sp)
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -64
 ; RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 64
 ; RV64-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   %v = select i1 %cmp, <4 x double> %c, <4 x double> %d
   ret <4 x double> %v
 }
 
 define <8 x double> @select_v8f64(i1 zeroext %c, <8 x double> %a, <8 x double> %b) {
 ; RV32-LABEL: select_v8f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -128
 ; RV32-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 128
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -64
-; RV32-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v12
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB20_2
+; RV32-NEXT:    bnez a0, .LBB20_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.d ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v12
+; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB20_4
 ; RV32-NEXT:  .LBB20_2:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v8, 7
+; RV32-NEXT:    j .LBB20_5
+; RV32-NEXT:  .LBB20_3:
+; RV32-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB20_2
+; RV32-NEXT:  .LBB20_4:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 7
+; RV32-NEXT:  .LBB20_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_4:
-; RV32-NEXT:    fsd ft1, 56(sp)
+; RV32-NEXT:    fsd ft0, 56(sp)
+; RV32-NEXT:    bnez a0, .LBB20_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 6
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB20_8
+; RV32-NEXT:  .LBB20_7:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_6:
-; RV32-NEXT:    fsd ft1, 48(sp)
+; RV32-NEXT:  .LBB20_8:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 48(sp)
+; RV32-NEXT:    bnez a0, .LBB20_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 5
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB20_11
+; RV32-NEXT:  .LBB20_10:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_8:
-; RV32-NEXT:    fsd ft1, 40(sp)
+; RV32-NEXT:  .LBB20_11:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 40(sp)
+; RV32-NEXT:    bnez a0, .LBB20_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 4
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB20_14
+; RV32-NEXT:  .LBB20_13:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_10:
-; RV32-NEXT:    fsd ft1, 32(sp)
+; RV32-NEXT:  .LBB20_14:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 32(sp)
+; RV32-NEXT:    bnez a0, .LBB20_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 3
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB20_17
+; RV32-NEXT:  .LBB20_16:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_12:
-; RV32-NEXT:    fsd ft1, 24(sp)
+; RV32-NEXT:  .LBB20_17:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB20_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 2
-; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_14:
-; RV32-NEXT:    fsd ft1, 16(sp)
+; RV32-NEXT:    j .LBB20_20
+; RV32-NEXT:  .LBB20_19:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
-; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    vslidedown.vi v28, v8, 2
+; RV32-NEXT:  .LBB20_20:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB20_22
+; RV32-NEXT:  # %bb.21:
+; RV32-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    j .LBB20_23
+; RV32-NEXT:  .LBB20_22:
+; RV32-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB20_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB20_16:
-; RV32-NEXT:    fsd ft1, 8(sp)
+; RV32-NEXT:  .LBB20_23:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 8(sp)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -128
 ; RV32-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 128
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_v8f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -128
 ; RV64-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 128
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -64
-; RV64-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v12
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB20_2
+; RV64-NEXT:    bnez a0, .LBB20_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.d ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v12
+; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB20_4
 ; RV64-NEXT:  .LBB20_2:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v8, 7
+; RV64-NEXT:    j .LBB20_5
+; RV64-NEXT:  .LBB20_3:
+; RV64-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB20_2
+; RV64-NEXT:  .LBB20_4:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 7
+; RV64-NEXT:  .LBB20_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_4:
-; RV64-NEXT:    fsd ft1, 56(sp)
+; RV64-NEXT:    fsd ft0, 56(sp)
+; RV64-NEXT:    bnez a0, .LBB20_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 6
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB20_8
+; RV64-NEXT:  .LBB20_7:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_6:
-; RV64-NEXT:    fsd ft1, 48(sp)
+; RV64-NEXT:  .LBB20_8:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 48(sp)
+; RV64-NEXT:    bnez a0, .LBB20_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 5
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB20_11
+; RV64-NEXT:  .LBB20_10:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_8:
-; RV64-NEXT:    fsd ft1, 40(sp)
+; RV64-NEXT:  .LBB20_11:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 40(sp)
+; RV64-NEXT:    bnez a0, .LBB20_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 4
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB20_14
+; RV64-NEXT:  .LBB20_13:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_10:
-; RV64-NEXT:    fsd ft1, 32(sp)
+; RV64-NEXT:  .LBB20_14:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 32(sp)
+; RV64-NEXT:    bnez a0, .LBB20_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 3
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB20_17
+; RV64-NEXT:  .LBB20_16:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_12:
-; RV64-NEXT:    fsd ft1, 24(sp)
+; RV64-NEXT:  .LBB20_17:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB20_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 2
-; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_14:
-; RV64-NEXT:    fsd ft1, 16(sp)
+; RV64-NEXT:    j .LBB20_20
+; RV64-NEXT:  .LBB20_19:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
-; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    vslidedown.vi v28, v8, 2
+; RV64-NEXT:  .LBB20_20:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB20_22
+; RV64-NEXT:  # %bb.21:
+; RV64-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    j .LBB20_23
+; RV64-NEXT:  .LBB20_22:
+; RV64-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB20_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB20_16:
-; RV64-NEXT:    fsd ft1, 8(sp)
+; RV64-NEXT:  .LBB20_23:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 8(sp)
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -128
 ; RV64-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 128
 ; RV64-NEXT:    ret
   %v = select i1 %c, <8 x double> %a, <8 x double> %b
   ret <8 x double> %v
 }
 
 define <8 x double> @selectcc_v8f64(double %a, double %b, <8 x double> %c, <8 x double> %d) {
 ; RV32-LABEL: selectcc_v8f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -128
 ; RV32-NEXT:    .cfi_def_cfa_offset 128
 ; RV32-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 128
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -64
 ; RV32-NEXT:    feq.d a0, fa0, fa1
-; RV32-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v12
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB21_2
+; RV32-NEXT:    bnez a0, .LBB21_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.d ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v12
+; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB21_4
 ; RV32-NEXT:  .LBB21_2:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v8, 7
+; RV32-NEXT:    j .LBB21_5
+; RV32-NEXT:  .LBB21_3:
+; RV32-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB21_2
+; RV32-NEXT:  .LBB21_4:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 7
+; RV32-NEXT:  .LBB21_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_4:
-; RV32-NEXT:    fsd ft1, 56(sp)
+; RV32-NEXT:    fsd ft0, 56(sp)
+; RV32-NEXT:    bnez a0, .LBB21_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 6
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB21_8
+; RV32-NEXT:  .LBB21_7:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_6:
-; RV32-NEXT:    fsd ft1, 48(sp)
+; RV32-NEXT:  .LBB21_8:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 48(sp)
+; RV32-NEXT:    bnez a0, .LBB21_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 5
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB21_11
+; RV32-NEXT:  .LBB21_10:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_8:
-; RV32-NEXT:    fsd ft1, 40(sp)
+; RV32-NEXT:  .LBB21_11:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 40(sp)
+; RV32-NEXT:    bnez a0, .LBB21_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 4
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB21_14
+; RV32-NEXT:  .LBB21_13:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_10:
-; RV32-NEXT:    fsd ft1, 32(sp)
+; RV32-NEXT:  .LBB21_14:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 32(sp)
+; RV32-NEXT:    bnez a0, .LBB21_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 3
-; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    j .LBB21_17
+; RV32-NEXT:  .LBB21_16:
+; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_12:
-; RV32-NEXT:    fsd ft1, 24(sp)
+; RV32-NEXT:  .LBB21_17:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB21_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v12, 2
-; RV32-NEXT:    vfmv.f.s ft0, v28
-; RV32-NEXT:    vslidedown.vi v28, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_14:
-; RV32-NEXT:    fsd ft1, 16(sp)
+; RV32-NEXT:    j .LBB21_20
+; RV32-NEXT:  .LBB21_19:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
-; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    vslidedown.vi v28, v8, 2
+; RV32-NEXT:  .LBB21_20:
 ; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB21_22
+; RV32-NEXT:  # %bb.21:
+; RV32-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
+; RV32-NEXT:    vslidedown.vi v28, v12, 1
+; RV32-NEXT:    j .LBB21_23
+; RV32-NEXT:  .LBB21_22:
+; RV32-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v28
-; RV32-NEXT:    bnez a0, .LBB21_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB21_16:
-; RV32-NEXT:    fsd ft1, 8(sp)
+; RV32-NEXT:  .LBB21_23:
+; RV32-NEXT:    vfmv.f.s ft0, v28
+; RV32-NEXT:    fsd ft0, 8(sp)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vle64.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -128
 ; RV32-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 128
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selectcc_v8f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -128
 ; RV64-NEXT:    .cfi_def_cfa_offset 128
 ; RV64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 128
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -64
 ; RV64-NEXT:    feq.d a0, fa0, fa1
-; RV64-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v12
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB21_2
+; RV64-NEXT:    bnez a0, .LBB21_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.d ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v12
+; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB21_4
 ; RV64-NEXT:  .LBB21_2:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v8, 7
+; RV64-NEXT:    j .LBB21_5
+; RV64-NEXT:  .LBB21_3:
+; RV64-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB21_2
+; RV64-NEXT:  .LBB21_4:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 7
+; RV64-NEXT:  .LBB21_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_4:
-; RV64-NEXT:    fsd ft1, 56(sp)
+; RV64-NEXT:    fsd ft0, 56(sp)
+; RV64-NEXT:    bnez a0, .LBB21_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 6
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB21_8
+; RV64-NEXT:  .LBB21_7:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_6:
-; RV64-NEXT:    fsd ft1, 48(sp)
+; RV64-NEXT:  .LBB21_8:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 48(sp)
+; RV64-NEXT:    bnez a0, .LBB21_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 5
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB21_11
+; RV64-NEXT:  .LBB21_10:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_8:
-; RV64-NEXT:    fsd ft1, 40(sp)
+; RV64-NEXT:  .LBB21_11:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 40(sp)
+; RV64-NEXT:    bnez a0, .LBB21_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 4
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB21_14
+; RV64-NEXT:  .LBB21_13:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_10:
-; RV64-NEXT:    fsd ft1, 32(sp)
+; RV64-NEXT:  .LBB21_14:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 32(sp)
+; RV64-NEXT:    bnez a0, .LBB21_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 3
-; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    j .LBB21_17
+; RV64-NEXT:  .LBB21_16:
+; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_12:
-; RV64-NEXT:    fsd ft1, 24(sp)
+; RV64-NEXT:  .LBB21_17:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB21_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v12, 2
-; RV64-NEXT:    vfmv.f.s ft0, v28
-; RV64-NEXT:    vslidedown.vi v28, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_14:
-; RV64-NEXT:    fsd ft1, 16(sp)
+; RV64-NEXT:    j .LBB21_20
+; RV64-NEXT:  .LBB21_19:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
-; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    vslidedown.vi v28, v8, 2
+; RV64-NEXT:  .LBB21_20:
 ; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB21_22
+; RV64-NEXT:  # %bb.21:
+; RV64-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
+; RV64-NEXT:    vslidedown.vi v28, v12, 1
+; RV64-NEXT:    j .LBB21_23
+; RV64-NEXT:  .LBB21_22:
+; RV64-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v28
-; RV64-NEXT:    bnez a0, .LBB21_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB21_16:
-; RV64-NEXT:    fsd ft1, 8(sp)
+; RV64-NEXT:  .LBB21_23:
+; RV64-NEXT:    vfmv.f.s ft0, v28
+; RV64-NEXT:    fsd ft0, 8(sp)
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -128
 ; RV64-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 128
 ; RV64-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   %v = select i1 %cmp, <8 x double> %c, <8 x double> %d
   ret <8 x double> %v
 }
 
 define <16 x double> @select_v16f64(i1 zeroext %c, <16 x double> %a, <16 x double> %b) {
 ; RV32-LABEL: select_v16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -256
 ; RV32-NEXT:    .cfi_def_cfa_offset 256
 ; RV32-NEXT:    sw ra, 252(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 248(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 256
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -128
-; RV32-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v16
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB22_2
+; RV32-NEXT:    bnez a0, .LBB22_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.d ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v16
+; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB22_4
 ; RV32-NEXT:  .LBB22_2:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
+; RV32-NEXT:    vslidedown.vi v24, v8, 15
+; RV32-NEXT:    j .LBB22_5
+; RV32-NEXT:  .LBB22_3:
+; RV32-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB22_2
+; RV32-NEXT:  .LBB22_4:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 15
+; RV32-NEXT:  .LBB22_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v24
-; RV32-NEXT:    vslidedown.vi v24, v8, 15
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_4:
-; RV32-NEXT:    fsd ft1, 120(sp)
+; RV32-NEXT:    fsd ft0, 120(sp)
+; RV32-NEXT:    bnez a0, .LBB22_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 14
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_8
+; RV32-NEXT:  .LBB22_7:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 14
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_6:
-; RV32-NEXT:    fsd ft1, 112(sp)
+; RV32-NEXT:  .LBB22_8:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 112(sp)
+; RV32-NEXT:    bnez a0, .LBB22_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 13
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_11
+; RV32-NEXT:  .LBB22_10:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 13
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_8:
-; RV32-NEXT:    fsd ft1, 104(sp)
+; RV32-NEXT:  .LBB22_11:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 104(sp)
+; RV32-NEXT:    bnez a0, .LBB22_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 12
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_14
+; RV32-NEXT:  .LBB22_13:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 12
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_10:
-; RV32-NEXT:    fsd ft1, 96(sp)
+; RV32-NEXT:  .LBB22_14:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 96(sp)
+; RV32-NEXT:    bnez a0, .LBB22_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 11
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_17
+; RV32-NEXT:  .LBB22_16:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 11
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_12:
-; RV32-NEXT:    fsd ft1, 88(sp)
+; RV32-NEXT:  .LBB22_17:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 88(sp)
+; RV32-NEXT:    bnez a0, .LBB22_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 10
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_20
+; RV32-NEXT:  .LBB22_19:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 10
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_14:
-; RV32-NEXT:    fsd ft1, 80(sp)
+; RV32-NEXT:  .LBB22_20:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 80(sp)
+; RV32-NEXT:    bnez a0, .LBB22_22
+; RV32-NEXT:  # %bb.21:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 9
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_23
+; RV32-NEXT:  .LBB22_22:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 9
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_16:
-; RV32-NEXT:    fsd ft1, 72(sp)
+; RV32-NEXT:  .LBB22_23:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 72(sp)
+; RV32-NEXT:    bnez a0, .LBB22_25
+; RV32-NEXT:  # %bb.24:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 8
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_26
+; RV32-NEXT:  .LBB22_25:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 8
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_18
-; RV32-NEXT:  # %bb.17:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_18:
-; RV32-NEXT:    fsd ft1, 64(sp)
+; RV32-NEXT:  .LBB22_26:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 64(sp)
+; RV32-NEXT:    bnez a0, .LBB22_28
+; RV32-NEXT:  # %bb.27:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 7
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_29
+; RV32-NEXT:  .LBB22_28:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_20
-; RV32-NEXT:  # %bb.19:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_20:
-; RV32-NEXT:    fsd ft1, 56(sp)
+; RV32-NEXT:  .LBB22_29:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 56(sp)
+; RV32-NEXT:    bnez a0, .LBB22_31
+; RV32-NEXT:  # %bb.30:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 6
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_32
+; RV32-NEXT:  .LBB22_31:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_22
-; RV32-NEXT:  # %bb.21:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_22:
-; RV32-NEXT:    fsd ft1, 48(sp)
+; RV32-NEXT:  .LBB22_32:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 48(sp)
+; RV32-NEXT:    bnez a0, .LBB22_34
+; RV32-NEXT:  # %bb.33:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 5
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_35
+; RV32-NEXT:  .LBB22_34:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_24
-; RV32-NEXT:  # %bb.23:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_24:
-; RV32-NEXT:    fsd ft1, 40(sp)
+; RV32-NEXT:  .LBB22_35:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 40(sp)
+; RV32-NEXT:    bnez a0, .LBB22_37
+; RV32-NEXT:  # %bb.36:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 4
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_38
+; RV32-NEXT:  .LBB22_37:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_26
-; RV32-NEXT:  # %bb.25:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_26:
-; RV32-NEXT:    fsd ft1, 32(sp)
+; RV32-NEXT:  .LBB22_38:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 32(sp)
+; RV32-NEXT:    bnez a0, .LBB22_40
+; RV32-NEXT:  # %bb.39:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 3
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB22_41
+; RV32-NEXT:  .LBB22_40:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_28
-; RV32-NEXT:  # %bb.27:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_28:
-; RV32-NEXT:    fsd ft1, 24(sp)
+; RV32-NEXT:  .LBB22_41:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB22_43
+; RV32-NEXT:  # %bb.42:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 2
-; RV32-NEXT:    vfmv.f.s ft0, v24
-; RV32-NEXT:    vslidedown.vi v24, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB22_30
-; RV32-NEXT:  # %bb.29:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_30:
-; RV32-NEXT:    fsd ft1, 16(sp)
+; RV32-NEXT:    j .LBB22_44
+; RV32-NEXT:  .LBB22_43:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
-; RV32-NEXT:    vslidedown.vi v16, v16, 1
-; RV32-NEXT:    vfmv.f.s ft0, v16
+; RV32-NEXT:    vslidedown.vi v24, v8, 2
+; RV32-NEXT:  .LBB22_44:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB22_46
+; RV32-NEXT:  # %bb.45:
+; RV32-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
+; RV32-NEXT:    vslidedown.vi v8, v16, 1
+; RV32-NEXT:    j .LBB22_47
+; RV32-NEXT:  .LBB22_46:
+; RV32-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v8, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v8
-; RV32-NEXT:    bnez a0, .LBB22_32
-; RV32-NEXT:  # %bb.31:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB22_32:
-; RV32-NEXT:    fsd ft1, 8(sp)
+; RV32-NEXT:  .LBB22_47:
+; RV32-NEXT:    vfmv.f.s ft0, v8
+; RV32-NEXT:    fsd ft0, 8(sp)
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -256
 ; RV32-NEXT:    lw s0, 248(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 252(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 256
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_v16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -256
 ; RV64-NEXT:    .cfi_def_cfa_offset 256
 ; RV64-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 256
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -128
-; RV64-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v16
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB22_2
+; RV64-NEXT:    bnez a0, .LBB22_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.d ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v16
+; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB22_4
 ; RV64-NEXT:  .LBB22_2:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
+; RV64-NEXT:    vslidedown.vi v24, v8, 15
+; RV64-NEXT:    j .LBB22_5
+; RV64-NEXT:  .LBB22_3:
+; RV64-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB22_2
+; RV64-NEXT:  .LBB22_4:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 15
+; RV64-NEXT:  .LBB22_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v24
-; RV64-NEXT:    vslidedown.vi v24, v8, 15
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_4:
-; RV64-NEXT:    fsd ft1, 120(sp)
+; RV64-NEXT:    fsd ft0, 120(sp)
+; RV64-NEXT:    bnez a0, .LBB22_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 14
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_8
+; RV64-NEXT:  .LBB22_7:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 14
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_6:
-; RV64-NEXT:    fsd ft1, 112(sp)
+; RV64-NEXT:  .LBB22_8:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 112(sp)
+; RV64-NEXT:    bnez a0, .LBB22_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 13
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_11
+; RV64-NEXT:  .LBB22_10:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 13
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_8:
-; RV64-NEXT:    fsd ft1, 104(sp)
+; RV64-NEXT:  .LBB22_11:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 104(sp)
+; RV64-NEXT:    bnez a0, .LBB22_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 12
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_14
+; RV64-NEXT:  .LBB22_13:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 12
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_10:
-; RV64-NEXT:    fsd ft1, 96(sp)
+; RV64-NEXT:  .LBB22_14:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 96(sp)
+; RV64-NEXT:    bnez a0, .LBB22_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 11
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_17
+; RV64-NEXT:  .LBB22_16:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 11
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_12:
-; RV64-NEXT:    fsd ft1, 88(sp)
+; RV64-NEXT:  .LBB22_17:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 88(sp)
+; RV64-NEXT:    bnez a0, .LBB22_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 10
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_20
+; RV64-NEXT:  .LBB22_19:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 10
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_14:
-; RV64-NEXT:    fsd ft1, 80(sp)
+; RV64-NEXT:  .LBB22_20:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 80(sp)
+; RV64-NEXT:    bnez a0, .LBB22_22
+; RV64-NEXT:  # %bb.21:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 9
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_23
+; RV64-NEXT:  .LBB22_22:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 9
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_16:
-; RV64-NEXT:    fsd ft1, 72(sp)
+; RV64-NEXT:  .LBB22_23:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 72(sp)
+; RV64-NEXT:    bnez a0, .LBB22_25
+; RV64-NEXT:  # %bb.24:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 8
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_26
+; RV64-NEXT:  .LBB22_25:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 8
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_18
-; RV64-NEXT:  # %bb.17:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_18:
-; RV64-NEXT:    fsd ft1, 64(sp)
+; RV64-NEXT:  .LBB22_26:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 64(sp)
+; RV64-NEXT:    bnez a0, .LBB22_28
+; RV64-NEXT:  # %bb.27:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 7
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_29
+; RV64-NEXT:  .LBB22_28:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_20
-; RV64-NEXT:  # %bb.19:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_20:
-; RV64-NEXT:    fsd ft1, 56(sp)
+; RV64-NEXT:  .LBB22_29:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 56(sp)
+; RV64-NEXT:    bnez a0, .LBB22_31
+; RV64-NEXT:  # %bb.30:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 6
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_32
+; RV64-NEXT:  .LBB22_31:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_22
-; RV64-NEXT:  # %bb.21:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_22:
-; RV64-NEXT:    fsd ft1, 48(sp)
+; RV64-NEXT:  .LBB22_32:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 48(sp)
+; RV64-NEXT:    bnez a0, .LBB22_34
+; RV64-NEXT:  # %bb.33:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 5
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_35
+; RV64-NEXT:  .LBB22_34:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_24
-; RV64-NEXT:  # %bb.23:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_24:
-; RV64-NEXT:    fsd ft1, 40(sp)
+; RV64-NEXT:  .LBB22_35:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 40(sp)
+; RV64-NEXT:    bnez a0, .LBB22_37
+; RV64-NEXT:  # %bb.36:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 4
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_38
+; RV64-NEXT:  .LBB22_37:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_26
-; RV64-NEXT:  # %bb.25:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_26:
-; RV64-NEXT:    fsd ft1, 32(sp)
+; RV64-NEXT:  .LBB22_38:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 32(sp)
+; RV64-NEXT:    bnez a0, .LBB22_40
+; RV64-NEXT:  # %bb.39:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 3
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB22_41
+; RV64-NEXT:  .LBB22_40:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_28
-; RV64-NEXT:  # %bb.27:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_28:
-; RV64-NEXT:    fsd ft1, 24(sp)
+; RV64-NEXT:  .LBB22_41:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB22_43
+; RV64-NEXT:  # %bb.42:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 2
-; RV64-NEXT:    vfmv.f.s ft0, v24
-; RV64-NEXT:    vslidedown.vi v24, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB22_30
-; RV64-NEXT:  # %bb.29:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_30:
-; RV64-NEXT:    fsd ft1, 16(sp)
+; RV64-NEXT:    j .LBB22_44
+; RV64-NEXT:  .LBB22_43:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
-; RV64-NEXT:    vslidedown.vi v16, v16, 1
-; RV64-NEXT:    vfmv.f.s ft0, v16
+; RV64-NEXT:    vslidedown.vi v24, v8, 2
+; RV64-NEXT:  .LBB22_44:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB22_46
+; RV64-NEXT:  # %bb.45:
+; RV64-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
+; RV64-NEXT:    vslidedown.vi v8, v16, 1
+; RV64-NEXT:    j .LBB22_47
+; RV64-NEXT:  .LBB22_46:
+; RV64-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v8, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v8
-; RV64-NEXT:    bnez a0, .LBB22_32
-; RV64-NEXT:  # %bb.31:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB22_32:
-; RV64-NEXT:    fsd ft1, 8(sp)
+; RV64-NEXT:  .LBB22_47:
+; RV64-NEXT:    vfmv.f.s ft0, v8
+; RV64-NEXT:    fsd ft0, 8(sp)
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -256
 ; RV64-NEXT:    ld s0, 240(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 256
 ; RV64-NEXT:    ret
   %v = select i1 %c, <16 x double> %a, <16 x double> %b
   ret <16 x double> %v
 }
 
 define <16 x double> @selectcc_v16f64(double %a, double %b, <16 x double> %c, <16 x double> %d) {
 ; RV32-LABEL: selectcc_v16f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -256
 ; RV32-NEXT:    .cfi_def_cfa_offset 256
 ; RV32-NEXT:    sw ra, 252(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s0, 248(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 256
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -128
 ; RV32-NEXT:    feq.d a0, fa0, fa1
-; RV32-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
-; RV32-NEXT:    vfmv.f.s ft1, v16
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    bnez a0, .LBB23_2
+; RV32-NEXT:    bnez a0, .LBB23_3
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    fmv.d ft0, ft1
+; RV32-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v16
+; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    beqz a0, .LBB23_4
 ; RV32-NEXT:  .LBB23_2:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
+; RV32-NEXT:    vslidedown.vi v24, v8, 15
+; RV32-NEXT:    j .LBB23_5
+; RV32-NEXT:  .LBB23_3:
+; RV32-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV32-NEXT:    vfmv.f.s ft0, v8
 ; RV32-NEXT:    fsd ft0, 0(sp)
+; RV32-NEXT:    bnez a0, .LBB23_2
+; RV32-NEXT:  .LBB23_4:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 15
+; RV32-NEXT:  .LBB23_5:
 ; RV32-NEXT:    vfmv.f.s ft0, v24
-; RV32-NEXT:    vslidedown.vi v24, v8, 15
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_4
-; RV32-NEXT:  # %bb.3:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_4:
-; RV32-NEXT:    fsd ft1, 120(sp)
+; RV32-NEXT:    fsd ft0, 120(sp)
+; RV32-NEXT:    bnez a0, .LBB23_7
+; RV32-NEXT:  # %bb.6:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 14
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_8
+; RV32-NEXT:  .LBB23_7:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 14
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_6
-; RV32-NEXT:  # %bb.5:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_6:
-; RV32-NEXT:    fsd ft1, 112(sp)
+; RV32-NEXT:  .LBB23_8:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 112(sp)
+; RV32-NEXT:    bnez a0, .LBB23_10
+; RV32-NEXT:  # %bb.9:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 13
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_11
+; RV32-NEXT:  .LBB23_10:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 13
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_8
-; RV32-NEXT:  # %bb.7:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_8:
-; RV32-NEXT:    fsd ft1, 104(sp)
+; RV32-NEXT:  .LBB23_11:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 104(sp)
+; RV32-NEXT:    bnez a0, .LBB23_13
+; RV32-NEXT:  # %bb.12:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 12
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_14
+; RV32-NEXT:  .LBB23_13:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 12
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_10
-; RV32-NEXT:  # %bb.9:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_10:
-; RV32-NEXT:    fsd ft1, 96(sp)
+; RV32-NEXT:  .LBB23_14:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 96(sp)
+; RV32-NEXT:    bnez a0, .LBB23_16
+; RV32-NEXT:  # %bb.15:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 11
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_17
+; RV32-NEXT:  .LBB23_16:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 11
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_12
-; RV32-NEXT:  # %bb.11:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_12:
-; RV32-NEXT:    fsd ft1, 88(sp)
+; RV32-NEXT:  .LBB23_17:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 88(sp)
+; RV32-NEXT:    bnez a0, .LBB23_19
+; RV32-NEXT:  # %bb.18:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 10
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_20
+; RV32-NEXT:  .LBB23_19:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 10
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_14
-; RV32-NEXT:  # %bb.13:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_14:
-; RV32-NEXT:    fsd ft1, 80(sp)
+; RV32-NEXT:  .LBB23_20:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 80(sp)
+; RV32-NEXT:    bnez a0, .LBB23_22
+; RV32-NEXT:  # %bb.21:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 9
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_23
+; RV32-NEXT:  .LBB23_22:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 9
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_16
-; RV32-NEXT:  # %bb.15:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_16:
-; RV32-NEXT:    fsd ft1, 72(sp)
+; RV32-NEXT:  .LBB23_23:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 72(sp)
+; RV32-NEXT:    bnez a0, .LBB23_25
+; RV32-NEXT:  # %bb.24:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 8
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_26
+; RV32-NEXT:  .LBB23_25:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 8
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_18
-; RV32-NEXT:  # %bb.17:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_18:
-; RV32-NEXT:    fsd ft1, 64(sp)
+; RV32-NEXT:  .LBB23_26:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 64(sp)
+; RV32-NEXT:    bnez a0, .LBB23_28
+; RV32-NEXT:  # %bb.27:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 7
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_29
+; RV32-NEXT:  .LBB23_28:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 7
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_20
-; RV32-NEXT:  # %bb.19:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_20:
-; RV32-NEXT:    fsd ft1, 56(sp)
+; RV32-NEXT:  .LBB23_29:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 56(sp)
+; RV32-NEXT:    bnez a0, .LBB23_31
+; RV32-NEXT:  # %bb.30:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 6
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_32
+; RV32-NEXT:  .LBB23_31:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 6
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_22
-; RV32-NEXT:  # %bb.21:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_22:
-; RV32-NEXT:    fsd ft1, 48(sp)
+; RV32-NEXT:  .LBB23_32:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 48(sp)
+; RV32-NEXT:    bnez a0, .LBB23_34
+; RV32-NEXT:  # %bb.33:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 5
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_35
+; RV32-NEXT:  .LBB23_34:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 5
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_24
-; RV32-NEXT:  # %bb.23:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_24:
-; RV32-NEXT:    fsd ft1, 40(sp)
+; RV32-NEXT:  .LBB23_35:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 40(sp)
+; RV32-NEXT:    bnez a0, .LBB23_37
+; RV32-NEXT:  # %bb.36:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 4
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_38
+; RV32-NEXT:  .LBB23_37:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 4
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_26
-; RV32-NEXT:  # %bb.25:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_26:
-; RV32-NEXT:    fsd ft1, 32(sp)
+; RV32-NEXT:  .LBB23_38:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 32(sp)
+; RV32-NEXT:    bnez a0, .LBB23_40
+; RV32-NEXT:  # %bb.39:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 3
-; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    j .LBB23_41
+; RV32-NEXT:  .LBB23_40:
+; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v8, 3
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_28
-; RV32-NEXT:  # %bb.27:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_28:
-; RV32-NEXT:    fsd ft1, 24(sp)
+; RV32-NEXT:  .LBB23_41:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 24(sp)
+; RV32-NEXT:    bnez a0, .LBB23_43
+; RV32-NEXT:  # %bb.42:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v24, v16, 2
-; RV32-NEXT:    vfmv.f.s ft0, v24
-; RV32-NEXT:    vslidedown.vi v24, v8, 2
-; RV32-NEXT:    vfmv.f.s ft1, v24
-; RV32-NEXT:    bnez a0, .LBB23_30
-; RV32-NEXT:  # %bb.29:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_30:
-; RV32-NEXT:    fsd ft1, 16(sp)
+; RV32-NEXT:    j .LBB23_44
+; RV32-NEXT:  .LBB23_43:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
-; RV32-NEXT:    vslidedown.vi v16, v16, 1
-; RV32-NEXT:    vfmv.f.s ft0, v16
+; RV32-NEXT:    vslidedown.vi v24, v8, 2
+; RV32-NEXT:  .LBB23_44:
+; RV32-NEXT:    vfmv.f.s ft0, v24
+; RV32-NEXT:    fsd ft0, 16(sp)
+; RV32-NEXT:    bnez a0, .LBB23_46
+; RV32-NEXT:  # %bb.45:
+; RV32-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
+; RV32-NEXT:    vslidedown.vi v8, v16, 1
+; RV32-NEXT:    j .LBB23_47
+; RV32-NEXT:  .LBB23_46:
+; RV32-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; RV32-NEXT:    vslidedown.vi v8, v8, 1
-; RV32-NEXT:    vfmv.f.s ft1, v8
-; RV32-NEXT:    bnez a0, .LBB23_32
-; RV32-NEXT:  # %bb.31:
-; RV32-NEXT:    fmv.d ft1, ft0
-; RV32-NEXT:  .LBB23_32:
-; RV32-NEXT:    fsd ft1, 8(sp)
+; RV32-NEXT:  .LBB23_47:
+; RV32-NEXT:    vfmv.f.s ft0, v8
+; RV32-NEXT:    fsd ft0, 8(sp)
 ; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV32-NEXT:    vle64.v v8, (sp)
 ; RV32-NEXT:    addi sp, s0, -256
 ; RV32-NEXT:    lw s0, 248(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 252(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 256
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selectcc_v16f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -256
 ; RV64-NEXT:    .cfi_def_cfa_offset 256
 ; RV64-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 256
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -128
 ; RV64-NEXT:    feq.d a0, fa0, fa1
-; RV64-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
-; RV64-NEXT:    vfmv.f.s ft1, v16
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    bnez a0, .LBB23_2
+; RV64-NEXT:    bnez a0, .LBB23_3
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    fmv.d ft0, ft1
+; RV64-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v16
+; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    beqz a0, .LBB23_4
 ; RV64-NEXT:  .LBB23_2:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
+; RV64-NEXT:    vslidedown.vi v24, v8, 15
+; RV64-NEXT:    j .LBB23_5
+; RV64-NEXT:  .LBB23_3:
+; RV64-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; RV64-NEXT:    vfmv.f.s ft0, v8
 ; RV64-NEXT:    fsd ft0, 0(sp)
+; RV64-NEXT:    bnez a0, .LBB23_2
+; RV64-NEXT:  .LBB23_4:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 15
+; RV64-NEXT:  .LBB23_5:
 ; RV64-NEXT:    vfmv.f.s ft0, v24
-; RV64-NEXT:    vslidedown.vi v24, v8, 15
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_4
-; RV64-NEXT:  # %bb.3:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_4:
-; RV64-NEXT:    fsd ft1, 120(sp)
+; RV64-NEXT:    fsd ft0, 120(sp)
+; RV64-NEXT:    bnez a0, .LBB23_7
+; RV64-NEXT:  # %bb.6:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 14
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_8
+; RV64-NEXT:  .LBB23_7:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 14
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_6
-; RV64-NEXT:  # %bb.5:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_6:
-; RV64-NEXT:    fsd ft1, 112(sp)
+; RV64-NEXT:  .LBB23_8:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 112(sp)
+; RV64-NEXT:    bnez a0, .LBB23_10
+; RV64-NEXT:  # %bb.9:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 13
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_11
+; RV64-NEXT:  .LBB23_10:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 13
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_8
-; RV64-NEXT:  # %bb.7:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_8:
-; RV64-NEXT:    fsd ft1, 104(sp)
+; RV64-NEXT:  .LBB23_11:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 104(sp)
+; RV64-NEXT:    bnez a0, .LBB23_13
+; RV64-NEXT:  # %bb.12:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 12
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_14
+; RV64-NEXT:  .LBB23_13:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 12
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_10
-; RV64-NEXT:  # %bb.9:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_10:
-; RV64-NEXT:    fsd ft1, 96(sp)
+; RV64-NEXT:  .LBB23_14:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 96(sp)
+; RV64-NEXT:    bnez a0, .LBB23_16
+; RV64-NEXT:  # %bb.15:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 11
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_17
+; RV64-NEXT:  .LBB23_16:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 11
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_12
-; RV64-NEXT:  # %bb.11:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_12:
-; RV64-NEXT:    fsd ft1, 88(sp)
+; RV64-NEXT:  .LBB23_17:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 88(sp)
+; RV64-NEXT:    bnez a0, .LBB23_19
+; RV64-NEXT:  # %bb.18:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 10
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_20
+; RV64-NEXT:  .LBB23_19:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 10
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_14
-; RV64-NEXT:  # %bb.13:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_14:
-; RV64-NEXT:    fsd ft1, 80(sp)
+; RV64-NEXT:  .LBB23_20:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 80(sp)
+; RV64-NEXT:    bnez a0, .LBB23_22
+; RV64-NEXT:  # %bb.21:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 9
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_23
+; RV64-NEXT:  .LBB23_22:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 9
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_16
-; RV64-NEXT:  # %bb.15:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_16:
-; RV64-NEXT:    fsd ft1, 72(sp)
+; RV64-NEXT:  .LBB23_23:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 72(sp)
+; RV64-NEXT:    bnez a0, .LBB23_25
+; RV64-NEXT:  # %bb.24:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 8
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_26
+; RV64-NEXT:  .LBB23_25:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 8
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_18
-; RV64-NEXT:  # %bb.17:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_18:
-; RV64-NEXT:    fsd ft1, 64(sp)
+; RV64-NEXT:  .LBB23_26:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 64(sp)
+; RV64-NEXT:    bnez a0, .LBB23_28
+; RV64-NEXT:  # %bb.27:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 7
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_29
+; RV64-NEXT:  .LBB23_28:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 7
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_20
-; RV64-NEXT:  # %bb.19:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_20:
-; RV64-NEXT:    fsd ft1, 56(sp)
+; RV64-NEXT:  .LBB23_29:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 56(sp)
+; RV64-NEXT:    bnez a0, .LBB23_31
+; RV64-NEXT:  # %bb.30:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 6
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_32
+; RV64-NEXT:  .LBB23_31:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 6
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_22
-; RV64-NEXT:  # %bb.21:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_22:
-; RV64-NEXT:    fsd ft1, 48(sp)
+; RV64-NEXT:  .LBB23_32:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 48(sp)
+; RV64-NEXT:    bnez a0, .LBB23_34
+; RV64-NEXT:  # %bb.33:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 5
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_35
+; RV64-NEXT:  .LBB23_34:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 5
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_24
-; RV64-NEXT:  # %bb.23:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_24:
-; RV64-NEXT:    fsd ft1, 40(sp)
+; RV64-NEXT:  .LBB23_35:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 40(sp)
+; RV64-NEXT:    bnez a0, .LBB23_37
+; RV64-NEXT:  # %bb.36:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 4
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_38
+; RV64-NEXT:  .LBB23_37:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 4
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_26
-; RV64-NEXT:  # %bb.25:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_26:
-; RV64-NEXT:    fsd ft1, 32(sp)
+; RV64-NEXT:  .LBB23_38:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 32(sp)
+; RV64-NEXT:    bnez a0, .LBB23_40
+; RV64-NEXT:  # %bb.39:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 3
-; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    j .LBB23_41
+; RV64-NEXT:  .LBB23_40:
+; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v8, 3
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_28
-; RV64-NEXT:  # %bb.27:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_28:
-; RV64-NEXT:    fsd ft1, 24(sp)
+; RV64-NEXT:  .LBB23_41:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 24(sp)
+; RV64-NEXT:    bnez a0, .LBB23_43
+; RV64-NEXT:  # %bb.42:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v24, v16, 2
-; RV64-NEXT:    vfmv.f.s ft0, v24
-; RV64-NEXT:    vslidedown.vi v24, v8, 2
-; RV64-NEXT:    vfmv.f.s ft1, v24
-; RV64-NEXT:    bnez a0, .LBB23_30
-; RV64-NEXT:  # %bb.29:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_30:
-; RV64-NEXT:    fsd ft1, 16(sp)
+; RV64-NEXT:    j .LBB23_44
+; RV64-NEXT:  .LBB23_43:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
-; RV64-NEXT:    vslidedown.vi v16, v16, 1
-; RV64-NEXT:    vfmv.f.s ft0, v16
+; RV64-NEXT:    vslidedown.vi v24, v8, 2
+; RV64-NEXT:  .LBB23_44:
+; RV64-NEXT:    vfmv.f.s ft0, v24
+; RV64-NEXT:    fsd ft0, 16(sp)
+; RV64-NEXT:    bnez a0, .LBB23_46
+; RV64-NEXT:  # %bb.45:
+; RV64-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
+; RV64-NEXT:    vslidedown.vi v8, v16, 1
+; RV64-NEXT:    j .LBB23_47
+; RV64-NEXT:  .LBB23_46:
+; RV64-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; RV64-NEXT:    vslidedown.vi v8, v8, 1
-; RV64-NEXT:    vfmv.f.s ft1, v8
-; RV64-NEXT:    bnez a0, .LBB23_32
-; RV64-NEXT:  # %bb.31:
-; RV64-NEXT:    fmv.d ft1, ft0
-; RV64-NEXT:  .LBB23_32:
-; RV64-NEXT:    fsd ft1, 8(sp)
+; RV64-NEXT:  .LBB23_47:
+; RV64-NEXT:    vfmv.f.s ft0, v8
+; RV64-NEXT:    fsd ft0, 8(sp)
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (sp)
 ; RV64-NEXT:    addi sp, s0, -256
 ; RV64-NEXT:    ld s0, 240(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 256
 ; RV64-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   %v = select i1 %cmp, <16 x double> %c, <16 x double> %d
   ret <16 x double> %v
 }

llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll

declare void @llvm.riscv.vse.nxv1i64(
   <vscale x 1 x i64>*,
   i64);
 
 define i64 @test(<vscale x 1 x i64> %0) nounwind {
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.entry:
   ; CHECK:   liveins: $v8
   ; CHECK:   [[COPY:%[0-9]+]]:vr = COPY $v8
-  ; CHECK:   dead %2:gpr = PseudoVSETIVLI 1, 88, implicit-def $vl, implicit-def $vtype
-  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 6, implicit $vl, implicit $vtype
+  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 6
   ; CHECK:   [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load 8 from %ir.a)
   ; CHECK:   $x10 = COPY [[LD]]
   ; CHECK:   PseudoRET implicit $x10
 entry:
   %a = alloca i64
   %b = bitcast i64* %a to <vscale x 1 x i64>*
   call void @llvm.riscv.vse.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %b,
     i64 1)
   %c = load i64, i64* %a
   ret i64 %c
 }

llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

 ---
 name: mask_reg_alloc
 tracksRegLiveness: true
 body:             |
   bb.0 (%ir-block.0):
     liveins: $v0, $v1, $v2, $v3
     ; CHECK-LABEL: name: mask_reg_alloc
     ; CHECK: liveins: $v0, $v1, $v2, $v3
-    ; CHECK: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: dead renamable $x10 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
+    ; CHECK: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype
     ; CHECK: renamable $v0 = COPY killed renamable $v1
-    ; CHECK: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
-    ; CHECK: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype
+    ; CHECK: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, 1, 3, implicit $vl, implicit $vtype
     ; CHECK: PseudoRET implicit $v0
     %0:vr = COPY $v0
     %1:vr = COPY $v1
     %2:vr = COPY $v2
     %3:vr = COPY $v3
     %4:vmv0 = COPY %0
-    %5:vrnov0 = PseudoVMERGE_VIM_M1 killed %2, 1, %4, $noreg, -1, implicit $vl, implicit $vtype
+    %5:vrnov0 = PseudoVMERGE_VIM_M1 killed %2, 1, %4, 1, 3
     %6:vmv0 = COPY %1
-    %7:vrnov0 = PseudoVMERGE_VIM_M1 killed %3, 1, %6, $noreg, -1, implicit $vl, implicit $vtype
-    %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, $noreg, -1, implicit $vl, implicit $vtype
+    %7:vrnov0 = PseudoVMERGE_VIM_M1 killed %3, 1, %6, 1, 3
+    %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, 1, 3
     $v0 = COPY %8
     PseudoRET implicit $v0
 ...

llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir

bb.0 (%ir-block.0):
 
     ; CHECK-LABEL: name: masked_load_nxv8i64
     ; CHECK: liveins: $x10, $v0
     ; CHECK: [[COPY:%[0-9]+]]:vr = COPY $v0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $x10
     ; CHECK: $v0 = COPY [[COPY]]
     ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
     ; CHECK: [[COPY2:%[0-9]+]]:vrm8nov0 = COPY [[DEF]]
-    ; CHECK: dead %5:gpr = PseudoVSETVLI $x0, 91, implicit-def $vl, implicit-def $vtype
-    ; CHECK: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[COPY2]], [[COPY1]], $v0, $noreg, 6, implicit $vl, implicit $vtype :: (load 64 from %ir.a, align 8)
+    ; CHECK: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[COPY2]], [[COPY1]], $v0, $x0, 6 :: (load 64 from %ir.a, align 8)
     ; CHECK: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]]
     ; CHECK: PseudoRET implicit $v8m8
     %1:vr = COPY $v0
     %0:gpr = COPY $x10
     $v0 = COPY %1
     %3:vrm8 = IMPLICIT_DEF
     %4:vrm8nov0 = COPY %3
-    %2:vrm8nov0 = PseudoVLE64_V_M8_MASK %4, %0, $v0, $x0, 6, implicit $vl, implicit $vtype :: (load 64 from %ir.a, align 8)
+    %2:vrm8nov0 = PseudoVLE64_V_M8_MASK %4, %0, $v0, $x0, 6 :: (load 64 from %ir.a, align 8)
     $v8m8 = COPY %2
     PseudoRET implicit $v8m8
 
 ...

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
 
 define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
 
 define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.h fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
   ret half %red
 }
 
 define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
 

 
 define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
 

 
 define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.s fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
   ret float %red
 }
 
 define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
 

 
 define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.d fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
 
 define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_fadd_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s ft0, v25
 ; CHECK-NEXT:    fadd.d fa0, fa0, ft0
 ; CHECK-NEXT:    ret
   %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
   ret double %red
 }
 
 define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
 ; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, fa0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfredosum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
   ret double %red
 }
 
 declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>)
 
 define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI18_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI18_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
 ; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI19_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI19_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
 ; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI20_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI20_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
 
 define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI21_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI21_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
 

 ; CHECK-NEXT:    lui a0, %hi(.LCPI23_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI23_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>)
 
 define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI24_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI24_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI25_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI25_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI26_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI26_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
 

 ; CHECK-LABEL: vreduce_fmin_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI28_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI28_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>)
 
 define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI29_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI29_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>)
 

 ; CHECK-LABEL: vreduce_fmin_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI33_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI33_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>)
 
 define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI34_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI34_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double>)
 
 define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {
 ; CHECK-LABEL: vreduce_fmin_nxv16f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI35_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI35_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)
   ret double %red
 }
 
 declare half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half>)
 
 define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv1f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI36_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI36_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
 ; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI37_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI37_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
   ret half %red
 }
 
 define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
 ; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI38_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI38_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half>)
 
 define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv2f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI39_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI39_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)
   ret half %red
 }
 
 declare half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half>)
 

 ; CHECK-NEXT:    lui a0, %hi(.LCPI41_0)
 ; CHECK-NEXT:    flh ft0, %lo(.LCPI41_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)
   ret half %red
 }
 
 declare float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float>)
 
 define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv1f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI42_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI42_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI43_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI43_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
   ret float %red
 }
 
 define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI44_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI44_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>)
 

 ; CHECK-LABEL: vreduce_fmax_nxv4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI46_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI46_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
   ret float %red
 }
 
 declare float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float>)
 
 define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI47_0)
 ; CHECK-NEXT:    flw ft0, %lo(.LCPI47_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)
   ret float %red
 }
 
 declare double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double>)
 

 ; CHECK-LABEL: vreduce_fmax_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI51_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI51_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>)
 
 define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI52_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI52_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
   ret double %red
 }
 
 declare double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double>)
 
 define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {
 ; CHECK-LABEL: vreduce_fmax_nxv16f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI53_0)
 ; CHECK-NEXT:    fld ft0, %lo(.LCPI53_0)(a0)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
   ret double %red
 }

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
 
 declare i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_add_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_add_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 8
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 8
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16>)
 

 
 define i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_add_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32>)
 
 define i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>)
 

 
 define i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32>)
 
 define i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>)
 

 
 define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red

 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    sw zero, 8(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red

 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red

 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    sw zero, 8(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red

 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    sw a0, 12(sp)
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    addi a0, sp, 8
 ; CHECK-NEXT:    vlse64.v v25, (a0), zero
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
 
 declare i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_add_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8>)
 
 define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8>)
 
 define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -128
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 127
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8>)
 
 define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
   ret i8 %red
 }
 
 declare i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_add_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 8
 ; CHECK-NEXT:    addiw a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16>)
 
 define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048568
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 8
 ; CHECK-NEXT:    addiw a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16>)
 
 define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
   ret i16 %red
 }
 
 declare i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16>)
 

 
 define signext i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_add_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    addiw a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32>)
 
 define signext i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>)
 

 
 define signext i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    addiw a0, a0, -1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32>)
 
 define signext i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
   ret i32 %red
 }
 
 declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>)
 

 
 define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
 ; CHECK-NEXT:    slli a0, a0, 63
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
 ; CHECK-NEXT:    srli a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
 ; CHECK-NEXT:    slli a0, a0, 63
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
 ; CHECK-NEXT:    srli a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=experimental-v \
+# RUN:     -run-pass=riscv-insert-vsetvli | FileCheck %s
+
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.ll"
+  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+  target triple = "riscv64"
+
+  ; Function Attrs: nounwind
+  define <vscale x 1 x i64> @add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
+  entry:
+    %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
+    ret <vscale x 1 x i64> %a
+  }
+
+  ; Function Attrs: nounwind
+  define <vscale x 1 x i64> @load_add(<vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 {
+  entry:
+    %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* %0, i64 %2)
+    %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
+    ret <vscale x 1 x i64> %b
+  }
+
+  ; Function Attrs: nounwind
+  define <vscale x 1 x i64> @load_zext(<vscale x 1 x i32>* %0, i64 %1) #0 {
+  entry:
+    %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* %0, i64 %1)
+    %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %1)
+    ret <vscale x 1 x i64> %b
+  }
+
+  ; Function Attrs: nounwind readnone
+  declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
+
+  ; Function Attrs: nounwind
+  define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 {
+  entry:
+    %a = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %0)
+    ret i64 %a
+  }
+
+  define void @add_v2i64(<2 x i64>* %x, <2 x i64>* %y) #2 {
+    %a = load <2 x i64>, <2 x i64>* %x, align 16
+    %b = load <2 x i64>, <2 x i64>* %y, align 16
+    %c = add <2 x i64> %a, %b
+    store <2 x i64> %c, <2 x i64>* %x, align 16
+    ret void
+  }
+
+  ; Function Attrs: nofree nosync nounwind readnone willreturn
+  declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>) #3
+
+  define i64 @vreduce_add_v2i64(<2 x i64>* %x) #2 {
+    %v = load <2 x i64>, <2 x i64>* %x, align 16
+    %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)
+    ret i64 %red
+  }
+
+  ; Function Attrs: nounwind
+  declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #0
+
+  ; Function Attrs: nounwind
+  define <vscale x 1 x i64> @vsetvli_add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
+  entry:
+    %a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 1)
+    %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %a)
+    ret <vscale x 1 x i64> %b
+  }
+
+  ; Function Attrs: nounwind readnone
+  declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
+
+  ; Function Attrs: nounwind readonly
+  declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* nocapture, i64) #2
+
+  ; Function Attrs: nounwind readonly
+  declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* nocapture, i64) #2
+
+  ; Function Attrs: nounwind readnone
+  declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
+
+  attributes #0 = { nounwind "target-features"="+experimental-v" }
+  attributes #1 = { nounwind readnone "target-features"="+experimental-v" }
+  attributes #2 = { "target-features"="+experimental-v" }
+  attributes #3 = { nofree nosync nounwind readnone willreturn "target-features"="+experimental-v" }
+  attributes #4 = { nounwind readonly "target-features"="+experimental-v" }
+
+...
+---
+name:            add
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vr }
+  - { id: 1, class: vr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: vr }
+liveins:
+  - { reg: '$v8', virtual-reg: '%0' }
+  - { reg: '$v9', virtual-reg: '%1' }
+  - { reg: '$x10', virtual-reg: '%2' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9, $x10
+
+    ; CHECK-LABEL: name: add
+    ; CHECK: liveins: $v8, $v9, $x10
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK: [[COPY1:%[0-9]+]]:vr = COPY $v9
+    ; CHECK: [[COPY2:%[0-9]+]]:vr = COPY $v8
+    ; CHECK: dead %4:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: $v8 = COPY [[PseudoVADD_VV_M1_]]
+    ; CHECK: PseudoRET implicit $v8
+    %2:gpr = COPY $x10
+    %1:vr = COPY $v9
+    %0:vr = COPY $v8
+    %3:vr = PseudoVADD_VV_M1 %0, %1, %2, 6
+    $v8 = COPY %3
+    PseudoRET implicit $v8
+
+...
+---
+name:            load_add
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: vr }
+  - { id: 4, class: vr }
+liveins:
+  - { reg: '$x10', virtual-reg: '%0' }
+  - { reg: '$v8', virtual-reg: '%1' }
+  - { reg: '$x11', virtual-reg: '%2' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x10, $v8, $x11
+
+    ; CHECK-LABEL: name: load_add
+    ; CHECK: liveins: $x10, $v8, $x11
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK: [[COPY1:%[0-9]+]]:vr = COPY $v8
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK: dead %5:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY2]], $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: $v8 = COPY [[PseudoVADD_VV_M1_]]
+    ; CHECK: PseudoRET implicit $v8
+    %2:gpr = COPY $x11
+    %1:vr = COPY $v8
+    %0:gpr = COPY $x10
+    %3:vr = PseudoVLE64_V_M1 %0, %2, 6
+    %4:vr = PseudoVADD_VV_M1 killed %3, %1, %2, 6
+    $v8 = COPY %4
+    PseudoRET implicit $v8
+
+...
+---
+name:            load_zext
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: vr }
+  - { id: 3, class: vr }
+liveins:
+  - { reg: '$x10', virtual-reg: '%0' }
+  - { reg: '$x11', virtual-reg: '%1' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: load_zext
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK: dead %5:gpr = PseudoVSETVLI [[COPY]], 87, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[COPY1]], $noreg, 5, implicit $vl, implicit $vtype
+    ; CHECK: dead %4:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: early-clobber %3:vr = PseudoVZEXT_VF2_M1 killed [[PseudoVLE32_V_MF2_]], $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: $v8 = COPY %3
+    ; CHECK: PseudoRET implicit $v8
+    %1:gpr = COPY $x11
+    %0:gpr = COPY $x10
+    %2:vr = PseudoVLE32_V_MF2 %0, %1, 5
+    early-clobber %3:vr = PseudoVZEXT_VF2_M1 killed %2, %1, 6
+    $v8 = COPY %3
+    PseudoRET implicit $v8
+
+...
+---
+name:            vmv_x_s
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vr }
+  - { id: 1, class: gpr }
+liveins:
+  - { reg: '$v8', virtual-reg: '%0' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $v8
+
+    ; CHECK-LABEL: name: vmv_x_s
+    ; CHECK: liveins: $v8
+    ; CHECK: [[COPY:%[0-9]+]]:vr = COPY $v8
+    ; CHECK: dead $x0 = PseudoVSETVLI killed $x0, 88, implicit-def $vl, implicit-def $vtype, implicit $vl
+    ; CHECK: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[COPY]], 6, implicit $vtype
+    ; CHECK: $x10 = COPY [[PseudoVMV_X_S_M1_]]
+    ; CHECK: PseudoRET implicit $x10
+    %0:vr = COPY $v8
+    %1:gpr = PseudoVMV_X_S_M1 %0, 6
+    $x10 = COPY %1
+    PseudoRET implicit $x10
+
+...
+---
+name:            add_v2i64
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: vr }
+  - { id: 3, class: vr }
+  - { id: 4, class: vr }
+liveins:
+  - { reg: '$x10', virtual-reg: '%0' }
+  - { reg: '$x11', virtual-reg: '%1' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: add_v2i64
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK: dead %5:gpr = PseudoVSETIVLI 2, 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY1]], 2, 6, implicit $vl, implicit $vtype :: (load 16 from %ir.x)
+    ; CHECK: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY]], 2, 6, implicit $vl, implicit $vtype :: (load 16 from %ir.y)
+    ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE64_V_M1_]], killed [[PseudoVLE64_V_M1_1]], 2, 6, implicit $vl, implicit $vtype
+    ; CHECK: PseudoVSE64_V_M1 killed [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6, implicit $vl, implicit $vtype :: (store 16 into %ir.x)
+    ; CHECK: PseudoRET
+    %1:gpr = COPY $x11
+    %0:gpr = COPY $x10
+    %2:vr = PseudoVLE64_V_M1 %0, 2, 6 :: (load 16 from %ir.x)
+    %3:vr = PseudoVLE64_V_M1 %1, 2, 6 :: (load 16 from %ir.y)
+    %4:vr = PseudoVADD_VV_M1 killed %2, killed %3, 2, 6
+    PseudoVSE64_V_M1 killed %4, %0, 2, 6 :: (store 16 into %ir.x)
+    PseudoRET
+
+...
+---
+name:            vreduce_add_v2i64
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: vr }
+  - { id: 2, class: vr }
+  - { id: 3, class: vr }
+  - { id: 4, class: vr }
+  - { id: 5, class: gpr }
+liveins:
+  - { reg: '$x10', virtual-reg: '%0' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $x10
+
+    ; CHECK-LABEL: name: vreduce_add_v2i64
+    ; CHECK: liveins: $x10
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK: dead %8:gpr = PseudoVSETIVLI 2, 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY]], 2, 6, implicit $vl, implicit $vtype :: (load 16 from %ir.x)
+    ; CHECK: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK: dead %7:gpr = PseudoVSETIVLI 2, 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVREDSUM_VS_M1_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1 [[DEF]], killed [[PseudoVLE64_V_M1_]], killed [[PseudoVMV_V_I_M1_]], 2, 6, implicit $vl, implicit $vtype
+    ; CHECK: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 killed [[PseudoVREDSUM_VS_M1_]], 6, implicit $vtype
+    ; CHECK: $x10 = COPY [[PseudoVMV_X_S_M1_]]
+    ; CHECK: PseudoRET implicit $x10
+    %0:gpr = COPY $x10
+    %1:vr = PseudoVLE64_V_M1 %0, 2, 6 :: (load 16 from %ir.x)
+    %2:vr = PseudoVMV_V_I_M1 0, $x0, 6
+    %4:vr = IMPLICIT_DEF
+    %3:vr = PseudoVREDSUM_VS_M1 %4, killed %1, killed %2, 2, 6
+    %5:gpr = PseudoVMV_X_S_M1 killed %3, 6
+    $x10 = COPY %5
+    PseudoRET implicit $x10
+
+...
+---
+name:            vsetvli_add
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vr }
+  - { id: 1, class: vr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+  - { id: 4, class: vr }
+liveins:
+  - { reg: '$v8', virtual-reg: '%0' }
+  - { reg: '$v9', virtual-reg: '%1' }
+  - { reg: '$x10', virtual-reg: '%2' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9, $x10
+
+    ; CHECK-LABEL: name: vsetvli_add
+    ; CHECK: liveins: $v8, $v9, $x10
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK: [[COPY1:%[0-9]+]]:vr = COPY $v9
+    ; CHECK: [[COPY2:%[0-9]+]]:vr = COPY $v8
+    ; CHECK: [[PseudoVSETVLI:%[0-9]+]]:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
+    ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: $v8 = COPY [[PseudoVADD_VV_M1_]]
+    ; CHECK: PseudoRET implicit $v8
+    %2:gpr = COPY $x10
+    %1:vr = COPY $v9
+    %0:vr = COPY $v8
+    %3:gpr = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype
+    %4:vr = PseudoVADD_VV_M1 %0, %1, killed %3, 6
+    $v8 = COPY %4
+    PseudoRET implicit $v8
+
+...

llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -march=riscv64 -mattr=+experimental-v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
   target triple = "riscv64"
 
   define void @zvlsseg_spill(i64 *%base, i64 %vl) {
     ret void
   }
bb.0:
     ; CHECK: VS1R_V killed $v8, killed renamable $x10
     ; CHECK: $x10 = PseudoReadVLENB
     ; CHECK: $x10 = SLLI killed $x10, 3
     ; CHECK: $x2 = ADD $x2, killed $x10
     ; CHECK: $x2 = frame-destroy ADDI $x2, 16
     ; CHECK: PseudoRET
     %0:gpr = COPY $x10
     %1:gpr = COPY $x11
-    $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 %0, %1, 6, implicit $vl, implicit $vtype
+    $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 %0, %1, 6
     PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0, $x0
     renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 %stack.0, $x0
     VS1R_V killed $v8, %0:gpr
     PseudoRET
 ...