[RISCV] Optimize SEW=64 shifts by splat on RV32.

[craig.topper]

Summary

SEW=64 shifts only uses the log2(64) bits of shift amount. If we're
splatting a 64 bit value in 2 parts, we can avoid splatting the
upper bits and just let the low bits be sign extended. They won't
be read anyway.

For the purposes of SelectionDAG semantics of the generic ISD opcodes,
if hi was non-zero or bit 31 of the low is 1, the shift was already
undefined so it should be ok to replace high with sign extend of low.

In order do be able to find the split i64 value before it becomes
a stack operation, I added a new ISD opcode that will be expanded
to the stack spill in PreprocessISelDAG. This new node is conceptually
similar to BuildPairF64, but I expanded earlier so that we could
go through regular isel to get the right VLSE opcode for the LMUL.
BuildPairF64 is expanded in a CustomInserter.

[craig.topper]

Ping

[frasercrmck]

I probably don't have the full picture here, but I was wondering if there was a generic "simplify demanded bits" we could hook this node into, since presumably LLVM already knows that only those bits of the shift are used. Does SimplifyDemandedBitsForTargetNode not apply here?

[craig.topper]

In D102521#2777262, @frasercrmck wrote:

I probably don't have the full picture here, but I was wondering if there was a generic "simplify demanded bits" we could hook this node into, since presumably LLVM already knows that only those bits of the shift are used. Does SimplifyDemandedBitsForTargetNode not apply here?

I think for generic shift, nodes llvm considers all bits of the shift amount to be demanded. It's not generally safe because not all targets have shift instructions that modulo the shift amount.

[frasercrmck]

In D102521#2777568, @craig.topper wrote:

In D102521#2777262, @frasercrmck wrote:

I probably don't have the full picture here, but I was wondering if there was a generic "simplify demanded bits" we could hook this node into, since presumably LLVM already knows that only those bits of the shift are used. Does SimplifyDemandedBitsForTargetNode not apply here?

I think for generic shift, nodes llvm considers all bits of the shift amount to be demanded. It's not generally safe because not all targets have shift instructions that modulo the shift amount.

Interesting, that makes sense. Thanks.

Then this is probably the best way of doing it. LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

StringRef getPassName() const override {
     return "RISCV DAG->DAG Pattern Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<RISCVSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
+  void PreprocessISelDAG() override;
   void PostprocessISelDAG() override;
 
   void Select(SDNode *Node) override;
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   bool SelectAddrFI(SDValue Addr, SDValue &Base);

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines an instruction selector for the RISCV target.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVISelDAGToDAG.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "MCTargetDesc/RISCVMatInt.h"
 #include "RISCVISelLowering.h"
+#include "RISCVMachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/Support/Alignment.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 

 #define GET_RISCVVLETable_IMPL
 #define GET_RISCVVSETable_IMPL
 #define GET_RISCVVLXTable_IMPL
 #define GET_RISCVVSXTable_IMPL
 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCV
 } // namespace llvm
 
+void RISCVDAGToDAGISel::PreprocessISelDAG() {
+  for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
+                                       E = CurDAG->allnodes_end();
+       I != E;) {
+    SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
+
+    // Lower SPLAT_VECTOR_SPLIT_I64 to two scalar stores and a stride 0 vector
+    // load. Done after lowering and combining so that we have a chance to
+    // optimize this to VMV_V_X_VL when the upper bits aren't needed.
+    if (N->getOpcode() != RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL)
+      continue;
+
+    assert(N->getNumOperands() == 3 && "Unexpected number of operands");
+    MVT VT = N->getSimpleValueType(0);
+    SDValue Lo = N->getOperand(0);
+    SDValue Hi = N->getOperand(1);
+    SDValue VL = N->getOperand(2);
+    assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() &&
+           Lo.getValueType() == MVT::i32 && Hi.getValueType() == MVT::i32 &&
+           "Unexpected VTs!");
+    MachineFunction &MF = CurDAG->getMachineFunction();
+    RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
+    SDLoc DL(N);
+
+    // We use the same frame index we use for moving two i32s into 64-bit FPR.
+    // This is an analogous operation.
+    int FI = FuncInfo->getMoveF64FrameIndex(MF);
+    MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
+    const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
+    SDValue StackSlot =
+        CurDAG->getFrameIndex(FI, TLI.getPointerTy(CurDAG->getDataLayout()));
+
+    SDValue Chain = CurDAG->getEntryNode();
+    Lo = CurDAG->getStore(Chain, DL, Lo, StackSlot, MPI, Align(8));
+
+    SDValue OffsetSlot =
+        CurDAG->getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), DL);
+    Hi = CurDAG->getStore(Chain, DL, Hi, OffsetSlot, MPI.getWithOffset(4),
+                          Align(8));
+
+    Chain = CurDAG->getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
+
+    SDVTList VTs = CurDAG->getVTList({VT, MVT::Other});
+    SDValue IntID =
+        CurDAG->getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64);
+    SDValue Ops[] = {Chain, IntID, StackSlot,
+                     CurDAG->getRegister(RISCV::X0, MVT::i64), VL};
+
+    SDValue Result = CurDAG->getMemIntrinsicNode(
+        ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64, MPI, Align(8),
+        MachineMemOperand::MOLoad);
+
+    // We're about to replace all uses of the SPLAT_VECTOR_SPLIT_I64 with the
+    // vlse we created.  This will cause general havok on the dag because
+    // anything below the conversion could be folded into other existing nodes.
+    // To avoid invalidating 'I', back it up to the convert node.
+    --I;
+    CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
+
+    // Now that we did that, the node is dead.  Increment the iterator to the
+    // next node to process, then delete N.
+    ++I;
+    CurDAG->DeleteNode(N);
+  }
+}
+
 void RISCVDAGToDAGISel::PostprocessISelDAG() {
   doPeepholeLoadStoreADDI();
 }
 
 static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
                          MVT XLenVT) {
   RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64);
 

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   VMV_X_S,
   // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
   VMV_S_X_VL,
   // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
   VFMV_S_F_VL,
   // Splats an i64 scalar to a vector type (with element type i64) where the
   // scalar is a sign-extended i32.
   SPLAT_VECTOR_I64,
+  // Splats an 64-bit value that has been split into two i32 parts. This is
+  // expanded late to two scalar stores and a stride 0 vector load.
+  SPLAT_VECTOR_SPLIT_I64_VL,
   // Read VLENB CSR
   READ_VLENB,
   // Truncates a RVV integer vector by one power-of-two. Carries both an extra
   // mask and VL operand.
   TRUNCATE_VECTOR_VL,
   // Matches the semantics of vslideup/vslidedown. The first operand is the
   // pass-thru operand, the second is the source vector, the third is the
   // XLenVT index (either constant or non-constant), the fourth is the mask

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setTargetDAGCombine(ISD::AND);
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::XOR);
   if (Subtarget.hasStdExtV()) {
     setTargetDAGCombine(ISD::FCOPYSIGN);
     setTargetDAGCombine(ISD::MGATHER);
     setTargetDAGCombine(ISD::MSCATTER);
+    setTargetDAGCombine(ISD::SRA);
+    setTargetDAGCombine(ISD::SRL);
+    setTargetDAGCombine(ISD::SHL);
   }
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
                                             LLVMContext &Context,
                                             EVT VT) const {
   if (!VT.isVector())
     return getPointerTy(DL);
if (!DAG.shouldOptForSize() &&
     }
 
     return Vec;
   }
 
   return SDValue();
 }
 
-// Use a stack slot to splat the two i32 values in Lo/Hi to the vector desired
-// vector nxvXi64 VT.
-static SDValue splatPartsI64ThroughStack(const SDLoc &DL, MVT VT, SDValue Lo,
-                                         SDValue Hi, SDValue VL,
-                                         SelectionDAG &DAG) {
-  assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() &&
-         Lo.getValueType() == MVT::i32 && Hi.getValueType() == MVT::i32 &&
-         "Unexpected VTs!");
-  MachineFunction &MF = DAG.getMachineFunction();
-  RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
-
-  // We use the same frame index we use for moving two i32s into 64-bit FPR.
-  // This is an analogous operation.
-  int FI = FuncInfo->getMoveF64FrameIndex(MF);
-  MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  SDValue StackSlot =
-      DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()));
-
-  SDValue Chain = DAG.getEntryNode();
-  Lo = DAG.getStore(Chain, DL, Lo, StackSlot, MPI, Align(8));
-
-  SDValue OffsetSlot =
-      DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), DL);
-  Hi = DAG.getStore(Chain, DL, Hi, OffsetSlot, MPI.getWithOffset(4), Align(8));
-
-  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
-
-  SDVTList VTs = DAG.getVTList({VT, MVT::Other});
-  SDValue IntID = DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64);
-  SDValue Ops[] = {Chain, IntID, StackSlot,
-                   DAG.getRegister(RISCV::X0, MVT::i64), VL};
-
-  return DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64,
-                                 MPI, Align(8), MachineMemOperand::MOLoad);
-}
-
 static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo,
                                    SDValue Hi, SDValue VL, SelectionDAG &DAG) {
   if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
     int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
     int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
     // If Hi constant is all the same sign bit as Lo, lower this as a custom
     // node in order to try and match RVV vector/scalar instructions.
     if ((LoC >> 31) == HiC)
       return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL);
   }
 
   // Fall back to a stack store and stride x0 vector load.
-  return splatPartsI64ThroughStack(DL, VT, Lo, Hi, VL, DAG);
+  return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Lo, Hi, VL);
 }
 
 // Called by type legalization to handle splat of i64 on RV32.
 // FIXME: We can optimize this when the type has sign or zero bits in one
 // of the halves.
 static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar,
                                    SDValue VL, SelectionDAG &DAG) {
   assert(Scalar.getValueType() == MVT::i64 && "Unexpected VT!");
SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
 
   // Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended.
   if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo &&
       isa<ConstantSDNode>(Hi.getOperand(1)) &&
       Hi.getConstantOperandVal(1) == 31)
     return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo);
 
   // Fall back to use a stack store and stride x0 vector load. Use X0 as VL.
-  return splatPartsI64ThroughStack(DL, VecVT, Lo, Hi,
-                                   DAG.getRegister(RISCV::X0, MVT::i64), DAG);
+  return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VecVT, Lo, Hi,
+                     DAG.getRegister(RISCV::X0, MVT::i64));
 }
 
 // Custom-lower extensions from mask vectors by using a vselect either with 1
 // for zero/any-extension or -1 for sign-extension:
 //   (vXiN = (s|z)ext vXi1:vmask) -> (vXiN = vselect vmask, (-1 or 1), 0)
 // Note that any-extension is lowered identically to zero-extension.
 SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
                                                 int64_t ExtTrueVal) const {
case ISD::MSCATTER: {
     }
     const auto *MSN = cast<MaskedScatterSDNode>(N);
     return DAG.getMaskedScatter(
         N->getVTList(), MGSN->getMemoryVT(), DL,
         {MGSN->getChain(), MSN->getValue(), MGSN->getMask(), MGSN->getBasePtr(),
          Index, MGSN->getScale()},
         MGSN->getMemOperand(), NewIndexTy, MSN->isTruncatingStore());
   }
+  case RISCVISD::SRA_VL:
+  case RISCVISD::SRL_VL:
+  case RISCVISD::SHL_VL: {
+    SDValue ShAmt = N->getOperand(1);
+    if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
+      // We don't need the upper 32 bits of a 64-bit element for a shift amount.
+      SDLoc DL(N);
+      SDValue VL = N->getOperand(3);
+      EVT VT = N->getValueType(0);
+      ShAmt =
+          DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, ShAmt.getOperand(0), VL);
+      return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt,
+                         N->getOperand(2), N->getOperand(3));
+    }
+    break;
+  }
+  case ISD::SRA:
+  case ISD::SRL:
+  case ISD::SHL: {
+    SDValue ShAmt = N->getOperand(1);
+    if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
+      // We don't need the upper 32 bits of a 64-bit element for a shift amount.
+      SDLoc DL(N);
+      EVT VT = N->getValueType(0);
+      ShAmt =
+          DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VT, ShAmt.getOperand(0));
+      return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt);
+    }
+    break;
+  }
   }
 
   return SDValue();
 }
 
 bool RISCVTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
   // The following folds are only desirable if `(OP _, c1 << c2)` can be
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(BDECOMPRESS)
   NODE_NAME_CASE(BDECOMPRESSW)
   NODE_NAME_CASE(VMV_V_X_VL)
   NODE_NAME_CASE(VFMV_V_F_VL)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(VMV_S_X_VL)
   NODE_NAME_CASE(VFMV_S_F_VL)
   NODE_NAME_CASE(SPLAT_VECTOR_I64)
+  NODE_NAME_CASE(SPLAT_VECTOR_SPLIT_I64_VL)
   NODE_NAME_CASE(READ_VLENB)
   NODE_NAME_CASE(TRUNCATE_VECTOR_VL)
   NODE_NAME_CASE(VSLIDEUP_VL)
   NODE_NAME_CASE(VSLIDE1UP_VL)
   NODE_NAME_CASE(VSLIDEDOWN_VL)
   NODE_NAME_CASE(VSLIDE1DOWN_VL)
   NODE_NAME_CASE(VID_VL)
   NODE_NAME_CASE(VFNCVT_ROD_VL)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 
 define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
 ; CHECK-LABEL: vnsra_v8i16_v8i8_scalar:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vnsra.wx v25, v8, a0
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
; CHECK-NEXT:    ret
   %insert = insertelement <4 x i32> undef, i32 %y, i32 0
   %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
   %a = ashr <4 x i32> %x, %splat
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <2 x i32> @vnsra_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
-; RV32-LABEL: vnsra_v2i64_v2i32_scalar:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsra.vv v25, v8, v25
-; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; RV32-NEXT:    vnsrl.wi v8, v25, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vnsra_v2i64_v2i32_scalar:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; RV64-NEXT:    vnsra.wx v25, v8, a0
-; RV64-NEXT:    vmv1r.v v8, v25
-; RV64-NEXT:    ret
+; CHECK-LABEL: vnsra_v2i64_v2i32_scalar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsra.wx v25, v8, a0
+; CHECK-NEXT:    vmv1r.v v8, v25
+; CHECK-NEXT:    ret
   %insert = insertelement <2 x i64> undef, i64 %y, i32 0
   %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
   %a = ashr <2 x i64> %x, %splat
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <8 x i8> @vnsra_v8i16_v8i8_imm(<8 x i16> %x) {
; CHECK-NEXT:    ret
   %insert = insertelement <4 x i32> undef, i32 %y, i32 0
   %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
   %a = lshr <4 x i32> %x, %splat
   %b = trunc <4 x i32> %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <2 x i32> @vnsrl_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
-; RV32-LABEL: vnsrl_v2i64_v2i32_scalar:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsrl.vv v25, v8, v25
-; RV32-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; RV32-NEXT:    vnsrl.wi v8, v25, 0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vnsrl_v2i64_v2i32_scalar:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
-; RV64-NEXT:    vnsrl.wx v25, v8, a0
-; RV64-NEXT:    vmv1r.v v8, v25
-; RV64-NEXT:    ret
+; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e32,mf2,ta,mu
+; CHECK-NEXT:    vnsrl.wx v25, v8, a0
+; CHECK-NEXT:    vmv1r.v v8, v25
+; CHECK-NEXT:    ret
   %insert = insertelement <2 x i64> undef, i64 %y, i32 0
   %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
   %a = lshr <2 x i64> %x, %splat
   %b = trunc <2 x i64> %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <8 x i8> @vnsrl_v8i16_v8i8_imm(<8 x i16> %x) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll

; CHECK-NEXT:    ret
   %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
   %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
   ret <2 x i64> %v
 }
 
 define <2 x i64> @vsll_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v25, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
   %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
   ret <2 x i64> %v
 }
 
 define <2 x i64> @vsll_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v2i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v25
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v2i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @vsll_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v4i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v26, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
   %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @vsll_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v4i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v26
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v4i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
   %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
   ret <8 x i64> %v
 }
 
 define <8 x i64> @vsll_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v28, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
   %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
   ret <8 x i64> %v
 }
 
 define <8 x i64> @vsll_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v8i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v28
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v8i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
   %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
   ret <16 x i64> %v
 }
 
 define <16 x i64> @vsll_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v16i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v16, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
   %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
   ret <16 x i64> %v
 }
 
 define <16 x i64> @vsll_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_v16i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_v16i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll

; CHECK-NEXT:    ret
   %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
   %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
   ret <2 x i64> %v
 }
 
 define <2 x i64> @vsra_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v25, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
   %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
   ret <2 x i64> %v
 }
 
 define <2 x i64> @vsra_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v2i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v25
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v2i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @vsra_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v4i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v26, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
   %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @vsra_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v4i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v26
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v4i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
   %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
   ret <8 x i64> %v
 }
 
 define <8 x i64> @vsra_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v28, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
   %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
   ret <8 x i64> %v
 }
 
 define <8 x i64> @vsra_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v8i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v28
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v8i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
   %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
   ret <16 x i64> %v
 }
 
 define <16 x i64> @vsra_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v16i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v16, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
   %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
   ret <16 x i64> %v
 }
 
 define <16 x i64> @vsra_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_v16i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_v16i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll

; CHECK-NEXT:    ret
   %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
   %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
   ret <2 x i64> %v
 }
 
 define <2 x i64> @vsrl_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v25, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
   %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
   ret <2 x i64> %v
 }
 
 define <2 x i64> @vsrl_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v2i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v25
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v2i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @vsrl_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v4i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v26, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
   %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @vsrl_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v4i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v26
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v4i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
   %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
   ret <8 x i64> %v
 }
 
 define <8 x i64> @vsrl_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v28, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
   %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
   ret <8 x i64> %v
 }
 
 define <8 x i64> @vsrl_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v8i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v28
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v8i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
   %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
   ret <16 x i64> %v
 }
 
 define <16 x i64> @vsrl_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v16i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v16, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
   %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
   ret <16 x i64> %v
 }
 
 define <16 x i64> @vsrl_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_v16i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_v16i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = shl <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vshl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv1i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v25, (a0), zero
-; CHECK-NEXT:    vsll.vv v8, v8, v25
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = shl <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vshl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = shl <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vshl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v26, (a0), zero
-; CHECK-NEXT:    vsll.vv v8, v8, v26
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = shl <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vshl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = shl <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vshl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv4i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v28, (a0), zero
-; CHECK-NEXT:    vsll.vv v8, v8, v28
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = shl <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vshl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = shl <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vshl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv8i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-NEXT:    vsll.vv v8, v8, v16
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = shl <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vshl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {

llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll

; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i64> @llvm.vp.shl.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @vsll_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv1i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v25, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i64> @llvm.vp.shl.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @vsll_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv1i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v25
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv1i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
   %v = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @vsll_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v26, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %v = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @vsll_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv2i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v26
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv2i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i64> @llvm.vp.shl.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @vsll_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv4i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v28, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i64> @llvm.vp.shl.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @vsll_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv4i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v28
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv4i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i64> @llvm.vp.shl.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i64> %v
 }
 
 define <vscale x 8 x i64> @vsll_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v16, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i64> @llvm.vp.shl.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i64> %v
 }
 
 define <vscale x 8 x i64> @vsll_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsll_vx_nxv8i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsll.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsll.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsll_vx_nxv8i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsll.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll

 ; CHECK-NEXT:    ret
   %vc = ashr <vscale x 1 x i64> %va, %vb
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsra_vx_nxv1i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v25, (a0), zero
-; CHECK-NEXT:    vsra.vv v8, v8, v25
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsra.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = ashr <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vsra_vi_nxv1i64_0(<vscale x 1 x i64> %va) {

 ; CHECK-NEXT:    ret
   %vc = ashr <vscale x 2 x i64> %va, %vb
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsra_vx_nxv2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v26, (a0), zero
-; CHECK-NEXT:    vsra.vv v8, v8, v26
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsra.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = ashr <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vsra_vi_nxv2i64_0(<vscale x 2 x i64> %va) {

 ; CHECK-NEXT:    ret
   %vc = ashr <vscale x 4 x i64> %va, %vb
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsra_vx_nxv4i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v28, (a0), zero
-; CHECK-NEXT:    vsra.vv v8, v8, v28
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsra.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = ashr <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vsra_vi_nxv4i64_0(<vscale x 4 x i64> %va) {

 ; CHECK-NEXT:    ret
   %vc = ashr <vscale x 8 x i64> %va, %vb
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsra_vx_nxv8i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-NEXT:    vsra.vv v8, v8, v16
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsra.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = ashr <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vsra_vi_nxv8i64_0(<vscale x 8 x i64> %va) {

llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll

; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv1i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v25, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @vsra_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv1i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v25
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv1i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
   %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v26, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @vsra_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv2i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v26
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv2i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv4i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v28, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @vsra_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv4i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v28
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv4i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i64> %v
 }
 
 define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v16, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i64> %v
 }
 
 define <vscale x 8 x i64> @vsra_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsra_vx_nxv8i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsra.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsra.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsra_vx_nxv8i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsra.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = lshr <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsrl_vx_nxv1i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v25, (a0), zero
-; CHECK-NEXT:    vsrl.vv v8, v8, v25
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = lshr <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vsrl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = lshr <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vsrl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsrl_vx_nxv2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v26, (a0), zero
-; CHECK-NEXT:    vsrl.vv v8, v8, v26
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = lshr <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vsrl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = lshr <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vsrl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsrl_vx_nxv4i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v28, (a0), zero
-; CHECK-NEXT:    vsrl.vv v8, v8, v28
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = lshr <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vsrl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = lshr <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vsrl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vsrl_vx_nxv8i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sw a1, 12(sp)
-; CHECK-NEXT:    sw a0, 8(sp)
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    addi a0, sp, 8
-; CHECK-NEXT:    vlse64.v v16, (a0), zero
-; CHECK-NEXT:    vsrl.vv v8, v8, v16
-; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = lshr <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vsrl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {

llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll

; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i64> @llvm.vp.lshr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv1i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v25, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %v = call <vscale x 1 x i64> @llvm.vp.lshr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @vsrl_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv1i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v25, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m1,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v25
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv1i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
   %v = call <vscale x 2 x i64> @llvm.vp.lshr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @vsrl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv2i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v26, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %v = call <vscale x 2 x i64> @llvm.vp.lshr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @vsrl_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv2i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v26, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m2,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v26
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv2i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i64> @llvm.vp.lshr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @vsrl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv4i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v28, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i64> @llvm.vp.lshr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @vsrl_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv4i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v28, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m4,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v28
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv4i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
; CHECK-NEXT:    ret
   %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i64> @llvm.vp.lshr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i64> %v
 }
 
 define <vscale x 8 x i64> @vsrl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v16, v0.t
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0, v0.t
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %v = call <vscale x 8 x i64> @llvm.vp.lshr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
   ret <vscale x 8 x i64> %v
 }
 
 define <vscale x 8 x i64> @vsrl_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
 ; RV32-LABEL: vsrl_vx_nxv8i64_unmasked:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
-; RV32-NEXT:    vsrl.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    vsetvli a1, a2, e64,m8,ta,mu
+; RV32-NEXT:    vsrl.vx v8, v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vsrl_vx_nxv8i64_unmasked:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
 ; RV64-NEXT:    vsrl.vx v8, v8, a0
 ; RV64-NEXT:    ret
   %elt.head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0