[RISCV] Lower splats of non-constant i1s as SETCCs

[frasercrmck]

Summary

This patch adds support for splatting i1 types to fixed-length or
scalable vector types. It does so by lowering the operation to a SETCC
of the equivalent i8 type.

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

167

I was wondering if vmv.v.i v26, 0 ; vmsne.vx v0, v26, a0 would be faster. Any insights there?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1365

Don't we need to mask out all but bit 0 of Splat? I don't think those bits are defined.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1365

Yeah I think you're right. I was going by the "zero or one" boolean contents contract which I thought covered us when the i1s were widened to XLEN but, thinking about it, that probably doesn't cover the operands of BUILD_VECTOR or SPLAT_VECTOR. Right?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1365

It applies to the output of SETCC or the expectations of SELECT. But the i1 could have been produced by a TRUNCATE for example in which case it wouldn't have to respect boolean contents.

DAG combine should be able to delete the AND if the input came from SETCC, though X86 detects that case directly in lowering. See LowerBUILD_VECTORvXi1 right around the FIXME comment in that function.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1365

Yeah, makes sense. I was hoping to hear something like that. I added a couple of tests such as i1 zeroext and where the i1 comes from an icmp and I verified that those are correctly optimized. You should be able to see those further down somewhere.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1365

Your last comment make it sound like you uploaded another patch, but I only see one patch in the history.

[frasercrmck]

• rebase
• add explicit truncation of splatted value down to one bit

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1365

Oh dear yeah I forgot to upload the latest diff. Thanks!

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

private:
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
                              int64_t ExtTrueVal) const;
   SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (!Subtarget.is64Bit()) {
       setOperationAction(ISD::VECREDUCE_XOR, MVT::i64, Custom);
       setOperationAction(ISD::VECREDUCE_SMAX, MVT::i64, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, MVT::i64, Custom);
       setOperationAction(ISD::VECREDUCE_UMAX, MVT::i64, Custom);
       setOperationAction(ISD::VECREDUCE_UMIN, MVT::i64, Custom);
     }
 
     for (MVT VT : BoolVecVTs) {
-      setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
+      setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
 
       // Mask VTs are custom-expanded into a series of standard nodes
       setOperationAction(ISD::TRUNCATE, VT, Custom);
       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
       setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
 
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
 
if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
         // mask type; bitcast for the final result.
         assert(VT.getSizeInBits() == IntegerViaVecVT.getSizeInBits());
         Vec = DAG.getBitcast(VT, Vec);
       }
 
       return Vec;
     }
 
+    // A splat can be lowered as a SETCC. For each fixed-length mask vector
+    // type, we have a legal equivalently-sized i8 type, so we can use that.
+    if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
+      MVT InterVT = VT.changeVectorElementType(MVT::i8);
+      Splat = DAG.getSplatBuildVector(InterVT, DL, Splat);
+      SDValue Zero = DAG.getConstant(0, DL, InterVT);
+      return DAG.getSetCC(DL, VT, Splat, Zero, ISD::SETNE);
+    }
+
     return SDValue();
   }
 
   if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
     unsigned Opc = VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL
                                         : RISCVISD::VMV_V_X_VL;
     Splat = DAG.getNode(Opc, DL, ContainerVT, Splat, VL);
     return convertFromScalableVector(VT, Splat, DAG, Subtarget);
if (Op.getOperand(0).getValueType().isVector() &&
         Op.getOperand(0).getValueType().getVectorElementType() == MVT::i1)
       return lowerVectorMaskExt(Op, DAG, /*ExtVal*/ 1);
     return lowerFixedLengthVectorExtendToRVV(Op, DAG, RISCVISD::VZEXT_VL);
   case ISD::SIGN_EXTEND:
     if (Op.getOperand(0).getValueType().isVector() &&
         Op.getOperand(0).getValueType().getVectorElementType() == MVT::i1)
       return lowerVectorMaskExt(Op, DAG, /*ExtVal*/ -1);
     return lowerFixedLengthVectorExtendToRVV(Op, DAG, RISCVISD::VSEXT_VL);
+  case ISD::SPLAT_VECTOR:
+    assert(Op.getValueType().getVectorElementType() == MVT::i1 &&
+           "Unexpected SPLAT_VECTOR lowering");
+    return lowerVectorMaskSplat(Op, DAG);
   case ISD::SPLAT_VECTOR_PARTS:
     return lowerSPLAT_VECTOR_PARTS(Op, DAG);
   case ISD::INSERT_VECTOR_ELT:
     return lowerINSERT_VECTOR_ELT(Op, DAG);
   case ISD::EXTRACT_VECTOR_ELT:
     return lowerEXTRACT_VECTOR_ELT(Op, DAG);
   case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
 
   Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
   Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
 
   SDValue Parts[2] = {Lo, Hi};
   return DAG.getMergeValues(Parts, DL);
 }
 
+// Lower splats of i1 types to SETCC. For each mask vector type, we have a
+// legal equivalently-sized i8 type, so we can use that as a go-between.
+SDValue RISCVTargetLowering::lowerVectorMaskSplat(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SDValue SplatVal = Op.getOperand(0);
+  // All-zeros or all-ones splats are handled specially.
+  if (isa<ConstantSDNode>(SplatVal))
+    return Op;
+  SDLoc DL(Op);
+  MVT VT = Op.getSimpleValueType();
+  MVT InterVT = VT.changeVectorElementType(MVT::i8);
+  SDValue LHS = DAG.getSplatVector(InterVT, DL, SplatVal);
+  SDValue Zero = DAG.getConstant(0, DL, InterVT);
+  return DAG.getSetCC(DL, VT, LHS, Zero, ISD::SETNE);
+}
+
 // Custom-lower a SPLAT_VECTOR_PARTS where XLEN<SEW, as the SEW element type is
 // illegal (currently only vXi64 RV32).
 // FIXME: We could also catch non-constant sign-extended i32 values and lower
 // them to SPLAT_VECTOR_I64
 SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
   MVT VecVT = Op.getSimpleValueType();

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

 ; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <2 x i1> zeroinitializer, <2 x i1>* %x
   ret void
 }
 
+define void @splat_v1i1(<1 x i1>* %x, i1 %y) {
+; CHECK-LABEL: splat_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vsetivli a1, 1, e8,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v26, v25, 0
+; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vi v25, v26, 0
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  %a = insertelement <1 x i1> undef, i1 %y, i32 0
+  %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer
+  store <1 x i1> %b, <1 x i1>* %x
+  ret void
+}
+
 define void @splat_ones_v4i1(<4 x i1>* %x) {
 ; CHECK-LABEL: splat_ones_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
   ret void
 }
 
+define void @splat_v4i1(<4 x i1>* %x, i1 %y) {
+; CHECK-LABEL: splat_v4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a2, 4, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vsetivli a1, 4, e8,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v26, v25, 0
+; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vi v25, v26, 0
+; CHECK-NEXT:    vse1.v v25, (a0)
+; CHECK-NEXT:    ret
+  %a = insertelement <4 x i1> undef, i1 %y, i32 0
+  %b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer
+  store <4 x i1> %b, <4 x i1>* %x
+  ret void
+}
+
 define void @splat_zeros_v8i1(<8 x i1>* %x) {
 ; CHECK-LABEL: splat_zeros_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmclr.m v25
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <8 x i1> zeroinitializer, <8 x i1>* %x
   ret void
 }
 
+define void @splat_v8i1(<8 x i1>* %x, i1 %y) {
+; CHECK-LABEL: splat_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    vmsne.vi v26, v25, 0
+; CHECK-NEXT:    vse1.v v26, (a0)
+; CHECK-NEXT:    ret
+  %a = insertelement <8 x i1> undef, i1 %y, i32 0
+  %b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer
+  store <8 x i1> %b, <8 x i1>* %x
+  ret void
+}
+
 define void @splat_ones_v16i1(<16 x i1>* %x) {
 ; CHECK-LABEL: splat_ones_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; CHECK-NEXT:    vmset.m v25
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i1>* %x
   ret void
 }
 
+define void @splat_v16i1(<16 x i1>* %x, i1 %y) {
+; CHECK-LABEL: splat_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    vmsne.vi v26, v25, 0
+; CHECK-NEXT:    vse1.v v26, (a0)
+; CHECK-NEXT:    ret
+  %a = insertelement <16 x i1> undef, i1 %y, i32 0
+  %b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer
+  store <16 x i1> %b, <16 x i1>* %x
+  ret void
+}
+
 define void @splat_zeros_v32i1(<32 x i1>* %x) {
 ; LMULMAX2-LABEL: splat_zeros_v32i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a1, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vmclr.m v25
 ; LMULMAX2-NEXT:    vse1.v v25, (a0)
 ; LMULMAX2-NEXT:    ret

 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    addi a0, a0, 2
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   store <32 x i1> zeroinitializer, <32 x i1>* %x
   ret void
 }
 
+define void @splat_v32i1(<32 x i1>* %x, i1 %y) {
+; LMULMAX2-LABEL: splat_v32i1:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a2, zero, 32
+; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
+; LMULMAX2-NEXT:    vmv.v.x v26, a1
+; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
+; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-RV32-LABEL: splat_v32i1:
+; LMULMAX1-RV32:       # %bb.0:
+; LMULMAX1-RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.v.x v25, a1
+; LMULMAX1-RV32-NEXT:    vmsne.vi v26, v25, 0
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV32-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV32-NEXT:    vse1.v v26, (a0)
+; LMULMAX1-RV32-NEXT:    ret
+;
+; LMULMAX1-RV64-LABEL: splat_v32i1:
+; LMULMAX1-RV64:       # %bb.0:
+; LMULMAX1-RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmv.v.x v25, a1
+; LMULMAX1-RV64-NEXT:    vmsne.vi v26, v25, 0
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV64-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV64-NEXT:    vse1.v v26, (a0)
+; LMULMAX1-RV64-NEXT:    ret
+  %a = insertelement <32 x i1> undef, i1 %y, i32 0
+  %b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer
+  store <32 x i1> %b, <32 x i1>* %x
+  ret void
+}
+
 define void @splat_ones_v64i1(<64 x i1>* %x) {
 ; LMULMAX2-LABEL: splat_ones_v64i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a1, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vmset.m v25
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)

 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    addi a0, a0, 2
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x
   ret void
 }
+
+define void @splat_v64i1(<64 x i1>* %x, i1 %y) {
+; LMULMAX2-LABEL: splat_v64i1:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    addi a2, zero, 32
+; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
+; LMULMAX2-NEXT:    vmv.v.x v26, a1
+; LMULMAX2-NEXT:    vmsne.vi v25, v26, 0
+; LMULMAX2-NEXT:    addi a1, a0, 4
+; LMULMAX2-NEXT:    vse1.v v25, (a1)
+; LMULMAX2-NEXT:    vse1.v v25, (a0)
+; LMULMAX2-NEXT:    ret
+;
+; LMULMAX1-RV32-LABEL: splat_v64i1:
+; LMULMAX1-RV32:       # %bb.0:
+; LMULMAX1-RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.v.x v25, a1
+; LMULMAX1-RV32-NEXT:    vmsne.vi v26, v25, 0
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 6
+; LMULMAX1-RV32-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 4
+; LMULMAX1-RV32-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV32-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV32-NEXT:    vse1.v v26, (a0)
+; LMULMAX1-RV32-NEXT:    ret
+;
+; LMULMAX1-RV64-LABEL: splat_v64i1:
+; LMULMAX1-RV64:       # %bb.0:
+; LMULMAX1-RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmv.v.x v25, a1
+; LMULMAX1-RV64-NEXT:    vmsne.vi v26, v25, 0
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 6
+; LMULMAX1-RV64-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
+; LMULMAX1-RV64-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
+; LMULMAX1-RV64-NEXT:    vse1.v v26, (a1)
+; LMULMAX1-RV64-NEXT:    vse1.v v26, (a0)
+; LMULMAX1-RV64-NEXT:    ret
+  %a = insertelement <64 x i1> undef, i1 %y, i32 0
+  %b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer
+  store <64 x i1> %b, <64 x i1>* %x
+  ret void
+}

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i1> undef, i1 -1, i32 0
   %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
   ret <vscale x 1 x i1> %splat
 }
 
+define <vscale x 1 x i1> @vsplat_nxv1i1_2(i1 %x) {
+; CHECK-LABEL: vsplat_nxv1i1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i1> undef, i1 %x, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  ret <vscale x 1 x i1> %splat
+}
+
 define <vscale x 2 x i1> @vsplat_nxv2i1_0() {
 ; CHECK-LABEL: vsplat_nxv2i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i1> undef, i1 0, i32 0
   %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
   ret <vscale x 2 x i1> %splat
 }
 
 define <vscale x 2 x i1> @vsplat_nxv2i1_1() {
 ; CHECK-LABEL: vsplat_nxv2i1_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i1> undef, i1 -1, i32 0
   %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
   ret <vscale x 2 x i1> %splat
 }
 
+define <vscale x 2 x i1> @vsplat_nxv2i1_2(i1 %x) {
+; CHECK-LABEL: vsplat_nxv2i1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i1> undef, i1 %x, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  ret <vscale x 2 x i1> %splat
+}
+
 define <vscale x 4 x i1> @vsplat_nxv4i1_0() {
 ; CHECK-LABEL: vsplat_nxv4i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i1> undef, i1 0, i32 0
   %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   ret <vscale x 4 x i1> %splat
 }
 
 define <vscale x 4 x i1> @vsplat_nxv4i1_1() {
 ; CHECK-LABEL: vsplat_nxv4i1_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i1> undef, i1 -1, i32 0
   %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   ret <vscale x 4 x i1> %splat
 }
 
+define <vscale x 4 x i1> @vsplat_nxv4i1_2(i1 %x) {
+; CHECK-LABEL: vsplat_nxv4i1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i1> undef, i1 %x, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  ret <vscale x 4 x i1> %splat
+}
+
 define <vscale x 8 x i1> @vsplat_nxv8i1_0() {
 ; CHECK-LABEL: vsplat_nxv8i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i1> undef, i1 0, i32 0
   %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   ret <vscale x 8 x i1> %splat
 }
 
 define <vscale x 8 x i1> @vsplat_nxv8i1_1() {
 ; CHECK-LABEL: vsplat_nxv8i1_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i1> undef, i1 -1, i32 0
   %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   ret <vscale x 8 x i1> %splat
 }
 
+define <vscale x 8 x i1> @vsplat_nxv8i1_2(i1 %x) {
+; CHECK-LABEL: vsplat_nxv8i1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i1> undef, i1 %x, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i1> %splat
+}
+
 define <vscale x 16 x i1> @vsplat_nxv16i1_0() {
 ; CHECK-LABEL: vsplat_nxv16i1_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i1> undef, i1 0, i32 0
   %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
   ret <vscale x 16 x i1> %splat
 }
 
 define <vscale x 16 x i1> @vsplat_nxv16i1_1() {
 ; CHECK-LABEL: vsplat_nxv16i1_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i1> undef, i1 -1, i32 0
   %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
   ret <vscale x 16 x i1> %splat
 }
+
+define <vscale x 16 x i1> @vsplat_nxv16i1_2(i1 %x) {
+; CHECK-LABEL: vsplat_nxv16i1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i1> undef, i1 %x, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  ret <vscale x 16 x i1> %splat
+}