[RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.

[craig.topper]

Summary

This adds a special operand type that is allowed to be either
an immediate or register. By giving it a unique operand type the
machine verifier will ignore it.

This perturbs a lot of tests but mostly it is just slightly different
instruction orders. Something bad did happen to some min/max reduction
tests. We're spilling vector registers when we weren't before.

[khchen]

Select the immediate during isel does make sense to me, but unfortunately there are some cases have a slower result.
Do you know is there any cases which have better instruction order and reduce register spilling when apply the new scheme?
I'm just afraid of the new one would be always generate the slower instruction order.

[craig.topper]

Rebase after switching SEW=64 splats on RV32 to use stack slot

[craig.topper]

In D101246#2717226, @khchen wrote:

Select the immediate during isel does make sense to me, but unfortunately there are some cases have a slower result.
Do you know is there any cases which have better instruction order and reduce register spilling when apply the new scheme?
I'm just afraid of the new one would be always generate the slower instruction order.

I think the extra spilling cases are gone now. Those were LMUL=8 cases on RV32 where we used 2 vector register groups to splat a 64 bit element. This left 2 register groups to use for other things. It looks like we're also using a vlmax splat when we have a fixed length vector which causes an extra vsetvli that acts as a scheduling barrier. Some of this should be improved now because we're using a stack store instead of tying up 2 vector registers. We're at least not spilling anymore.

[khchen]

Thanks for clarification, LGTM.

[frasercrmck]

LGTM!

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

121

Should we comment what this is since it's not as obvious as the IMMs above? Or is it expected that people look to the tablgen Operand definition?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM5,
   OPERAND_UIMM12,
   OPERAND_SIMM12,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
-  OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN
+  OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
+  OPERAND_AVL,
 };
 } // namespace RISCVOp
 
 // Describes the predecessor/successor bits used in the FENCE instruction.
 namespace RISCVFenceField {
 enum FenceField {
   I = 8,
   O = 4,

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const {
   uint64_t VC1 = N->getConstantOperandVal(1);
   uint64_t VC2 = Shl.getConstantOperandVal(1);
 
   // Immediate range should be enforced by uimm5 predicate.
   assert(VC2 < 32 && "Unexpected immediate");
   return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF);
 }
 
-// X0 has special meaning for vsetvl/vsetvli.
-//  rd | rs1 |   AVL value | Effect on vl
-//--------------------------------------------------------------
-// !X0 |  X0 |       VLMAX | Set vl to VLMAX
-//  X0 |  X0 | Value in vl | Keep current vl, just change vtype.
+// Select VL as a 5 bit immediate or a value that will become a register. This
+// allows us to choose betwen VSETIVLI or VSETVLI later.
 bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
-  // If the VL value is a constant 0, manually select it to an ADDI with 0
-  // immediate to prevent the default selection path from matching it to X0.
   auto *C = dyn_cast<ConstantSDNode>(N);
-  if (C && C->isNullValue())
-    VL = SDValue(selectImm(CurDAG, SDLoc(N), 0, Subtarget->getXLenVT()), 0);
+  if (C && isUInt<5>(C->getZExtValue()))
+    VL = CurDAG->getTargetConstant(C->getZExtValue(), SDLoc(N),
+                                   N->getValueType(0));
   else
     VL = N;
 
   return true;
 }
 
 bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
   if (N.getOpcode() != ISD::SPLAT_VECTOR &&

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
   assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
   RISCVVSEW ElementWidth = static_cast<RISCVVSEW>(Log2_32(SEW / 8));
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   auto BuildVSETVLI = [&]() {
     if (VLIndex >= 0) {
       Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-      Register VLReg = MI.getOperand(VLIndex).getReg();
+      const MachineOperand &VLOp = MI.getOperand(VLIndex);
 
-      // VL might be a compile time constant, but isel would have to put it
-      // in a register. See if VL comes from an ADDI X0, imm.
-      if (VLReg.isVirtual()) {
-        MachineInstr *Def = MRI.getVRegDef(VLReg);
-        if (Def && Def->getOpcode() == RISCV::ADDI &&
-            Def->getOperand(1).getReg() == RISCV::X0 &&
-            Def->getOperand(2).isImm()) {
-          uint64_t Imm = Def->getOperand(2).getImm();
-          // VSETIVLI allows a 5-bit zero extended immediate.
-          if (isUInt<5>(Imm))
-            return BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETIVLI))
-                .addReg(DestReg, RegState::Define | RegState::Dead)
-                .addImm(Imm);
-        }
-      }
+      // VL can be a register or an immediate.
+      if (VLOp.isImm())
+            .addImm(VLOp.getImm());
 
+      Register VLReg = MI.getOperand(VLIndex).getReg();
       return BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI))
           .addReg(DestReg, RegState::Define | RegState::Dead)
           .addReg(VLReg);
     }
 
     // With no VL operator in the pseudo, do not modify VL (rd = X0, rs1 = X0).
     return BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI))
         .addReg(RISCV::X0, RegState::Define | RegState::Dead)
static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
   }
 
   // For simplicity we reuse the vtype representation here.
   MIB.addImm(RISCVVType::encodeVTYPE(VLMul, ElementWidth,
                                      /*TailAgnostic*/ TailAgnostic,
                                      /*MaskAgnostic*/ false));
 
   // Remove (now) redundant operands from pseudo
-  if (VLIndex >= 0) {
+  if (VLIndex >= 0 && MI.getOperand(VLIndex).isReg()) {
     MI.getOperand(VLIndex).setReg(RISCV::NoRegister);
     MI.getOperand(VLIndex).setIsKill(false);
   }
 
   return BB;
 }
 
 MachineBasicBlock *

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 //===----------------------------------------------------------------------===//
 
 def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
                            SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
                                                 SDTCisInt<1>]>>;
 def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
                               SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
 
+// Operand that is allowed to be a register or a 5 bit immediate.
+// This allows us to pick between VSETIVLI and VSETVLI opcodes using the same
+// pseudo instructions.
+def AVL : RegisterOperand<GPR> {
+  let OperandNamespace = "RISCVOp";
+  let OperandType = "OPERAND_AVL";
+}
+
 // X0 has special meaning for vsetvl/vsetvli.
 //  rd | rs1 |   AVL value | Effect on vl
 //--------------------------------------------------------------
 // !X0 |  X0 |       VLMAX | Set vl to VLMAX
 //  X0 |  X0 | Value in vl | Keep current vl, just change vtype.
 def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
 
 def DecImm : SDNodeXForm<imm, [{
string ret = !if(!eq(octuple, 1), "MF8",
                    !if(!eq(octuple, 4), "MF2",
                    !if(!eq(octuple, 8), "M1",
                    !if(!eq(octuple, 16), "M2",
                    !if(!eq(octuple, 32), "M4",
                    !if(!eq(octuple, 64), "M8",
                    "NoDef")))))));
 }
 
-def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT GPR:$vl)))>;
+def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
 
 // Output pattern for X0 used to represent VLMAX in the pseudo instructions.
 def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
 
 // List of EEW.
 defvar EEWList = [8, 16, 32, 64];
 
 class SegRegClass<LMULInfo m, int nf> {

 class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
       Pseudo<outs, ins, []>, RISCVVPseudo {
   let BaseInstr = instr;
   let VLMul = m.value;
 }
 
 class VPseudoUSLoadNoMask<VReg RetClass, bits<7> EEW, bit isFF> :
       Pseudo<(outs RetClass:$rd),
-             (ins GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSLoadMask<VReg RetClass, bits<7> EEW, bit isFF> :
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1,
-                   VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSLoadNoMask<VReg RetClass, bits<7> EEW>:
       Pseudo<(outs RetClass:$rd),
-             (ins GPR:$rs1, GPR:$rs2, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSLoadMask<VReg RetClass, bits<7> EEW>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1, GPR:$rs2,
-                   VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                          bit Ordered, bit EarlyClobber>:
       Pseudo<(outs RetClass:$rd),
-             (ins GPR:$rs1, IdxClass:$rs2, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins GPR:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLX</*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoILoadMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                        bit Ordered, bit EarlyClobber>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1, IdxClass:$rs2,
-                   VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                   VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLX</*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSStoreNoMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
-              (ins StClass:$rd, GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
+              (ins StClass:$rd, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/0, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSStoreMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
-              (ins StClass:$rd, GPR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+              (ins StClass:$rd, GPR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/1, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSStoreNoMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
-              (ins StClass:$rd, GPR:$rs1, GPR:$rs2, GPR:$vl, ixlenimm:$sew),[]>,
+              (ins StClass:$rd, GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/0, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSStoreMask<VReg StClass, bits<7> EEW>:
       Pseudo<(outs),
-              (ins StClass:$rd, GPR:$rs1, GPR:$rs2, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+              (ins StClass:$rd, GPR:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSE</*Masked*/1, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Unary instruction that is never masked so HasDummyMask=0.
 class VPseudoUnaryNoDummyMask<VReg RetClass,
                               DAGOperand Op2Class> :
         Pseudo<(outs RetClass:$rd),
-               (ins Op2Class:$rs1, GPR:$vl, ixlenimm:$sew), []>,
+               (ins Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoNullaryNoMask<VReg RegClass>:
       Pseudo<(outs RegClass:$rd),
-             (ins GPR:$vl, ixlenimm:$sew),
+             (ins AVL:$vl, ixlenimm:$sew),
              []>, RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoNullaryMask<VReg RegClass>:
       Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
-             (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, GPR:$vl,
+             (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
               ixlenimm:$sew), []>, RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints ="$rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Nullary for pseudo instructions. They are expanded in
 // RISCVExpandPseudoInsts pass.
 class VPseudoNullaryPseudoM<string BaseInst>
-       : Pseudo<(outs VR:$rd), (ins GPR:$vl, ixlenimm:$sew), []>,
+       : Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>,
        RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   // BaseInstr is not used in RISCVExpandPseudoInsts pass.
   // Just fill a corresponding real v-inst to pass tablegen check.
   let BaseInstr = !cast<Instruction>(BaseInst);
 }
 
 // RetClass could be GPR or VReg.
 class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
         Pseudo<(outs RetClass:$rd),
-               (ins OpClass:$rs2, GPR:$vl, ixlenimm:$sew), []>,
+               (ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Constraint;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
                (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
-                    VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // mask unary operation without maskedoff
 class VPseudoMaskUnarySOutMask:
         Pseudo<(outs GPR:$rd),
-               (ins VR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+               (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Mask can be V0~V31
 class VPseudoUnaryAnyMask<VReg RetClass,
                           VReg Op1Class> :
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$merge,
                   Op1Class:$rs2,
-                  VR:$vm, GPR:$vl, ixlenimm:$sew),
+                  VR:$vm, AVL:$vl, ixlenimm:$sew),
              []>,
       RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = "@earlyclobber $rd, $rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoBinaryNoMask<VReg RetClass,
                           VReg Op1Class,
                           DAGOperand Op2Class,
                           string Constraint> :
         Pseudo<(outs RetClass:$rd),
-               (ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew), []>,
+               (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Constraint;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                           bit Ordered>:
       Pseudo<(outs),
-              (ins StClass:$rd, GPR:$rs1, IdxClass:$rs2, GPR:$vl, ixlenimm:$sew),[]>,
+              (ins StClass:$rd, GPR:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSX</*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoIStoreMask<VReg StClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                         bit Ordered>:
       Pseudo<(outs),
-              (ins StClass:$rd, GPR:$rs1, IdxClass:$rs2, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+              (ins StClass:$rd, GPR:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSX</*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoBinaryMask<VReg RetClass,
                         RegisterClass Op1Class,
                         DAGOperand Op2Class,
                         string Constraint> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
                 (ins GetVRegNoV0<RetClass>.R:$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
-                     VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+                     VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Like VPseudoBinaryMask, but output can be V0.
 class VPseudoBinaryMOutMask<VReg RetClass,
                             RegisterClass Op1Class,
                             DAGOperand Op2Class,
                             string Constraint> :
         Pseudo<(outs RetClass:$rd),
                 (ins RetClass:$merge,
                      Op1Class:$rs2, Op2Class:$rs1,
-                     VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+                     VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoBinaryCarryIn<VReg RetClass,
                            VReg Op1Class,
                            DAGOperand Op2Class,
                            LMULInfo MInfo,
                            bit CarryIn,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
                !if(CarryIn,
-                  (ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, GPR:$vl,
+                  (ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, AVL:$vl,
                        ixlenimm:$sew),
-                  (ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew)), []>,
+                  (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew)), []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Constraint;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 0;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
   let VLMul = MInfo.value;
 }
 
 class VPseudoTernaryNoMask<VReg RetClass,
                            RegisterClass Op1Class,
                            DAGOperand Op2Class,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
                (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
-                    GPR:$vl, ixlenimm:$sew),
+                    AVL:$vl, ixlenimm:$sew),
                []>,
         RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoAMOWDNoMask<VReg RetClass,
                          VReg Op1Class> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
                (ins GPR:$rs1,
                     Op1Class:$vs2,
                     GetVRegNoV0<RetClass>.R:$vd,
-                    GPR:$vl, ixlenimm:$sew), []>,
+                    AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 1;
   let mayStore = 1;
   let hasSideEffects = 1;
   let usesCustomInserter = 1;
   let Constraints = "$vd_wd = $vd";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoAMOWDMask<VReg RetClass,
                        VReg Op1Class> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
                (ins GPR:$rs1,
                     Op1Class:$vs2,
                     GetVRegNoV0<RetClass>.R:$vd,
-                    VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+                    VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
         RISCVVPseudo {
   let mayLoad = 1;
   let mayStore = 1;
   let hasSideEffects = 1;
   let usesCustomInserter = 1;
   let Constraints = "$vd_wd = $vd";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;

 
 multiclass VPseudoAMO {
   foreach eew = EEWList in
     defm "EI" # eew : VPseudoAMOEI<eew>;
 }
 
 class VPseudoUSSegLoadNoMask<VReg RetClass, bits<7> EEW, bits<4> NF, bit isFF>:
       Pseudo<(outs RetClass:$rd),
-             (ins GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSSegLoadMask<VReg RetClass, bits<7> EEW, bits<4> NF, bit isFF>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
              (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
-                  VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                  VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/isFF, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegLoadNoMask<VReg RetClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs RetClass:$rd),
-             (ins GPR:$rs1, GPR:$offset, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins GPR:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegLoadMask<VReg RetClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
              (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
-                  GPR:$offset, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                  GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, EEW, VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Constraints = "$rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                             bits<4> NF, bit Ordered>:
       Pseudo<(outs RetClass:$rd),
-             (ins GPR:$rs1, IdxClass:$offset, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins GPR:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLXSEG<NF, /*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                           bits<4> NF, bit Ordered>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
              (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
-                  IdxClass:$offset, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                  IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLXSEG<NF, /*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   // For vector indexed segment loads, the destination vector register groups
   // cannot overlap the source vector register group
   let Constraints = "@earlyclobber $rd, $rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSSegStoreNoMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
-             (ins ValClass:$rd, GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins ValClass:$rd, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSSegStoreMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1,
-                  VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                  VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegStoreNoMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
-             (ins ValClass:$rd, GPR:$rs1, GPR: $offset, GPR:$vl, ixlenimm:$sew),[]>,
+             (ins ValClass:$rd, GPR:$rs1, GPR: $offset, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoSSegStoreMask<VReg ValClass, bits<7> EEW, bits<4> NF>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, GPR: $offset,
-                  VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                  VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                              bits<4> NF, bit Ordered>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, IdxClass: $index,
-                  GPR:$vl, ixlenimm:$sew),[]>,
+                  AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSXSEG<NF, /*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
                            bits<4> NF, bit Ordered>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, IdxClass: $index,
-                  VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+                  VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVSXSEG<NF, /*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
let VLMul = m.value in {
       let HasSEWOp = 1, BaseInstr = VMV_X_S in
       def PseudoVMV_X_S # "_" # m.MX: Pseudo<(outs GPR:$rd),
                                              (ins m.vrclass:$rs2, ixlenimm:$sew),
                                              []>, RISCVVPseudo;
       let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
           ForceTailAgnostic = true, Constraints = "$rd = $rs1" in
       def PseudoVMV_S_X # "_" # m.MX: Pseudo<(outs m.vrclass:$rd),
                                              (ins m.vrclass:$rs1, GPR:$rs2,
-                                                  GPR:$vl, ixlenimm:$sew),
+                                                  AVL:$vl, ixlenimm:$sew),
                                              []>, RISCVVPseudo;
     }
   }
 }
 } // Predicates = [HasStdExtV]
 
 //===----------------------------------------------------------------------===//
 // 17.2. Floating-Point Scalar Move Instructions
foreach f = FPList.fpinfo in {
                                                  (ins m.vrclass:$rs2,
                                                       ixlenimm:$sew),
                                                  []>, RISCVVPseudo;
         let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
             ForceTailAgnostic = true, Constraints = "$rd = $rs1" in
         def "PseudoVFMV_S_" # f.FX # "_" # m.MX :
                                           Pseudo<(outs m.vrclass:$rd),
                                                  (ins m.vrclass:$rs1, f.fprclass:$rs2,
-                                                      GPR:$vl, ixlenimm:$sew),
+                                                      AVL:$vl, ixlenimm:$sew),
                                                  []>, RISCVVPseudo;
       }
     }
   }
 }
 } // Predicates = [HasStdExtV, HasStdExtF]
 
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

 ; LMULMAX2-RV32-NEXT:    addi a6, zero, 56
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
 ; LMULMAX2-RV32-NEXT:    addi a2, zero, 40
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v27, v25, a2
 ; LMULMAX2-RV32-NEXT:    lui a3, 16
 ; LMULMAX2-RV32-NEXT:    addi a3, a3, -256
 ; LMULMAX2-RV32-NEXT:    vand.vx v27, v27, a3
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v27, v26
-; LMULMAX2-RV32-NEXT:    addi a4, zero, 5
-; LMULMAX2-RV32-NEXT:    vsetivli a5, 1, e8,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a4
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 4, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v27, 0
-; LMULMAX2-RV32-NEXT:    lui a4, 1044480
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v27, v27, a4, v0
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 2, e64,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vi v28, v25, 8
-; LMULMAX2-RV32-NEXT:    vand.vv v27, v28, v27
-; LMULMAX2-RV32-NEXT:    vsrl.vi v28, v25, 24
+; LMULMAX2-RV32-NEXT:    vsrl.vi v27, v25, 24
 ; LMULMAX2-RV32-NEXT:    lui a4, 4080
-; LMULMAX2-RV32-NEXT:    vand.vx v28, v28, a4
-; LMULMAX2-RV32-NEXT:    vor.vv v27, v27, v28
-; LMULMAX2-RV32-NEXT:    vor.vv v26, v27, v26
-; LMULMAX2-RV32-NEXT:    addi a5, zero, 255
+; LMULMAX2-RV32-NEXT:    vand.vx v27, v27, a4
+; LMULMAX2-RV32-NEXT:    addi a5, zero, 5
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v27, a5
+; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 0
+; LMULMAX2-RV32-NEXT:    lui a1, 1044480
+; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vi v29, v25, 8
+; LMULMAX2-RV32-NEXT:    vand.vv v28, v29, v28
+; LMULMAX2-RV32-NEXT:    vor.vv v27, v28, v27
+; LMULMAX2-RV32-NEXT:    vor.vv v26, v27, v26
+; LMULMAX2-RV32-NEXT:    addi a1, zero, 255
+; LMULMAX2-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.v.x v27, a1
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v27, v27, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsll.vi v28, v25, 8
 ; LMULMAX2-RV32-NEXT:    vand.vv v27, v28, v27
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a3
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsll.vi v29, v25, 24
 ; LMULMAX2-RV32-NEXT:    vand.vv v28, v29, v28
 ; LMULMAX2-RV32-NEXT:    vor.vv v27, v28, v27
+; LMULMAX2-RV32-NEXT:    vsll.vx v28, v25, a2
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a4
-; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
+; LMULMAX2-RV32-NEXT:    vmv.v.x v29, a4
+; LMULMAX2-RV32-NEXT:    vmerge.vim v29, v29, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vsll.vx v29, v25, a2
-; LMULMAX2-RV32-NEXT:    vand.vv v28, v29, v28
+; LMULMAX2-RV32-NEXT:    vand.vv v28, v28, v29
 ; LMULMAX2-RV32-NEXT:    vsll.vx v25, v25, a6
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v28
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -241
 ; LMULMAX2-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v26, a1

 ; LMULMAX1-RV32-NEXT:    addi a6, zero, 56
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
 ; LMULMAX1-RV32-NEXT:    addi a2, zero, 40
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v25, a2
 ; LMULMAX1-RV32-NEXT:    lui a3, 16
 ; LMULMAX1-RV32-NEXT:    addi a3, a3, -256
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, a3
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT:    addi a4, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a5, 1, e8,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a4
-; LMULMAX1-RV32-NEXT:    vsetivli a4, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.i v27, 0
-; LMULMAX1-RV32-NEXT:    lui a4, 1044480
-; LMULMAX1-RV32-NEXT:    vmerge.vxm v27, v27, a4, v0
-; LMULMAX1-RV32-NEXT:    vsetivli a4, 2, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vi v28, v25, 8
-; LMULMAX1-RV32-NEXT:    vand.vv v27, v28, v27
-; LMULMAX1-RV32-NEXT:    vsrl.vi v28, v25, 24
+; LMULMAX1-RV32-NEXT:    vsrl.vi v27, v25, 24
 ; LMULMAX1-RV32-NEXT:    lui a4, 4080
-; LMULMAX1-RV32-NEXT:    vand.vx v28, v28, a4
-; LMULMAX1-RV32-NEXT:    vor.vv v27, v27, v28
-; LMULMAX1-RV32-NEXT:    vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT:    addi a5, zero, 255
+; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, a4
+; LMULMAX1-RV32-NEXT:    addi a5, zero, 5
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.x v27, a5
+; LMULMAX1-RV32-NEXT:    vmv.v.i v28, 0
+; LMULMAX1-RV32-NEXT:    lui a1, 1044480
+; LMULMAX1-RV32-NEXT:    vmerge.vxm v28, v28, a1, v0
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vi v29, v25, 8
+; LMULMAX1-RV32-NEXT:    vand.vv v28, v29, v28
+; LMULMAX1-RV32-NEXT:    vor.vv v27, v28, v27
+; LMULMAX1-RV32-NEXT:    vor.vv v26, v27, v26
+; LMULMAX1-RV32-NEXT:    addi a1, zero, 255
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vmv.v.x v27, a1
 ; LMULMAX1-RV32-NEXT:    vmerge.vim v27, v27, 0, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsll.vi v28, v25, 8
 ; LMULMAX1-RV32-NEXT:    vand.vv v27, v28, v27
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v28, a3
 ; LMULMAX1-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsll.vi v29, v25, 24
 ; LMULMAX1-RV32-NEXT:    vand.vv v28, v29, v28
 ; LMULMAX1-RV32-NEXT:    vor.vv v27, v28, v27
+; LMULMAX1-RV32-NEXT:    vsll.vx v28, v25, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.x v28, a4
-; LMULMAX1-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
+; LMULMAX1-RV32-NEXT:    vmv.v.x v29, a4
+; LMULMAX1-RV32-NEXT:    vmerge.vim v29, v29, 0, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsll.vx v29, v25, a2
-; LMULMAX1-RV32-NEXT:    vand.vv v28, v29, v28
+; LMULMAX1-RV32-NEXT:    vand.vv v28, v28, v29
 ; LMULMAX1-RV32-NEXT:    vsll.vx v25, v25, a6
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v28
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 61681
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -241
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v26, a1

 ; LMULMAX2-RV32-NEXT:    addi a6, zero, 56
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
 ; LMULMAX2-RV32-NEXT:    addi a2, zero, 40
 ; LMULMAX2-RV32-NEXT:    vsrl.vx v30, v26, a2
 ; LMULMAX2-RV32-NEXT:    lui a3, 16
 ; LMULMAX2-RV32-NEXT:    addi a3, a3, -256
 ; LMULMAX2-RV32-NEXT:    vand.vx v30, v30, a3
 ; LMULMAX2-RV32-NEXT:    vor.vv v28, v30, v28
-; LMULMAX2-RV32-NEXT:    addi a4, zero, 85
-; LMULMAX2-RV32-NEXT:    vsetivli a5, 1, e8,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a4
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
-; LMULMAX2-RV32-NEXT:    lui a4, 1044480
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v30, v30, a4, v0
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 4, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vi v8, v26, 8
-; LMULMAX2-RV32-NEXT:    vand.vv v30, v8, v30
-; LMULMAX2-RV32-NEXT:    vsrl.vi v8, v26, 24
+; LMULMAX2-RV32-NEXT:    vsrl.vi v30, v26, 24
 ; LMULMAX2-RV32-NEXT:    lui a4, 4080
-; LMULMAX2-RV32-NEXT:    vand.vx v8, v8, a4
-; LMULMAX2-RV32-NEXT:    vor.vv v30, v30, v8
-; LMULMAX2-RV32-NEXT:    vor.vv v28, v30, v28
-; LMULMAX2-RV32-NEXT:    addi a5, zero, 255
+; LMULMAX2-RV32-NEXT:    vand.vx v30, v30, a4
+; LMULMAX2-RV32-NEXT:    addi a5, zero, 85
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v30, a5
+; LMULMAX2-RV32-NEXT:    vmv.v.i v8, 0
+; LMULMAX2-RV32-NEXT:    lui a1, 1044480
+; LMULMAX2-RV32-NEXT:    vmerge.vxm v8, v8, a1, v0
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vi v10, v26, 8
+; LMULMAX2-RV32-NEXT:    vand.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT:    vor.vv v30, v8, v30
+; LMULMAX2-RV32-NEXT:    vor.vv v28, v30, v28
+; LMULMAX2-RV32-NEXT:    addi a1, zero, 255
+; LMULMAX2-RV32-NEXT:    vsetivli a5, 8, e32,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.v.x v30, a1
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v30, v30, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsll.vi v8, v26, 8
 ; LMULMAX2-RV32-NEXT:    vand.vv v30, v8, v30
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v8, a3
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v8, v8, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vsll.vi v10, v26, 24
 ; LMULMAX2-RV32-NEXT:    vand.vv v8, v10, v8
 ; LMULMAX2-RV32-NEXT:    vor.vv v30, v8, v30
+; LMULMAX2-RV32-NEXT:    vsll.vx v8, v26, a2
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v8, a4
-; LMULMAX2-RV32-NEXT:    vmerge.vim v8, v8, 0, v0
+; LMULMAX2-RV32-NEXT:    vmv.v.x v10, a4
+; LMULMAX2-RV32-NEXT:    vmerge.vim v10, v10, 0, v0
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vsll.vx v10, v26, a2
-; LMULMAX2-RV32-NEXT:    vand.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT:    vand.vv v8, v8, v10
 ; LMULMAX2-RV32-NEXT:    vsll.vx v26, v26, a6
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v8
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v30
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -241
 ; LMULMAX2-RV32-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a1

 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: bitreverse_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle64.v v30, (a1)
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
-; LMULMAX1-RV32-NEXT:    addi a6, zero, 56
-; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v30, a6
-; LMULMAX1-RV32-NEXT:    addi a7, zero, 40
-; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v30, a7
+; LMULMAX1-RV32-NEXT:    addi a7, zero, 56
+; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v30, a7
+; LMULMAX1-RV32-NEXT:    addi a3, zero, 40
+; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v30, a3
 ; LMULMAX1-RV32-NEXT:    lui a4, 16
 ; LMULMAX1-RV32-NEXT:    addi a4, a4, -256
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, a4
 ; LMULMAX1-RV32-NEXT:    vor.vv v27, v27, v26
+; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v30, 24
+; LMULMAX1-RV32-NEXT:    lui a6, 4080
+; LMULMAX1-RV32-NEXT:    vand.vx v28, v26, a6
 ; LMULMAX1-RV32-NEXT:    addi a5, zero, 5
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a5
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v26, 0
 ; LMULMAX1-RV32-NEXT:    lui a2, 1044480
 ; LMULMAX1-RV32-NEXT:    vmerge.vxm v26, v26, a2, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vi v28, v30, 8
-; LMULMAX1-RV32-NEXT:    vand.vv v28, v28, v26
-; LMULMAX1-RV32-NEXT:    vsrl.vi v29, v30, 24
-; LMULMAX1-RV32-NEXT:    lui a5, 4080
-; LMULMAX1-RV32-NEXT:    vand.vx v29, v29, a5
-; LMULMAX1-RV32-NEXT:    vor.vv v28, v28, v29
+; LMULMAX1-RV32-NEXT:    vsrl.vi v29, v30, 8
+; LMULMAX1-RV32-NEXT:    vand.vv v29, v29, v26
+; LMULMAX1-RV32-NEXT:    vor.vv v28, v29, v28
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v28, v27
 ; LMULMAX1-RV32-NEXT:    addi a2, zero, 255
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v27, a2
 ; LMULMAX1-RV32-NEXT:    vmerge.vim v27, v27, 0, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsll.vi v28, v30, 8
 ; LMULMAX1-RV32-NEXT:    vand.vv v29, v28, v27
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v28, a4
 ; LMULMAX1-RV32-NEXT:    vmerge.vim v28, v28, 0, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsll.vi v8, v30, 24
 ; LMULMAX1-RV32-NEXT:    vand.vv v8, v8, v28
 ; LMULMAX1-RV32-NEXT:    vor.vv v8, v8, v29
+; LMULMAX1-RV32-NEXT:    vsll.vx v9, v30, a3
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.x v29, a5
+; LMULMAX1-RV32-NEXT:    vmv.v.x v29, a6
 ; LMULMAX1-RV32-NEXT:    vmerge.vim v29, v29, 0, v0
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsll.vx v9, v30, a7
 ; LMULMAX1-RV32-NEXT:    vand.vv v9, v9, v29
-; LMULMAX1-RV32-NEXT:    vsll.vx v30, v30, a6
+; LMULMAX1-RV32-NEXT:    vsll.vx v30, v30, a7
 ; LMULMAX1-RV32-NEXT:    vor.vv v30, v30, v9
 ; LMULMAX1-RV32-NEXT:    vor.vv v30, v30, v8
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v30, v31
 ; LMULMAX1-RV32-NEXT:    lui a2, 61681
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, -241
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v30, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v8, v31, v30
 ; LMULMAX1-RV32-NEXT:    vsll.vi v8, v8, 4
 ; LMULMAX1-RV32-NEXT:    lui a2, 986895
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, 240
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v9, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v31, v31, v9
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v31, v31, 4
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v31, v8
 ; LMULMAX1-RV32-NEXT:    lui a2, 209715
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, 819
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v8, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v10, v31, v8
 ; LMULMAX1-RV32-NEXT:    vsll.vi v10, v10, 2
 ; LMULMAX1-RV32-NEXT:    lui a2, 838861
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, -820
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v11, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v31, v31, v11
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v31, v31, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v31, v10
 ; LMULMAX1-RV32-NEXT:    lui a2, 349525
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, 1365
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v10, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v12, v31, v10
 ; LMULMAX1-RV32-NEXT:    vsll.vi v12, v12, 1
 ; LMULMAX1-RV32-NEXT:    lui a2, 699051
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, -1366
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v13, a2
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v31, v31, v13
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v31, v31, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v31, v12
-; LMULMAX1-RV32-NEXT:    vsrl.vx v12, v25, a6
-; LMULMAX1-RV32-NEXT:    vsrl.vx v14, v25, a7
+; LMULMAX1-RV32-NEXT:    vsrl.vx v12, v25, a7
+; LMULMAX1-RV32-NEXT:    vsrl.vx v14, v25, a3
 ; LMULMAX1-RV32-NEXT:    vand.vx v14, v14, a4
 ; LMULMAX1-RV32-NEXT:    vor.vv v12, v14, v12
-; LMULMAX1-RV32-NEXT:    vsrl.vi v14, v25, 8
-; LMULMAX1-RV32-NEXT:    vand.vv v26, v14, v26
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v14, v25, 24
-; LMULMAX1-RV32-NEXT:    vand.vx v14, v14, a5
+; LMULMAX1-RV32-NEXT:    vand.vx v14, v14, a6
+; LMULMAX1-RV32-NEXT:    vsrl.vi v15, v25, 8
+; LMULMAX1-RV32-NEXT:    vand.vv v26, v15, v26
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v14
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v12
 ; LMULMAX1-RV32-NEXT:    vsll.vi v12, v25, 8
 ; LMULMAX1-RV32-NEXT:    vand.vv v27, v12, v27
 ; LMULMAX1-RV32-NEXT:    vsll.vi v12, v25, 24
 ; LMULMAX1-RV32-NEXT:    vand.vv v28, v12, v28
 ; LMULMAX1-RV32-NEXT:    vor.vv v27, v28, v27
-; LMULMAX1-RV32-NEXT:    vsll.vx v28, v25, a7
+; LMULMAX1-RV32-NEXT:    vsll.vx v28, v25, a3
 ; LMULMAX1-RV32-NEXT:    vand.vv v28, v28, v29
-; LMULMAX1-RV32-NEXT:    vsll.vx v25, v25, a6
+; LMULMAX1-RV32-NEXT:    vsll.vx v25, v25, a7
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v28
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    vand.vv v26, v25, v30
 ; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 4
 ; LMULMAX1-RV32-NEXT:    vand.vv v25, v25, v9
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 4
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

 ; LMULMAX2-RV32-NEXT:    vse64.v v25, (a0)
 ; LMULMAX2-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: bswap_v2i64:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle64.v v25, (a0)
-; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vslidedown.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v26
 ; LMULMAX2-RV64-NEXT:    srli a2, a1, 40
 ; LMULMAX2-RV64-NEXT:    lui a3, 16
 ; LMULMAX2-RV64-NEXT:    addiw a7, a3, -256
 ; LMULMAX2-RV64-NEXT:    and a2, a2, a7
 ; LMULMAX2-RV64-NEXT:    srli a4, a1, 56
-; LMULMAX2-RV64-NEXT:    or a2, a2, a4
+; LMULMAX2-RV64-NEXT:    or t0, a2, a4
 ; LMULMAX2-RV64-NEXT:    srli a4, a1, 24
 ; LMULMAX2-RV64-NEXT:    lui a6, 4080
 ; LMULMAX2-RV64-NEXT:    and a4, a4, a6
 ; LMULMAX2-RV64-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV64-NEXT:    addi a3, zero, 255
-; LMULMAX2-RV64-NEXT:    slli t0, a3, 24
-; LMULMAX2-RV64-NEXT:    and a5, a5, t0
+; LMULMAX2-RV64-NEXT:    slli a2, a3, 24
+; LMULMAX2-RV64-NEXT:    and a5, a5, a2
 ; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    or t1, a4, a2
-; LMULMAX2-RV64-NEXT:    slli a4, a1, 8
-; LMULMAX2-RV64-NEXT:    slli t2, a3, 32
+; LMULMAX2-RV64-NEXT:    or t0, a4, t0
+; LMULMAX2-RV64-NEXT:    slli a5, a1, 8
+; LMULMAX2-RV64-NEXT:    slli t1, a3, 32
+; LMULMAX2-RV64-NEXT:    and a5, a5, t1
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 24
+; LMULMAX2-RV64-NEXT:    slli t2, a3, 40
 ; LMULMAX2-RV64-NEXT:    and a4, a4, t2
-; LMULMAX2-RV64-NEXT:    slli a2, a1, 24
-; LMULMAX2-RV64-NEXT:    slli t3, a3, 40
-; LMULMAX2-RV64-NEXT:    and a2, a2, t3
-; LMULMAX2-RV64-NEXT:    or a2, a2, a4
-; LMULMAX2-RV64-NEXT:    slli a4, a1, 40
+; LMULMAX2-RV64-NEXT:    or a4, a4, a5
+; LMULMAX2-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX2-RV64-NEXT:    slli a3, a3, 48
-; LMULMAX2-RV64-NEXT:    and a4, a4, a3
+; LMULMAX2-RV64-NEXT:    and a5, a5, a3
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 56
+; LMULMAX2-RV64-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a4
-; LMULMAX2-RV64-NEXT:    or a1, a1, a2
-; LMULMAX2-RV64-NEXT:    or t1, a1, t1
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; LMULMAX2-RV64-NEXT:    vslidedown.vi v25, v25, 1
-; LMULMAX2-RV64-NEXT:    vmv.x.s a2, v25
-; LMULMAX2-RV64-NEXT:    srli a4, a2, 40
-; LMULMAX2-RV64-NEXT:    and a4, a4, a7
-; LMULMAX2-RV64-NEXT:    srli a1, a2, 56
-; LMULMAX2-RV64-NEXT:    or a1, a4, a1
-; LMULMAX2-RV64-NEXT:    srli a4, a2, 24
+; LMULMAX2-RV64-NEXT:    or a1, a1, t0
+; LMULMAX2-RV64-NEXT:    vsetivli a4, 2, e64,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vmv.v.x v26, a1
+; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT:    srli a4, a1, 24
 ; LMULMAX2-RV64-NEXT:    and a4, a4, a6
-; LMULMAX2-RV64-NEXT:    srli a5, a2, 8
-; LMULMAX2-RV64-NEXT:    and a5, a5, t0
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    or a1, a4, a1
-; LMULMAX2-RV64-NEXT:    slli a4, a2, 8
-; LMULMAX2-RV64-NEXT:    and a4, a4, t2
-; LMULMAX2-RV64-NEXT:    slli a5, a2, 24
-; LMULMAX2-RV64-NEXT:    and a5, a5, t3
+; LMULMAX2-RV64-NEXT:    srli a5, a1, 8
+; LMULMAX2-RV64-NEXT:    and a2, a5, a2
+; LMULMAX2-RV64-NEXT:    or a2, a2, a4
+; LMULMAX2-RV64-NEXT:    srli a4, a1, 40
+; LMULMAX2-RV64-NEXT:    and a4, a4, a7
+; LMULMAX2-RV64-NEXT:    srli a5, a1, 56
+; LMULMAX2-RV64-NEXT:    or a4, a4, a5
+; LMULMAX2-RV64-NEXT:    or a2, a2, a4
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 8
+; LMULMAX2-RV64-NEXT:    and a4, a4, t1
+; LMULMAX2-RV64-NEXT:    slli a5, a1, 24
+; LMULMAX2-RV64-NEXT:    and a5, a5, t2
 ; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    slli a5, a2, 40
+; LMULMAX2-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX2-RV64-NEXT:    and a3, a5, a3
-; LMULMAX2-RV64-NEXT:    slli a2, a2, 56
-; LMULMAX2-RV64-NEXT:    or a2, a2, a3
-; LMULMAX2-RV64-NEXT:    or a2, a2, a4
-; LMULMAX2-RV64-NEXT:    or a1, a2, a1
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.v.x v25, a1
-; LMULMAX2-RV64-NEXT:    vmv.s.x v25, t1
-; LMULMAX2-RV64-NEXT:    vse64.v v25, (a0)
+; LMULMAX2-RV64-NEXT:    slli a1, a1, 56
+; LMULMAX2-RV64-NEXT:    or a1, a1, a3
+; LMULMAX2-RV64-NEXT:    or a1, a1, a4
+; LMULMAX2-RV64-NEXT:    or a1, a1, a2
+; LMULMAX2-RV64-NEXT:    vmv.s.x v26, a1
+; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: bswap_v2i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)

 ; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: bswap_v2i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vle64.v v25, (a0)
-; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vslidedown.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v26
 ; LMULMAX1-RV64-NEXT:    srli a2, a1, 40
 ; LMULMAX1-RV64-NEXT:    lui a3, 16
 ; LMULMAX1-RV64-NEXT:    addiw a7, a3, -256
 ; LMULMAX1-RV64-NEXT:    and a2, a2, a7
 ; LMULMAX1-RV64-NEXT:    srli a4, a1, 56
-; LMULMAX1-RV64-NEXT:    or a2, a2, a4
+; LMULMAX1-RV64-NEXT:    or t0, a2, a4
 ; LMULMAX1-RV64-NEXT:    srli a4, a1, 24
 ; LMULMAX1-RV64-NEXT:    lui a6, 4080
 ; LMULMAX1-RV64-NEXT:    and a4, a4, a6
 ; LMULMAX1-RV64-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV64-NEXT:    addi a3, zero, 255
-; LMULMAX1-RV64-NEXT:    slli t0, a3, 24
-; LMULMAX1-RV64-NEXT:    and a5, a5, t0
+; LMULMAX1-RV64-NEXT:    slli a2, a3, 24
+; LMULMAX1-RV64-NEXT:    and a5, a5, a2
 ; LMULMAX1-RV64-NEXT:    or a4, a5, a4
-; LMULMAX1-RV64-NEXT:    or t1, a4, a2
-; LMULMAX1-RV64-NEXT:    slli a4, a1, 8
-; LMULMAX1-RV64-NEXT:    slli t2, a3, 32
+; LMULMAX1-RV64-NEXT:    or t0, a4, t0
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 8
+; LMULMAX1-RV64-NEXT:    slli t1, a3, 32
+; LMULMAX1-RV64-NEXT:    and a5, a5, t1
+; LMULMAX1-RV64-NEXT:    slli a4, a1, 24
+; LMULMAX1-RV64-NEXT:    slli t2, a3, 40
 ; LMULMAX1-RV64-NEXT:    and a4, a4, t2
-; LMULMAX1-RV64-NEXT:    slli a2, a1, 24
-; LMULMAX1-RV64-NEXT:    slli t3, a3, 40
-; LMULMAX1-RV64-NEXT:    and a2, a2, t3
-; LMULMAX1-RV64-NEXT:    or a2, a2, a4
-; LMULMAX1-RV64-NEXT:    slli a4, a1, 40
+; LMULMAX1-RV64-NEXT:    or a4, a4, a5
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX1-RV64-NEXT:    slli a3, a3, 48
-; LMULMAX1-RV64-NEXT:    and a4, a4, a3
+; LMULMAX1-RV64-NEXT:    and a5, a5, a3
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 56
+; LMULMAX1-RV64-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV64-NEXT:    or a1, a1, a4
-; LMULMAX1-RV64-NEXT:    or a1, a1, a2
-; LMULMAX1-RV64-NEXT:    or t1, a1, t1
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT:    vmv.x.s a2, v25
-; LMULMAX1-RV64-NEXT:    srli a4, a2, 40
-; LMULMAX1-RV64-NEXT:    and a4, a4, a7
-; LMULMAX1-RV64-NEXT:    srli a1, a2, 56
-; LMULMAX1-RV64-NEXT:    or a1, a4, a1
-; LMULMAX1-RV64-NEXT:    srli a4, a2, 24
+; LMULMAX1-RV64-NEXT:    or a1, a1, t0
+; LMULMAX1-RV64-NEXT:    vsetivli a4, 2, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmv.v.x v26, a1
+; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT:    srli a4, a1, 24
 ; LMULMAX1-RV64-NEXT:    and a4, a4, a6
-; LMULMAX1-RV64-NEXT:    srli a5, a2, 8
-; LMULMAX1-RV64-NEXT:    and a5, a5, t0
-; LMULMAX1-RV64-NEXT:    or a4, a5, a4
-; LMULMAX1-RV64-NEXT:    or a1, a4, a1
-; LMULMAX1-RV64-NEXT:    slli a4, a2, 8
-; LMULMAX1-RV64-NEXT:    and a4, a4, t2
-; LMULMAX1-RV64-NEXT:    slli a5, a2, 24
-; LMULMAX1-RV64-NEXT:    and a5, a5, t3
+; LMULMAX1-RV64-NEXT:    srli a5, a1, 8
+; LMULMAX1-RV64-NEXT:    and a2, a5, a2
+; LMULMAX1-RV64-NEXT:    or a2, a2, a4
+; LMULMAX1-RV64-NEXT:    srli a4, a1, 40
+; LMULMAX1-RV64-NEXT:    and a4, a4, a7
+; LMULMAX1-RV64-NEXT:    srli a5, a1, 56
+; LMULMAX1-RV64-NEXT:    or a4, a4, a5
+; LMULMAX1-RV64-NEXT:    or a2, a2, a4
+; LMULMAX1-RV64-NEXT:    slli a4, a1, 8
+; LMULMAX1-RV64-NEXT:    and a4, a4, t1
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 24
+; LMULMAX1-RV64-NEXT:    and a5, a5, t2
 ; LMULMAX1-RV64-NEXT:    or a4, a5, a4
-; LMULMAX1-RV64-NEXT:    slli a5, a2, 40
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX1-RV64-NEXT:    and a3, a5, a3
-; LMULMAX1-RV64-NEXT:    slli a2, a2, 56
-; LMULMAX1-RV64-NEXT:    or a2, a2, a3
-; LMULMAX1-RV64-NEXT:    or a2, a2, a4
-; LMULMAX1-RV64-NEXT:    or a1, a2, a1
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vmv.v.x v25, a1
-; LMULMAX1-RV64-NEXT:    vmv.s.x v25, t1
-; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    slli a1, a1, 56
+; LMULMAX1-RV64-NEXT:    or a1, a1, a3
+; LMULMAX1-RV64-NEXT:    or a1, a1, a4
+; LMULMAX1-RV64-NEXT:    or a1, a1, a2
+; LMULMAX1-RV64-NEXT:    vmv.s.x v26, a1
+; LMULMAX1-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = load <2 x i64>, <2 x i64>* %y
   %c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
   store <2 x i64> %c, <2 x i64>* %x
   ret void
 }
 declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)

 ; LMULMAX2-RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; LMULMAX2-RV64-NEXT:    .cfi_offset ra, -8
 ; LMULMAX2-RV64-NEXT:    .cfi_offset s0, -16
 ; LMULMAX2-RV64-NEXT:    addi s0, sp, 64
 ; LMULMAX2-RV64-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX2-RV64-NEXT:    andi sp, sp, -32
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle64.v v26, (a0)
-; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v26
-; LMULMAX2-RV64-NEXT:    srli a2, a1, 40
-; LMULMAX2-RV64-NEXT:    lui a3, 16
-; LMULMAX2-RV64-NEXT:    addiw a7, a3, -256
-; LMULMAX2-RV64-NEXT:    and a2, a2, a7
-; LMULMAX2-RV64-NEXT:    srli a3, a1, 56
-; LMULMAX2-RV64-NEXT:    or a2, a2, a3
-; LMULMAX2-RV64-NEXT:    srli a3, a1, 24
+; LMULMAX2-RV64-NEXT:    vmv.x.s a2, v26
+; LMULMAX2-RV64-NEXT:    srli a1, a2, 24
 ; LMULMAX2-RV64-NEXT:    lui a6, 4080
-; LMULMAX2-RV64-NEXT:    and a4, a3, a6
-; LMULMAX2-RV64-NEXT:    srli a5, a1, 8
-; LMULMAX2-RV64-NEXT:    addi a3, zero, 255
-; LMULMAX2-RV64-NEXT:    slli t0, a3, 24
-; LMULMAX2-RV64-NEXT:    and a5, a5, t0
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    or a4, a4, a2
-; LMULMAX2-RV64-NEXT:    slli a2, a1, 8
-; LMULMAX2-RV64-NEXT:    slli t1, a3, 32
-; LMULMAX2-RV64-NEXT:    and a2, a2, t1
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 24
-; LMULMAX2-RV64-NEXT:    slli t2, a3, 40
-; LMULMAX2-RV64-NEXT:    and a5, a5, t2
-; LMULMAX2-RV64-NEXT:    or a5, a5, a2
-; LMULMAX2-RV64-NEXT:    slli a2, a1, 40
-; LMULMAX2-RV64-NEXT:    slli a3, a3, 48
-; LMULMAX2-RV64-NEXT:    and a2, a2, a3
-; LMULMAX2-RV64-NEXT:    slli a1, a1, 56
-; LMULMAX2-RV64-NEXT:    or a1, a1, a2
-; LMULMAX2-RV64-NEXT:    or a1, a1, a5
-; LMULMAX2-RV64-NEXT:    or a1, a1, a4
+; LMULMAX2-RV64-NEXT:    and a1, a1, a6
+; LMULMAX2-RV64-NEXT:    srli a3, a2, 8
+; LMULMAX2-RV64-NEXT:    addi a5, zero, 255
+; LMULMAX2-RV64-NEXT:    slli a7, a5, 24
+; LMULMAX2-RV64-NEXT:    and a3, a3, a7
+; LMULMAX2-RV64-NEXT:    or a3, a3, a1
+; LMULMAX2-RV64-NEXT:    srli a4, a2, 40
+; LMULMAX2-RV64-NEXT:    lui a1, 16
+; LMULMAX2-RV64-NEXT:    addiw t0, a1, -256
+; LMULMAX2-RV64-NEXT:    and a4, a4, t0
+; LMULMAX2-RV64-NEXT:    srli a1, a2, 56
+; LMULMAX2-RV64-NEXT:    or a1, a4, a1
+; LMULMAX2-RV64-NEXT:    or a1, a3, a1
+; LMULMAX2-RV64-NEXT:    slli a4, a2, 8
+; LMULMAX2-RV64-NEXT:    slli t1, a5, 32
+; LMULMAX2-RV64-NEXT:    and a3, a4, t1
+; LMULMAX2-RV64-NEXT:    slli a4, a2, 24
+; LMULMAX2-RV64-NEXT:    slli t2, a5, 40
+; LMULMAX2-RV64-NEXT:    and a4, a4, t2
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    slli a4, a2, 40
+; LMULMAX2-RV64-NEXT:    slli a5, a5, 48
+; LMULMAX2-RV64-NEXT:    and a4, a4, a5
+; LMULMAX2-RV64-NEXT:    slli a2, a2, 56
+; LMULMAX2-RV64-NEXT:    or a2, a2, a4
+; LMULMAX2-RV64-NEXT:    or a2, a2, a3
+; LMULMAX2-RV64-NEXT:    or a1, a2, a1
 ; LMULMAX2-RV64-NEXT:    sd a1, 0(sp)
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vslidedown.vi v28, v26, 3
 ; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v28
 ; LMULMAX2-RV64-NEXT:    srli a2, a1, 40
-; LMULMAX2-RV64-NEXT:    and a2, a2, a7
-; LMULMAX2-RV64-NEXT:    srli a4, a1, 56
-; LMULMAX2-RV64-NEXT:    or a2, a2, a4
-; LMULMAX2-RV64-NEXT:    srli a4, a1, 24
-; LMULMAX2-RV64-NEXT:    and a4, a4, a6
-; LMULMAX2-RV64-NEXT:    srli a5, a1, 8
-; LMULMAX2-RV64-NEXT:    and a5, a5, t0
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    or a2, a4, a2
-; LMULMAX2-RV64-NEXT:    slli a4, a1, 8
-; LMULMAX2-RV64-NEXT:    and a4, a4, t1
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 24
-; LMULMAX2-RV64-NEXT:    and a5, a5, t2
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 40
-; LMULMAX2-RV64-NEXT:    and a5, a5, a3
+; LMULMAX2-RV64-NEXT:    and a2, a2, t0
+; LMULMAX2-RV64-NEXT:    srli a3, a1, 56
+; LMULMAX2-RV64-NEXT:    or a2, a2, a3
+; LMULMAX2-RV64-NEXT:    srli a3, a1, 24
+; LMULMAX2-RV64-NEXT:    and a3, a3, a6
+; LMULMAX2-RV64-NEXT:    srli a4, a1, 8
+; LMULMAX2-RV64-NEXT:    and a4, a4, a7
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    or a2, a3, a2
+; LMULMAX2-RV64-NEXT:    slli a3, a1, 8
+; LMULMAX2-RV64-NEXT:    and a3, a3, t1
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 24
+; LMULMAX2-RV64-NEXT:    and a4, a4, t2
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 40
+; LMULMAX2-RV64-NEXT:    and a4, a4, a5
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 56
-; LMULMAX2-RV64-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a4
+; LMULMAX2-RV64-NEXT:    or a1, a1, a3
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a2
 ; LMULMAX2-RV64-NEXT:    sd a1, 24(sp)
 ; LMULMAX2-RV64-NEXT:    vslidedown.vi v28, v26, 2
 ; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v28
 ; LMULMAX2-RV64-NEXT:    srli a2, a1, 40
-; LMULMAX2-RV64-NEXT:    and a2, a2, a7
-; LMULMAX2-RV64-NEXT:    srli a4, a1, 56
-; LMULMAX2-RV64-NEXT:    or a2, a2, a4
-; LMULMAX2-RV64-NEXT:    srli a4, a1, 24
-; LMULMAX2-RV64-NEXT:    and a4, a4, a6
-; LMULMAX2-RV64-NEXT:    srli a5, a1, 8
-; LMULMAX2-RV64-NEXT:    and a5, a5, t0
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    or a2, a4, a2
-; LMULMAX2-RV64-NEXT:    slli a4, a1, 8
-; LMULMAX2-RV64-NEXT:    and a4, a4, t1
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 24
-; LMULMAX2-RV64-NEXT:    and a5, a5, t2
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 40
-; LMULMAX2-RV64-NEXT:    and a5, a5, a3
+; LMULMAX2-RV64-NEXT:    and a2, a2, t0
+; LMULMAX2-RV64-NEXT:    srli a3, a1, 56
+; LMULMAX2-RV64-NEXT:    or a2, a2, a3
+; LMULMAX2-RV64-NEXT:    srli a3, a1, 24
+; LMULMAX2-RV64-NEXT:    and a3, a3, a6
+; LMULMAX2-RV64-NEXT:    srli a4, a1, 8
+; LMULMAX2-RV64-NEXT:    and a4, a4, a7
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    or a2, a3, a2
+; LMULMAX2-RV64-NEXT:    slli a3, a1, 8
+; LMULMAX2-RV64-NEXT:    and a3, a3, t1
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 24
+; LMULMAX2-RV64-NEXT:    and a4, a4, t2
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 40
+; LMULMAX2-RV64-NEXT:    and a4, a4, a5
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 56
-; LMULMAX2-RV64-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a4
+; LMULMAX2-RV64-NEXT:    or a1, a1, a3
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a2
 ; LMULMAX2-RV64-NEXT:    sd a1, 16(sp)
 ; LMULMAX2-RV64-NEXT:    vslidedown.vi v26, v26, 1
 ; LMULMAX2-RV64-NEXT:    vmv.x.s a1, v26
 ; LMULMAX2-RV64-NEXT:    srli a2, a1, 40
-; LMULMAX2-RV64-NEXT:    and a2, a2, a7
-; LMULMAX2-RV64-NEXT:    srli a4, a1, 56
-; LMULMAX2-RV64-NEXT:    or a2, a2, a4
-; LMULMAX2-RV64-NEXT:    srli a4, a1, 24
-; LMULMAX2-RV64-NEXT:    and a4, a4, a6
-; LMULMAX2-RV64-NEXT:    srli a5, a1, 8
-; LMULMAX2-RV64-NEXT:    and a5, a5, t0
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    or a2, a4, a2
-; LMULMAX2-RV64-NEXT:    slli a4, a1, 8
-; LMULMAX2-RV64-NEXT:    and a4, a4, t1
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 24
-; LMULMAX2-RV64-NEXT:    and a5, a5, t2
-; LMULMAX2-RV64-NEXT:    or a4, a5, a4
-; LMULMAX2-RV64-NEXT:    slli a5, a1, 40
-; LMULMAX2-RV64-NEXT:    and a3, a5, a3
+; LMULMAX2-RV64-NEXT:    and a2, a2, t0
+; LMULMAX2-RV64-NEXT:    srli a3, a1, 56
+; LMULMAX2-RV64-NEXT:    or a2, a2, a3
+; LMULMAX2-RV64-NEXT:    srli a3, a1, 24
+; LMULMAX2-RV64-NEXT:    and a3, a3, a6
+; LMULMAX2-RV64-NEXT:    srli a4, a1, 8
+; LMULMAX2-RV64-NEXT:    and a4, a4, a7
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    or a2, a3, a2
+; LMULMAX2-RV64-NEXT:    slli a3, a1, 8
+; LMULMAX2-RV64-NEXT:    and a3, a3, t1
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 24
+; LMULMAX2-RV64-NEXT:    and a4, a4, t2
+; LMULMAX2-RV64-NEXT:    or a3, a4, a3
+; LMULMAX2-RV64-NEXT:    slli a4, a1, 40
+; LMULMAX2-RV64-NEXT:    and a4, a4, a5
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 56
-; LMULMAX2-RV64-NEXT:    or a1, a1, a3
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a4
+; LMULMAX2-RV64-NEXT:    or a1, a1, a3
 ; LMULMAX2-RV64-NEXT:    or a1, a1, a2
 ; LMULMAX2-RV64-NEXT:    sd a1, 8(sp)
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle64.v v26, (sp)
 ; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    addi sp, s0, -64
 ; LMULMAX2-RV64-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
 ; LMULMAX2-RV64-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload

 ; LMULMAX1-RV32-NEXT:    vse64.v v26, (a6)
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, 32
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: bswap_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    addi a6, a0, 16
-; LMULMAX1-RV64-NEXT:    vle64.v v26, (a6)
+; LMULMAX1-RV64-NEXT:    vle64.v v27, (a6)
 ; LMULMAX1-RV64-NEXT:    vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vslidedown.vi v26, v27, 1
 ; LMULMAX1-RV64-NEXT:    vmv.x.s a2, v26
 ; LMULMAX1-RV64-NEXT:    srli a1, a2, 40
 ; LMULMAX1-RV64-NEXT:    lui a3, 16
 ; LMULMAX1-RV64-NEXT:    addiw t0, a3, -256
 ; LMULMAX1-RV64-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV64-NEXT:    srli a3, a2, 56
 ; LMULMAX1-RV64-NEXT:    or a1, a1, a3
 ; LMULMAX1-RV64-NEXT:    srli a3, a2, 24
 ; LMULMAX1-RV64-NEXT:    lui a7, 4080
 ; LMULMAX1-RV64-NEXT:    and a3, a3, a7
 ; LMULMAX1-RV64-NEXT:    srli a5, a2, 8
 ; LMULMAX1-RV64-NEXT:    addi a4, zero, 255
 ; LMULMAX1-RV64-NEXT:    slli t1, a4, 24
 ; LMULMAX1-RV64-NEXT:    and a5, a5, t1
 ; LMULMAX1-RV64-NEXT:    or a3, a5, a3
-; LMULMAX1-RV64-NEXT:    or a5, a3, a1
+; LMULMAX1-RV64-NEXT:    or a3, a3, a1
 ; LMULMAX1-RV64-NEXT:    slli a1, a2, 8
 ; LMULMAX1-RV64-NEXT:    slli t2, a4, 32
-; LMULMAX1-RV64-NEXT:    and a3, a1, t2
-; LMULMAX1-RV64-NEXT:    slli a1, a2, 24
+; LMULMAX1-RV64-NEXT:    and a1, a1, t2
+; LMULMAX1-RV64-NEXT:    slli a5, a2, 24
 ; LMULMAX1-RV64-NEXT:    slli t3, a4, 40
-; LMULMAX1-RV64-NEXT:    and a1, a1, t3
-; LMULMAX1-RV64-NEXT:    or a1, a1, a3
-; LMULMAX1-RV64-NEXT:    slli a3, a2, 40
+; LMULMAX1-RV64-NEXT:    and a5, a5, t3
+; LMULMAX1-RV64-NEXT:    or a5, a5, a1
+; LMULMAX1-RV64-NEXT:    slli a1, a2, 40
 ; LMULMAX1-RV64-NEXT:    slli a4, a4, 48
-; LMULMAX1-RV64-NEXT:    and a3, a3, a4
+; LMULMAX1-RV64-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV64-NEXT:    slli a2, a2, 56
-; LMULMAX1-RV64-NEXT:    or a2, a2, a3
 ; LMULMAX1-RV64-NEXT:    or a1, a2, a1
-; LMULMAX1-RV64-NEXT:    or t4, a1, a5
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT:    vmv.x.s a2, v26
-; LMULMAX1-RV64-NEXT:    srli a3, a2, 40
-; LMULMAX1-RV64-NEXT:    and a3, a3, t0
-; LMULMAX1-RV64-NEXT:    srli a5, a2, 56
-; LMULMAX1-RV64-NEXT:    or a3, a3, a5
-; LMULMAX1-RV64-NEXT:    srli a5, a2, 24
-; LMULMAX1-RV64-NEXT:    and a5, a5, a7
-; LMULMAX1-RV64-NEXT:    srli a1, a2, 8
-; LMULMAX1-RV64-NEXT:    and a1, a1, t1
 ; LMULMAX1-RV64-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV64-NEXT:    or a1, a1, a3
-; LMULMAX1-RV64-NEXT:    slli a3, a2, 8
+; LMULMAX1-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmv.v.x v26, a1
+; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT:    srli a2, a1, 24
+; LMULMAX1-RV64-NEXT:    and a2, a2, a7
+; LMULMAX1-RV64-NEXT:    srli a3, a1, 8
+; LMULMAX1-RV64-NEXT:    and a3, a3, t1
+; LMULMAX1-RV64-NEXT:    or a2, a3, a2
+; LMULMAX1-RV64-NEXT:    srli a3, a1, 40
+; LMULMAX1-RV64-NEXT:    and a3, a3, t0
+; LMULMAX1-RV64-NEXT:    srli a5, a1, 56
+; LMULMAX1-RV64-NEXT:    or a3, a3, a5
+; LMULMAX1-RV64-NEXT:    or a2, a2, a3
+; LMULMAX1-RV64-NEXT:    slli a3, a1, 8
 ; LMULMAX1-RV64-NEXT:    and a3, a3, t2
-; LMULMAX1-RV64-NEXT:    slli a5, a2, 24
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 24
 ; LMULMAX1-RV64-NEXT:    and a5, a5, t3
 ; LMULMAX1-RV64-NEXT:    or a3, a5, a3
-; LMULMAX1-RV64-NEXT:    slli a5, a2, 40
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX1-RV64-NEXT:    and a5, a5, a4
-; LMULMAX1-RV64-NEXT:    slli a2, a2, 56
-; LMULMAX1-RV64-NEXT:    or a2, a2, a5
-; LMULMAX1-RV64-NEXT:    or a2, a2, a3
-; LMULMAX1-RV64-NEXT:    or a1, a2, a1
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vmv.v.x v26, a1
-; LMULMAX1-RV64-NEXT:    vmv.s.x v26, t4
-; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT:    slli a1, a1, 56
+; LMULMAX1-RV64-NEXT:    or a1, a1, a5
+; LMULMAX1-RV64-NEXT:    or a1, a1, a3
+; LMULMAX1-RV64-NEXT:    or a1, a1, a2
+; LMULMAX1-RV64-NEXT:    vmv.s.x v26, a1
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vslidedown.vi v27, v25, 1
+; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v27
 ; LMULMAX1-RV64-NEXT:    srli a2, a1, 40
 ; LMULMAX1-RV64-NEXT:    and a2, a2, t0
 ; LMULMAX1-RV64-NEXT:    srli a3, a1, 56
 ; LMULMAX1-RV64-NEXT:    or a2, a2, a3
 ; LMULMAX1-RV64-NEXT:    srli a3, a1, 24
 ; LMULMAX1-RV64-NEXT:    and a3, a3, a7
 ; LMULMAX1-RV64-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV64-NEXT:    and a5, a5, t1
 ; LMULMAX1-RV64-NEXT:    or a3, a5, a3
 ; LMULMAX1-RV64-NEXT:    or a2, a3, a2
 ; LMULMAX1-RV64-NEXT:    slli a3, a1, 8
 ; LMULMAX1-RV64-NEXT:    and a3, a3, t2
 ; LMULMAX1-RV64-NEXT:    slli a5, a1, 24
 ; LMULMAX1-RV64-NEXT:    and a5, a5, t3
 ; LMULMAX1-RV64-NEXT:    or a3, a5, a3
 ; LMULMAX1-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX1-RV64-NEXT:    and a5, a5, a4
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 56
 ; LMULMAX1-RV64-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV64-NEXT:    or a1, a1, a3
-; LMULMAX1-RV64-NEXT:    or t4, a1, a2
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT:    vmv.x.s a2, v25
-; LMULMAX1-RV64-NEXT:    srli a3, a2, 40
+; LMULMAX1-RV64-NEXT:    or a1, a1, a2
+; LMULMAX1-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vmv.v.x v27, a1
+; LMULMAX1-RV64-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT:    srli a2, a1, 24
+; LMULMAX1-RV64-NEXT:    and a2, a2, a7
+; LMULMAX1-RV64-NEXT:    srli a3, a1, 8
+; LMULMAX1-RV64-NEXT:    and a3, a3, t1
+; LMULMAX1-RV64-NEXT:    or a2, a3, a2
+; LMULMAX1-RV64-NEXT:    srli a3, a1, 40
 ; LMULMAX1-RV64-NEXT:    and a3, a3, t0
-; LMULMAX1-RV64-NEXT:    srli a5, a2, 56
+; LMULMAX1-RV64-NEXT:    srli a5, a1, 56
 ; LMULMAX1-RV64-NEXT:    or a3, a3, a5
-; LMULMAX1-RV64-NEXT:    srli a5, a2, 24
-; LMULMAX1-RV64-NEXT:    and a5, a5, a7
-; LMULMAX1-RV64-NEXT:    srli a1, a2, 8
-; LMULMAX1-RV64-NEXT:    and a1, a1, t1
-; LMULMAX1-RV64-NEXT:    or a1, a1, a5
-; LMULMAX1-RV64-NEXT:    or a1, a1, a3
-; LMULMAX1-RV64-NEXT:    slli a3, a2, 8
+; LMULMAX1-RV64-NEXT:    or a2, a2, a3
+; LMULMAX1-RV64-NEXT:    slli a3, a1, 8
 ; LMULMAX1-RV64-NEXT:    and a3, a3, t2
-; LMULMAX1-RV64-NEXT:    slli a5, a2, 24
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 24
 ; LMULMAX1-RV64-NEXT:    and a5, a5, t3
 ; LMULMAX1-RV64-NEXT:    or a3, a5, a3
-; LMULMAX1-RV64-NEXT:    slli a5, a2, 40
+; LMULMAX1-RV64-NEXT:    slli a5, a1, 40
 ; LMULMAX1-RV64-NEXT:    and a4, a5, a4
-; LMULMAX1-RV64-NEXT:    slli a2, a2, 56
-; LMULMAX1-RV64-NEXT:    or a2, a2, a4
-; LMULMAX1-RV64-NEXT:    or a2, a2, a3
-; LMULMAX1-RV64-NEXT:    or a1, a2, a1
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vmv.v.x v25, a1
-; LMULMAX1-RV64-NEXT:    vmv.s.x v25, t4
-; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    slli a1, a1, 56
+; LMULMAX1-RV64-NEXT:    or a1, a1, a4
+; LMULMAX1-RV64-NEXT:    or a1, a1, a3
+; LMULMAX1-RV64-NEXT:    or a1, a1, a2
+; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a1
+; LMULMAX1-RV64-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-RV64-NEXT:    vse64.v v26, (a6)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = load <4 x i64>, <4 x i64>* %y
   %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
   store <4 x i64> %c, <4 x i64>* %x
   ret void
 }
 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

 ; LMULMAX1-NEXT:    addi a1, a0, 64
 ; LMULMAX1-NEXT:    vle32.v v29, (a1)
 ; LMULMAX1-NEXT:    addi a1, a0, 80
 ; LMULMAX1-NEXT:    vle32.v v30, (a1)
 ; LMULMAX1-NEXT:    addi a1, a0, 96
 ; LMULMAX1-NEXT:    vle32.v v31, (a1)
 ; LMULMAX1-NEXT:    addi a0, a0, 112
 ; LMULMAX1-NEXT:    vle32.v v24, (a0)
-; LMULMAX1-NEXT:    ld a1, 0(s0)
-; LMULMAX1-NEXT:    addi a0, sp, 240
-; LMULMAX1-NEXT:    vse32.v v15, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 224
-; LMULMAX1-NEXT:    vse32.v v14, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 208
-; LMULMAX1-NEXT:    vse32.v v13, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 192
-; LMULMAX1-NEXT:    vse32.v v12, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 176
-; LMULMAX1-NEXT:    vse32.v v11, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 160
-; LMULMAX1-NEXT:    vse32.v v10, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 144
-; LMULMAX1-NEXT:    vse32.v v9, (a0)
-; LMULMAX1-NEXT:    addi a0, sp, 128
-; LMULMAX1-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-NEXT:    addi a0, zero, 42
-; LMULMAX1-NEXT:    sd a0, 8(sp)
+; LMULMAX1-NEXT:    ld a0, 0(s0)
+; LMULMAX1-NEXT:    addi a1, sp, 240
+; LMULMAX1-NEXT:    vse32.v v15, (a1)
+; LMULMAX1-NEXT:    addi a1, sp, 224
+; LMULMAX1-NEXT:    vse32.v v14, (a1)
+; LMULMAX1-NEXT:    addi a1, sp, 208
+; LMULMAX1-NEXT:    vse32.v v13, (a1)
+; LMULMAX1-NEXT:    addi a1, sp, 192
+; LMULMAX1-NEXT:    vse32.v v12, (a1)
+; LMULMAX1-NEXT:    addi a1, sp, 176
+; LMULMAX1-NEXT:    vse32.v v11, (a1)
+; LMULMAX1-NEXT:    addi a1, sp, 160
+; LMULMAX1-NEXT:    vse32.v v10, (a1)
+; LMULMAX1-NEXT:    addi a1, sp, 144
+; LMULMAX1-NEXT:    vse32.v v9, (a1)
+; LMULMAX1-NEXT:    addi a1, zero, 42
+; LMULMAX1-NEXT:    sd a1, 8(sp)
+; LMULMAX1-NEXT:    sd a0, 0(sp)
 ; LMULMAX1-NEXT:    addi a0, sp, 128
-; LMULMAX1-NEXT:    sd a1, 0(sp)
+; LMULMAX1-NEXT:    addi a1, sp, 128
+; LMULMAX1-NEXT:    vse32.v v8, (a1)
 ; LMULMAX1-NEXT:    vmv1r.v v8, v25
 ; LMULMAX1-NEXT:    vmv1r.v v9, v26
 ; LMULMAX1-NEXT:    vmv1r.v v10, v27
 ; LMULMAX1-NEXT:    vmv1r.v v11, v28
 ; LMULMAX1-NEXT:    vmv1r.v v12, v29
 ; LMULMAX1-NEXT:    vmv1r.v v13, v30
 ; LMULMAX1-NEXT:    vmv1r.v v14, v31
 ; LMULMAX1-NEXT:    vmv1r.v v15, v24

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

 ; LMULMAX2-RV32-LABEL: ctlz_v2i64:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX2-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX2-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v25
+; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX2-RV32-NEXT:    lui a2, 4112
-; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB3_2
+; LMULMAX2-RV32-NEXT:    lui a1, 4112
+; LMULMAX2-RV32-NEXT:    addi a2, a1, 257
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB3_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
-; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX2-RV32-NEXT:    or a1, a5, a1
+; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB3_3
 ; LMULMAX2-RV32-NEXT:  .LBB3_2:
-; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX2-RV32-NEXT:    or a1, a1, a5
+; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX2-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX1-RV32-LABEL: ctlz_v2i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v25
+; LMULMAX1-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 349525
 ; LMULMAX1-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX1-RV32-NEXT:    lui a1, 209715
 ; LMULMAX1-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX1-RV32-NEXT:    lui a1, 61681
 ; LMULMAX1-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX1-RV32-NEXT:    lui a2, 4112
-; LMULMAX1-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX1-RV32-NEXT:    addi a2, a2, 257
-; LMULMAX1-RV32-NEXT:    bnez a1, .LBB3_2
+; LMULMAX1-RV32-NEXT:    lui a1, 4112
+; LMULMAX1-RV32-NEXT:    addi a2, a1, 257
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    bnez a5, .LBB3_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
-; LMULMAX1-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX1-RV32-NEXT:    or a1, a5, a1
+; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    not a1, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB3_3
 ; LMULMAX1-RV32-NEXT:  .LBB3_2:
-; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX1-RV32-NEXT:    or a1, a1, a5
+; LMULMAX1-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX1-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV32-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX2-RV32-NEXT:    andi sp, sp, -32
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    sw zero, 28(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 20(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX2-RV32-NEXT:    lui a2, 4112
-; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
-; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
-; LMULMAX2-RV32-NEXT:    bnez a1, .LBB7_2
+; LMULMAX2-RV32-NEXT:    lui a1, 4112
+; LMULMAX2-RV32-NEXT:    addi a2, a1, 257
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
-; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
-; LMULMAX2-RV32-NEXT:    or a1, a5, a1
+; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
+; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    not a1, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB7_3
 ; LMULMAX2-RV32-NEXT:  .LBB7_2:
-; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
-; LMULMAX2-RV32-NEXT:    or a1, a1, a5
+; LMULMAX2-RV32-NEXT:    srli a1, a5, 1
+; LMULMAX2-RV32-NEXT:    or a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 2
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 8
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 16
 ; LMULMAX2-RV32-NEXT:    or a1, a1, a5

 ; LMULMAX2-RV64-NEXT:    addi sp, sp, 64
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: ctlz_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -32
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 32
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a6, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle64.v v26, (a6)
-; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    sw zero, 28(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 20(sp)
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    addi a7, zero, 32
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v27
 ; LMULMAX1-RV32-NEXT:    lui a2, 349525
 ; LMULMAX1-RV32-NEXT:    addi a5, a2, 1365
 ; LMULMAX1-RV32-NEXT:    lui a2, 209715
 ; LMULMAX1-RV32-NEXT:    addi a4, a2, 819
 ; LMULMAX1-RV32-NEXT:    lui a2, 61681
 ; LMULMAX1-RV32-NEXT:    addi t0, a2, -241
-; LMULMAX1-RV32-NEXT:    lui a3, 4112
-; LMULMAX1-RV32-NEXT:    addi a7, zero, 32
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v27
-; LMULMAX1-RV32-NEXT:    addi a3, a3, 257
-; LMULMAX1-RV32-NEXT:    bnez a2, .LBB7_2
+; LMULMAX1-RV32-NEXT:    lui a2, 4112
+; LMULMAX1-RV32-NEXT:    addi a3, a2, 257
+; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
-; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
-; LMULMAX1-RV32-NEXT:    or a1, a1, a2
+; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
+; LMULMAX1-RV32-NEXT:    or a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    not a1, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB7_3
 ; LMULMAX1-RV32-NEXT:  .LBB7_2:
-; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
-; LMULMAX1-RV32-NEXT:    or a1, a2, a1
+; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2

 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_6:
 ; LMULMAX1-RV32-NEXT:    sw a1, 24(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a7
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
-; LMULMAX1-RV32-NEXT:    bnez a2, .LBB7_8
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_8
 ; LMULMAX1-RV32-NEXT:  # %bb.7:
-; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
-; LMULMAX1-RV32-NEXT:    or a1, a1, a2
+; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
+; LMULMAX1-RV32-NEXT:    or a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    not a1, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB7_9
 ; LMULMAX1-RV32-NEXT:  .LBB7_8:
-; LMULMAX1-RV32-NEXT:    srli a1, a2, 1
-; LMULMAX1-RV32-NEXT:    or a1, a2, a1
+; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
+; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 2
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 8
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 16
 ; LMULMAX1-RV32-NEXT:    or a1, a1, a2

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: cttz_v4i32:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    addi sp, sp, -16
 ; LMULMAX2-RV64-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle32.v v25, (a0)
-; LMULMAX2-RV64-NEXT:    addi a1, zero, 1
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vslidedown.vi v26, v25, 3
 ; LMULMAX2-RV64-NEXT:    vmv.x.s a2, v26
+; LMULMAX2-RV64-NEXT:    addi a1, zero, 1
 ; LMULMAX2-RV64-NEXT:    slli a6, a1, 32
 ; LMULMAX2-RV64-NEXT:    or a2, a2, a6
 ; LMULMAX2-RV64-NEXT:    addi a3, a2, -1
 ; LMULMAX2-RV64-NEXT:    not a2, a2
 ; LMULMAX2-RV64-NEXT:    and a3, a2, a3
 ; LMULMAX2-RV64-NEXT:    srli a4, a3, 1
 ; LMULMAX2-RV64-NEXT:    lui a2, 21845
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 1365

 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: cttz_v4i32:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    addi sp, sp, -16
 ; LMULMAX1-RV64-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT:    addi a1, zero, 1
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 1, e32,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vslidedown.vi v26, v25, 3
 ; LMULMAX1-RV64-NEXT:    vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT:    addi a1, zero, 1
 ; LMULMAX1-RV64-NEXT:    slli a6, a1, 32
 ; LMULMAX1-RV64-NEXT:    or a2, a2, a6
 ; LMULMAX1-RV64-NEXT:    addi a3, a2, -1
 ; LMULMAX1-RV64-NEXT:    not a2, a2
 ; LMULMAX1-RV64-NEXT:    and a3, a2, a3
 ; LMULMAX1-RV64-NEXT:    srli a4, a3, 1
 ; LMULMAX1-RV64-NEXT:    lui a2, 21845
 ; LMULMAX1-RV64-NEXT:    addiw a2, a2, 1365

 ; LMULMAX2-RV32-LABEL: cttz_v2i64:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX2-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX2-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v25
+; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX2-RV32-NEXT:    lui a1, 4112
-; LMULMAX2-RV32-NEXT:    addi a2, a1, 257
-; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX2-RV32-NEXT:    bnez a5, .LBB3_2
+; LMULMAX2-RV32-NEXT:    lui a2, 4112
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
+; LMULMAX2-RV32-NEXT:    bnez a1, .LBB3_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
-; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
-; LMULMAX2-RV32-NEXT:    not a1, a1
-; LMULMAX2-RV32-NEXT:    and a1, a1, a5
+; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
+; LMULMAX2-RV32-NEXT:    not a5, a5
+; LMULMAX2-RV32-NEXT:    and a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB3_3
 ; LMULMAX2-RV32-NEXT:  .LBB3_2:
-; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
-; LMULMAX2-RV32-NEXT:    not a5, a5
-; LMULMAX2-RV32-NEXT:    and a1, a5, a1
+; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
+; LMULMAX2-RV32-NEXT:    not a1, a1
+; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4

 ; LMULMAX1-RV32-LABEL: cttz_v2i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -16
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v25
+; LMULMAX1-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
+; LMULMAX1-RV32-NEXT:    vmv.x.s a5, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 349525
 ; LMULMAX1-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX1-RV32-NEXT:    lui a1, 209715
 ; LMULMAX1-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX1-RV32-NEXT:    lui a1, 61681
 ; LMULMAX1-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX1-RV32-NEXT:    lui a1, 4112
-; LMULMAX1-RV32-NEXT:    addi a2, a1, 257
-; LMULMAX1-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
-; LMULMAX1-RV32-NEXT:    bnez a5, .LBB3_2
+; LMULMAX1-RV32-NEXT:    lui a2, 4112
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT:    addi a2, a2, 257
+; LMULMAX1-RV32-NEXT:    bnez a1, .LBB3_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
-; LMULMAX1-RV32-NEXT:    addi a5, a1, -1
-; LMULMAX1-RV32-NEXT:    not a1, a1
-; LMULMAX1-RV32-NEXT:    and a1, a1, a5
+; LMULMAX1-RV32-NEXT:    addi a1, a5, -1
+; LMULMAX1-RV32-NEXT:    not a5, a5
+; LMULMAX1-RV32-NEXT:    and a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB3_3
 ; LMULMAX1-RV32-NEXT:  .LBB3_2:
-; LMULMAX1-RV32-NEXT:    addi a1, a5, -1
-; LMULMAX1-RV32-NEXT:    not a5, a5
-; LMULMAX1-RV32-NEXT:    and a1, a5, a1
+; LMULMAX1-RV32-NEXT:    addi a5, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX1-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX1-RV32-NEXT:    srli a5, a1, 4

 ; LMULMAX2-RV64-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; LMULMAX2-RV64-NEXT:    .cfi_offset ra, -8
 ; LMULMAX2-RV64-NEXT:    .cfi_offset s0, -16
 ; LMULMAX2-RV64-NEXT:    addi s0, sp, 64
 ; LMULMAX2-RV64-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX2-RV64-NEXT:    andi sp, sp, -32
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle32.v v26, (a0)
-; LMULMAX2-RV64-NEXT:    addi a1, zero, 1
-; LMULMAX2-RV64-NEXT:    vsetivli a2, 1, e32,m2,ta,mu
+; LMULMAX2-RV64-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vslidedown.vi v28, v26, 7
 ; LMULMAX2-RV64-NEXT:    vmv.x.s a2, v28
+; LMULMAX2-RV64-NEXT:    addi a1, zero, 1
 ; LMULMAX2-RV64-NEXT:    slli a6, a1, 32
 ; LMULMAX2-RV64-NEXT:    or a2, a2, a6
 ; LMULMAX2-RV64-NEXT:    addi a3, a2, -1
 ; LMULMAX2-RV64-NEXT:    not a2, a2
 ; LMULMAX2-RV64-NEXT:    and a3, a2, a3
 ; LMULMAX2-RV64-NEXT:    srli a4, a3, 1
 ; LMULMAX2-RV64-NEXT:    lui a2, 21845
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 1365

 ; LMULMAX2-RV32-NEXT:    .cfi_def_cfa s0, 0
 ; LMULMAX2-RV32-NEXT:    andi sp, sp, -32
 ; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    sw zero, 28(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 20(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX2-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
+; LMULMAX2-RV32-NEXT:    vmv.x.s a5, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a4, a1, 1365
 ; LMULMAX2-RV32-NEXT:    lui a1, 209715
 ; LMULMAX2-RV32-NEXT:    addi a3, a1, 819
 ; LMULMAX2-RV32-NEXT:    lui a1, 61681
 ; LMULMAX2-RV32-NEXT:    addi a7, a1, -241
-; LMULMAX2-RV32-NEXT:    lui a1, 4112
-; LMULMAX2-RV32-NEXT:    addi a2, a1, 257
-; LMULMAX2-RV32-NEXT:    addi a6, zero, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v28
-; LMULMAX2-RV32-NEXT:    bnez a5, .LBB7_2
+; LMULMAX2-RV32-NEXT:    lui a2, 4112
+; LMULMAX2-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT:    addi a2, a2, 257
+; LMULMAX2-RV32-NEXT:    bnez a1, .LBB7_2
 ; LMULMAX2-RV32-NEXT:  # %bb.1:
-; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
-; LMULMAX2-RV32-NEXT:    not a1, a1
-; LMULMAX2-RV32-NEXT:    and a1, a1, a5
+; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
+; LMULMAX2-RV32-NEXT:    not a5, a5
+; LMULMAX2-RV32-NEXT:    and a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4
 ; LMULMAX2-RV32-NEXT:    add a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a7
 ; LMULMAX2-RV32-NEXT:    mul a1, a1, a2
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX2-RV32-NEXT:    addi a5, a1, 32
 ; LMULMAX2-RV32-NEXT:    j .LBB7_3
 ; LMULMAX2-RV32-NEXT:  .LBB7_2:
-; LMULMAX2-RV32-NEXT:    addi a1, a5, -1
-; LMULMAX2-RV32-NEXT:    not a5, a5
-; LMULMAX2-RV32-NEXT:    and a1, a5, a1
+; LMULMAX2-RV32-NEXT:    addi a5, a1, -1
+; LMULMAX2-RV32-NEXT:    not a1, a1
+; LMULMAX2-RV32-NEXT:    and a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 1
 ; LMULMAX2-RV32-NEXT:    and a5, a5, a4
 ; LMULMAX2-RV32-NEXT:    sub a1, a1, a5
 ; LMULMAX2-RV32-NEXT:    and a5, a1, a3
 ; LMULMAX2-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX2-RV32-NEXT:    and a1, a1, a3
 ; LMULMAX2-RV32-NEXT:    add a1, a5, a1
 ; LMULMAX2-RV32-NEXT:    srli a5, a1, 4

 ; LMULMAX2-RV64-NEXT:    addi sp, sp, 64
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: cttz_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi sp, sp, -32
 ; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 32
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a6, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle64.v v26, (a6)
-; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    sw zero, 28(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 20(sp)
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT:    addi a7, zero, 32
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v27
 ; LMULMAX1-RV32-NEXT:    lui a2, 349525
 ; LMULMAX1-RV32-NEXT:    addi a5, a2, 1365
 ; LMULMAX1-RV32-NEXT:    lui a2, 209715
 ; LMULMAX1-RV32-NEXT:    addi a4, a2, 819
 ; LMULMAX1-RV32-NEXT:    lui a2, 61681
 ; LMULMAX1-RV32-NEXT:    addi t0, a2, -241
-; LMULMAX1-RV32-NEXT:    lui a2, 4112
-; LMULMAX1-RV32-NEXT:    addi a3, a2, 257
-; LMULMAX1-RV32-NEXT:    addi a7, zero, 32
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vsrl.vx v27, v26, a7
-; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v27
-; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_2
+; LMULMAX1-RV32-NEXT:    lui a3, 4112
+; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT:    addi a3, a3, 257
+; LMULMAX1-RV32-NEXT:    bnez a2, .LBB7_2
 ; LMULMAX1-RV32-NEXT:  # %bb.1:
-; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
-; LMULMAX1-RV32-NEXT:    not a2, a2
-; LMULMAX1-RV32-NEXT:    and a1, a2, a1
+; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
+; LMULMAX1-RV32-NEXT:    not a1, a1
+; LMULMAX1-RV32-NEXT:    and a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4
 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 32
 ; LMULMAX1-RV32-NEXT:    j .LBB7_3
 ; LMULMAX1-RV32-NEXT:  .LBB7_2:
-; LMULMAX1-RV32-NEXT:    addi a2, a1, -1
-; LMULMAX1-RV32-NEXT:    not a1, a1
-; LMULMAX1-RV32-NEXT:    and a1, a1, a2
+; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
+; LMULMAX1-RV32-NEXT:    not a2, a2
+; LMULMAX1-RV32-NEXT:    and a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5
 ; LMULMAX1-RV32-NEXT:    sub a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a2, a1, a4
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, a4
 ; LMULMAX1-RV32-NEXT:    add a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 4

 ; LMULMAX1-RV32-NEXT:    add a1, a1, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a1, t0
 ; LMULMAX1-RV32-NEXT:    mul a1, a1, a3
 ; LMULMAX1-RV32-NEXT:    srli a1, a1, 24
 ; LMULMAX1-RV32-NEXT:  .LBB7_6:
 ; LMULMAX1-RV32-NEXT:    sw a1, 24(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 12(sp)
 ; LMULMAX1-RV32-NEXT:    sw zero, 4(sp)
-; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vsrl.vx v26, v25, a7
+; LMULMAX1-RV32-NEXT:    vmv.x.s a1, v25
 ; LMULMAX1-RV32-NEXT:    vmv.x.s a2, v26
 ; LMULMAX1-RV32-NEXT:    bnez a1, .LBB7_8
 ; LMULMAX1-RV32-NEXT:  # %bb.7:
 ; LMULMAX1-RV32-NEXT:    addi a1, a2, -1
 ; LMULMAX1-RV32-NEXT:    not a2, a2
 ; LMULMAX1-RV32-NEXT:    and a1, a2, a1
 ; LMULMAX1-RV32-NEXT:    srli a2, a1, 1
 ; LMULMAX1-RV32-NEXT:    and a2, a2, a5

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

; CHECK-NEXT:    ret
   ret <4 x i32> %z
 }
 
 define <4 x i64> @sextload_v4i8_v4i64(<4 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v4i8_v4i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v9, v25
+; LMULMAX1-NEXT:    vsext.vf8 v9, v26
+; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v4i8_v4i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i8>, <4 x i8>* %x
   %z = sext <4 x i8> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define <4 x i64> @zextload_v4i8_v4i64(<4 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v4i8_v4i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v9, v25
+; LMULMAX1-NEXT:    vzext.vf8 v9, v26
+; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v4i8_v4i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf8 v8, v25
; CHECK-NEXT:    ret
   ret <8 x i16> %z
 }
 
 define <8 x i32> @sextload_v8i8_v8i32(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v25
+; LMULMAX1-NEXT:    vsext.vf4 v9, v26
+; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i8_v8i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = sext <8 x i8> %y to <8 x i32>
   ret <8 x i32> %z
 }
 
 define <8 x i32> @zextload_v8i8_v8i32(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v25
+; LMULMAX1-NEXT:    vzext.vf4 v9, v26
+; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i8_v8i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = zext <8 x i8> %y to <8 x i32>
   ret <8 x i32> %z
 }
 
 define <8 x i64> @sextload_v8i8_v8i64(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i8_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v10, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v11, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v9, v25
+; LMULMAX1-NEXT:    vsext.vf8 v9, v26
+; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i8_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = sext <8 x i8> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define <8 x i64> @zextload_v8i8_v8i64(<8 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i8_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v10, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v11, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v9, v25
+; LMULMAX1-NEXT:    vzext.vf8 v9, v26
+; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i8_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i8>, <8 x i8>* %x
   %z = zext <8 x i8> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define <16 x i16> @sextload_v16i8_v16i16(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v16i8_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 8
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v9, v25
+; LMULMAX1-NEXT:    vsext.vf2 v9, v26
+; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i8_v16i16:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = sext <16 x i8> %y to <16 x i16>
   ret <16 x i16> %z
 }
 
 define <16 x i16> @zextload_v16i8_v16i16(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i8_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 8
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v9, v25
+; LMULMAX1-NEXT:    vzext.vf2 v9, v26
+; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i8_v16i16:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = zext <16 x i8> %y to <16 x i16>
   ret <16 x i16> %z
 }
 
 define <16 x i32> @sextload_v16i8_v16i32(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v16i8_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v10, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v11, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v25
+; LMULMAX1-NEXT:    vsext.vf4 v9, v26
+; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i8_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = sext <16 x i8> %y to <16 x i32>
   ret <16 x i32> %z
 }
 
 define <16 x i32> @zextload_v16i8_v16i32(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i8_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v11, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v25
+; LMULMAX1-NEXT:    vzext.vf4 v9, v26
+; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i8_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = zext <16 x i8> %y to <16 x i32>
   ret <16 x i32> %z
 }
 
 define <16 x i64> @sextload_v16i8_v16i64(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: sextload_v16i8_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v12, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v14, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v15, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf8 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v10, v25
+; LMULMAX1-NEXT:    vsext.vf8 v10, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v11, v25
+; LMULMAX1-NEXT:    vsext.vf8 v11, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf8 v13, v25
+; LMULMAX1-NEXT:    vsext.vf8 v13, v26
+; LMULMAX1-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i8_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
-; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX4-NEXT:    vslidedown.vi v25, v25, 8
+; LMULMAX4-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vsext.vf8 v12, v25
+; LMULMAX4-NEXT:    vsext.vf8 v12, v26
+; LMULMAX4-NEXT:    vsext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = sext <16 x i8> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define <16 x i64> @zextload_v16i8_v16i64(<16 x i8>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i8_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v12, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v14, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v15, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf8 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v10, v25
+; LMULMAX1-NEXT:    vzext.vf8 v10, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v11, v25
+; LMULMAX1-NEXT:    vzext.vf8 v11, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf8 v13, v25
+; LMULMAX1-NEXT:    vzext.vf8 v13, v26
+; LMULMAX1-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i8_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX4-NEXT:    vle8.v v25, (a0)
-; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX4-NEXT:    vslidedown.vi v25, v25, 8
+; LMULMAX4-NEXT:    vslidedown.vi v26, v25, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vzext.vf8 v12, v25
+; LMULMAX4-NEXT:    vzext.vf8 v12, v26
+; LMULMAX4-NEXT:    vzext.vf8 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i8>, <16 x i8>* %x
   %z = zext <16 x i8> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) {
 ; CHECK-LABEL: truncstore_v2i8_v2i1:
; CHECK-NEXT:    ret
   ret <4 x i32> %z
 }
 
 define <4 x i64> @sextload_v4i16_v4i64(<4 x i16>* %x) {
 ; LMULMAX1-LABEL: sextload_v4i16_v4i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v25
+; LMULMAX1-NEXT:    vsext.vf4 v9, v26
+; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v4i16_v4i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i16>, <4 x i16>* %x
   %z = sext <4 x i16> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define <4 x i64> @zextload_v4i16_v4i64(<4 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v4i16_v4i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v25
+; LMULMAX1-NEXT:    vzext.vf4 v9, v26
+; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v4i16_v4i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25
; CHECK-NEXT:    ret
   ret void
 }
 
 define <8 x i32> @sextload_v8i16_v8i32(<8 x i16>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i16_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v9, v25
+; LMULMAX1-NEXT:    vsext.vf2 v9, v26
+; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i16_v8i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i16>, <8 x i16>* %x
   %z = sext <8 x i16> %y to <8 x i32>
   ret <8 x i32> %z
 }
 
 define <8 x i32> @zextload_v8i16_v8i32(<8 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i16_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v9, v25
+; LMULMAX1-NEXT:    vzext.vf2 v9, v26
+; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i16_v8i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i16>, <8 x i16>* %x
   %z = zext <8 x i16> %y to <8 x i32>
   ret <8 x i32> %z
 }
 
 define <8 x i64> @sextload_v8i16_v8i64(<8 x i16>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i16_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v10, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v11, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v25
+; LMULMAX1-NEXT:    vsext.vf4 v9, v26
+; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i16_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i16>, <8 x i16>* %x
   %z = sext <8 x i16> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define <8 x i64> @zextload_v8i16_v8i64(<8 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i16_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v11, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v25
+; LMULMAX1-NEXT:    vzext.vf4 v9, v26
+; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i16_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf4 v8, v25

 
 define <16 x i32> @sextload_v16i16_v16i32(<16 x i16>* %x) {
 ; LMULMAX1-LABEL: sextload_v16i16_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v9, v25
-; LMULMAX1-NEXT:    vsext.vf2 v10, v26
+; LMULMAX1-NEXT:    vsext.vf2 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v11, v25
+; LMULMAX1-NEXT:    vsext.vf2 v11, v27
+; LMULMAX1-NEXT:    vsext.vf2 v8, v25
+; LMULMAX1-NEXT:    vsext.vf2 v10, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i16_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v26, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf2 v8, v26
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i16>, <16 x i16>* %x
   %z = sext <16 x i16> %y to <16 x i32>
   ret <16 x i32> %z
 }
 
 define <16 x i32> @zextload_v16i16_v16i32(<16 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i16_v16i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v9, v25
-; LMULMAX1-NEXT:    vzext.vf2 v10, v26
+; LMULMAX1-NEXT:    vzext.vf2 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v11, v25
+; LMULMAX1-NEXT:    vzext.vf2 v11, v27
+; LMULMAX1-NEXT:    vzext.vf2 v8, v25
+; LMULMAX1-NEXT:    vzext.vf2 v10, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i16_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v26, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf2 v8, v26
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i16>, <16 x i16>* %x
   %z = zext <16 x i16> %y to <16 x i32>
   ret <16 x i32> %z
 }
 
 define <16 x i64> @sextload_v16i16_v16i64(<16 x i16>* %x) {
 ; LMULMAX1-LABEL: sextload_v16i16_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v10, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v11, v27
-; LMULMAX1-NEXT:    vsext.vf4 v12, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v14, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v15, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v25
+; LMULMAX1-NEXT:    vsext.vf4 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v13, v25
+; LMULMAX1-NEXT:    vsext.vf4 v13, v27
+; LMULMAX1-NEXT:    vsext.vf4 v8, v25
+; LMULMAX1-NEXT:    vsext.vf4 v12, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i16_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v26, (a0)
-; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vsext.vf4 v8, v26
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e16,m2,ta,mu
-; LMULMAX4-NEXT:    vslidedown.vi v26, v26, 8
+; LMULMAX4-NEXT:    vslidedown.vi v28, v26, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vsext.vf4 v12, v26
+; LMULMAX4-NEXT:    vsext.vf4 v12, v28
+; LMULMAX4-NEXT:    vsext.vf4 v8, v26
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i16>, <16 x i16>* %x
   %z = sext <16 x i16> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define <16 x i64> @zextload_v16i16_v16i64(<16 x i16>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i16_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle16.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v11, v27
-; LMULMAX1-NEXT:    vzext.vf4 v12, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v14, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v15, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v9, v25
+; LMULMAX1-NEXT:    vzext.vf4 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v13, v25
+; LMULMAX1-NEXT:    vzext.vf4 v13, v27
+; LMULMAX1-NEXT:    vzext.vf4 v8, v25
+; LMULMAX1-NEXT:    vzext.vf4 v12, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i16_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vle16.v v26, (a0)
-; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vzext.vf4 v8, v26
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e16,m2,ta,mu
-; LMULMAX4-NEXT:    vslidedown.vi v26, v26, 8
+; LMULMAX4-NEXT:    vslidedown.vi v28, v26, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vzext.vf4 v12, v26
+; LMULMAX4-NEXT:    vzext.vf4 v12, v28
+; LMULMAX4-NEXT:    vzext.vf4 v8, v26
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i16>, <16 x i16>* %x
   %z = zext <16 x i16> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define void @truncstore_v2i32_v2i8(<2 x i32> %x, <2 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v2i32_v2i8:
; CHECK-NEXT:    ret
   ret void
 }
 
 define <4 x i64> @sextload_v4i32_v4i64(<4 x i32>* %x) {
 ; LMULMAX1-LABEL: sextload_v4i32_v4i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v9, v25
+; LMULMAX1-NEXT:    vsext.vf2 v9, v26
+; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v4i32_v4i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX4-NEXT:    ret
   %y = load <4 x i32>, <4 x i32>* %x
   %z = sext <4 x i32> %y to <4 x i64>
   ret <4 x i64> %z
 }
 
 define <4 x i64> @zextload_v4i32_v4i64(<4 x i32>* %x) {
 ; LMULMAX1-LABEL: zextload_v4i32_v4i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v9, v25
+; LMULMAX1-NEXT:    vzext.vf2 v9, v26
+; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v4i32_v4i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v25, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf2 v8, v25

 
 define <8 x i64> @sextload_v8i32_v8i64(<8 x i32>* %x) {
 ; LMULMAX1-LABEL: sextload_v8i32_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v9, v25
-; LMULMAX1-NEXT:    vsext.vf2 v10, v26
+; LMULMAX1-NEXT:    vsext.vf2 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v11, v25
+; LMULMAX1-NEXT:    vsext.vf2 v11, v27
+; LMULMAX1-NEXT:    vsext.vf2 v8, v25
+; LMULMAX1-NEXT:    vsext.vf2 v10, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v8i32_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v26, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vsext.vf2 v8, v26
 ; LMULMAX4-NEXT:    ret
   %y = load <8 x i32>, <8 x i32>* %x
   %z = sext <8 x i32> %y to <8 x i64>
   ret <8 x i64> %z
 }
 
 define <8 x i64> @zextload_v8i32_v8i64(<8 x i32>* %x) {
 ; LMULMAX1-LABEL: zextload_v8i32_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v8, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v9, v25
-; LMULMAX1-NEXT:    vzext.vf2 v10, v26
+; LMULMAX1-NEXT:    vzext.vf2 v9, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v11, v25
+; LMULMAX1-NEXT:    vzext.vf2 v11, v27
+; LMULMAX1-NEXT:    vzext.vf2 v8, v25
+; LMULMAX1-NEXT:    vzext.vf2 v10, v26
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v8i32_v8i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v26, (a0)
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; LMULMAX4-NEXT:    vzext.vf2 v8, v26

 ; LMULMAX1-NEXT:    addi a1, a0, 48
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a1, a0, 32
 ; LMULMAX1-NEXT:    vle32.v v26, (a1)
 ; LMULMAX1-NEXT:    vle32.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v28, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v8, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v9, v27
-; LMULMAX1-NEXT:    vsext.vf2 v10, v28
+; LMULMAX1-NEXT:    vsext.vf2 v9, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v28, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v28, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v11, v27
-; LMULMAX1-NEXT:    vsext.vf2 v12, v26
+; LMULMAX1-NEXT:    vsext.vf2 v11, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v13, v26
-; LMULMAX1-NEXT:    vsext.vf2 v14, v25
+; LMULMAX1-NEXT:    vsext.vf2 v13, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf2 v15, v25
+; LMULMAX1-NEXT:    vsext.vf2 v15, v29
+; LMULMAX1-NEXT:    vsext.vf2 v8, v27
+; LMULMAX1-NEXT:    vsext.vf2 v10, v28
+; LMULMAX1-NEXT:    vsext.vf2 v12, v26
+; LMULMAX1-NEXT:    vsext.vf2 v14, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: sextload_v16i32_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v28, (a0)
-; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vsext.vf2 v8, v28
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m4,ta,mu
-; LMULMAX4-NEXT:    vslidedown.vi v28, v28, 8
+; LMULMAX4-NEXT:    vslidedown.vi v8, v28, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vsext.vf2 v12, v28
+; LMULMAX4-NEXT:    vsext.vf2 v12, v8
+; LMULMAX4-NEXT:    vsext.vf2 v8, v28
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i32>, <16 x i32>* %x
   %z = sext <16 x i32> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define <16 x i64> @zextload_v16i32_v16i64(<16 x i32>* %x) {
 ; LMULMAX1-LABEL: zextload_v16i32_v16i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    addi a1, a0, 48
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vle32.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a1, a0, 32
 ; LMULMAX1-NEXT:    vle32.v v26, (a1)
 ; LMULMAX1-NEXT:    vle32.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v28, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v8, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v9, v27
-; LMULMAX1-NEXT:    vzext.vf2 v10, v28
+; LMULMAX1-NEXT:    vzext.vf2 v9, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v27, v28, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v28, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v11, v27
-; LMULMAX1-NEXT:    vzext.vf2 v12, v26
+; LMULMAX1-NEXT:    vzext.vf2 v11, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v13, v26
-; LMULMAX1-NEXT:    vzext.vf2 v14, v25
+; LMULMAX1-NEXT:    vzext.vf2 v13, v29
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v29, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf2 v15, v25
+; LMULMAX1-NEXT:    vzext.vf2 v15, v29
+; LMULMAX1-NEXT:    vzext.vf2 v8, v27
+; LMULMAX1-NEXT:    vzext.vf2 v10, v28
+; LMULMAX1-NEXT:    vzext.vf2 v12, v26
+; LMULMAX1-NEXT:    vzext.vf2 v14, v25
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: zextload_v16i32_v16i64:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vle32.v v28, (a0)
-; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vzext.vf2 v8, v28
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e32,m4,ta,mu
-; LMULMAX4-NEXT:    vslidedown.vi v28, v28, 8
+; LMULMAX4-NEXT:    vslidedown.vi v8, v28, 8
 ; LMULMAX4-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; LMULMAX4-NEXT:    vzext.vf2 v12, v28
+; LMULMAX4-NEXT:    vzext.vf2 v12, v8
+; LMULMAX4-NEXT:    vzext.vf2 v8, v28
 ; LMULMAX4-NEXT:    ret
   %y = load <16 x i32>, <16 x i32>* %x
   %z = zext <16 x i32> %y to <16 x i64>
   ret <16 x i64> %z
 }
 
 define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %z) {
 ; CHECK-LABEL: truncstore_v2i64_v2i8:

 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vse16.v v28, (a1)
 ; LMULMAX1-NEXT:    vse16.v v29, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v16i64_v16i16:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX4-NEXT:    vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT:    vnsrl.wi v26, v12, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX4-NEXT:    vnsrl.wi v28, v26, 0
+; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
+; LMULMAX4-NEXT:    vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
+; LMULMAX4-NEXT:    vnsrl.wi v30, v26, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vmv.v.i v26, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m2,tu,mu
-; LMULMAX4-NEXT:    vslideup.vi v26, v28, 0
-; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX4-NEXT:    vnsrl.wi v28, v12, 0
-; LMULMAX4-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
-; LMULMAX4-NEXT:    vnsrl.wi v30, v28, 0
+; LMULMAX4-NEXT:    vslideup.vi v26, v30, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,tu,mu
-; LMULMAX4-NEXT:    vslideup.vi v26, v30, 8
+; LMULMAX4-NEXT:    vslideup.vi v26, v28, 8
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; LMULMAX4-NEXT:    vse16.v v26, (a0)
 ; LMULMAX4-NEXT:    ret
   %y = trunc <16 x i64> %x to <16 x i16>
   store <16 x i16> %y, <16 x i16>* %z
   ret void
 }
 

 ; LMULMAX1-NEXT:    addi a1, a0, 16
 ; LMULMAX1-NEXT:    vse32.v v28, (a1)
 ; LMULMAX1-NEXT:    vse32.v v27, (a0)
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX4-LABEL: truncstore_v16i64_v16i32:
 ; LMULMAX4:       # %bb.0:
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX4-NEXT:    vnsrl.wi v28, v8, 0
+; LMULMAX4-NEXT:    vnsrl.wi v28, v12, 0
+; LMULMAX4-NEXT:    vnsrl.wi v12, v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vmv.v.i v8, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m4,tu,mu
-; LMULMAX4-NEXT:    vslideup.vi v8, v28, 0
-; LMULMAX4-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX4-NEXT:    vnsrl.wi v28, v12, 0
+; LMULMAX4-NEXT:    vslideup.vi v8, v12, 0
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e32,m4,tu,mu
 ; LMULMAX4-NEXT:    vslideup.vi v8, v28, 8
 ; LMULMAX4-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
 ; LMULMAX4-NEXT:    vse32.v v8, (a0)
 ; LMULMAX4-NEXT:    ret
   %y = trunc <16 x i64> %x to <16 x i32>
   store <16 x i32> %y, <16 x i32>* %z
   ret void

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

; RV64-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @extractelt_v2i64(<2 x i64>* %x) nounwind {
 ; RV32-LABEL: extractelt_v2i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

 ; LMULMAX8-NEXT:    vsetivli a0, 8, e32,m2,ta,mu
 ; LMULMAX8-NEXT:    vse32.v v26, (a1)
 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: fpext_v8f16_v8f32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v26, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v25
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v26
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v26, v25
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vse32.v v27, (a0)
 ; LMULMAX1-NEXT:    vse32.v v26, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %d = fpext <8 x half> %a to <8 x float>
   store <8 x float> %d, <8 x float>* %y

 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
 ; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v26
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
 ; LMULMAX1-NEXT:    vfwcvt.f.f.v v26, v27
-; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v25
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v25
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v29, v27
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v29, v28
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v27
+; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v28
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,mf4,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v27, v25
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v28, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.f.f.v v25, v27
+; LMULMAX1-NEXT:    vfwcvt.f.f.v v25, v28
 ; LMULMAX1-NEXT:    addi a0, a1, 48
 ; LMULMAX1-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vse64.v v29, (a0)
-; LMULMAX1-NEXT:    vse64.v v28, (a1)
+; LMULMAX1-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x half>, <8 x half>* %x
   %d = fpext <8 x half> %a to <8 x double>
   store <8 x double> %d, <8 x double>* %y
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

 }
 
 define void @fcmp_ord_fv_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
 ; CHECK-LABEL: fcmp_ord_fv_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 4, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vmfeq.vv v27, v25, v25
-; CHECK-NEXT:    vmfeq.vf v25, v26, fa0
+; CHECK-NEXT:    vmfeq.vf v27, v26, fa0
+; CHECK-NEXT:    vmfeq.vv v26, v25, v25
 ; CHECK-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; CHECK-NEXT:    vmand.mm v0, v25, v27
+; CHECK-NEXT:    vmand.mm v0, v27, v26
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e8,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0
 ; CHECK-NEXT:    vse1.v v25, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, <4 x half>* %x
   %b = insertelement <4 x half> undef, half %y, i32 0
   %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
   %d = fcmp ord <4 x half> %c, %a
   store <4 x i1> %d, <4 x i1>* %z
   ret void
 }
 
 define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
 ; CHECK-LABEL: fcmp_uno_fv_v4f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 2, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v25, (a0)
 ; CHECK-NEXT:    vfmv.v.f v26, fa0
-; CHECK-NEXT:    vmfne.vv v27, v25, v25
-; CHECK-NEXT:    vmfne.vf v25, v26, fa0
+; CHECK-NEXT:    vmfne.vf v27, v26, fa0
+; CHECK-NEXT:    vmfne.vv v26, v25, v25
 ; CHECK-NEXT:    vsetivli a0, 2, e8,m1,ta,mu
-; CHECK-NEXT:    vmor.mm v0, v25, v27
+; CHECK-NEXT:    vmor.mm v0, v27, v26
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 2, e8,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 0
 ; CHECK-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
 ; CHECK-NEXT:    vmsne.vi v25, v26, 0

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> undef, <4 x double> %x, <4 x i32> <i32 5, i32 6, i32 4, i32 5>
   ret <4 x double> %s
 }
 
 define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y) {
 ; RV32-LABEL: vrgather_shuffle_vv_v4f64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a0, zero, 1
-; RV32-NEXT:    addi a1, zero, 8
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a1
-; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vmv.v.i v28, 0
-; RV32-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
-; RV32-NEXT:    vslideup.vi v28, v25, 3
 ; RV32-NEXT:    lui a0, %hi(.LCPI6_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI6_0)
 ; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v8, v25
+; RV32-NEXT:    addi a0, zero, 8
+; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vmv.s.x v0, a0
+; RV32-NEXT:    addi a0, zero, 1
+; RV32-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
+; RV32-NEXT:    vmv.s.x v25, a0
+; RV32-NEXT:    vmv.v.i v28, 0
+; RV32-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
+; RV32-NEXT:    vslideup.vi v28, v25, 3
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v26, v10, v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vv_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.s.x v26, a0
 ; RV64-NEXT:    vmv.v.i v28, 0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV64-NEXT:    vslideup.vi v28, v26, 3
-; RV64-NEXT:    addi a0, zero, 8
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    lui a0, %hi(.LCPI6_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI6_0)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v30, (a0)
 ; RV64-NEXT:    vrgather.vv v26, v8, v30
+; RV64-NEXT:    addi a0, zero, 8
+; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,tu,mu
 ; RV64-NEXT:    vrgather.vv v26, v10, v28, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
   ret <4 x double> %s
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_zero_16f16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse16.v v25, (a1)
+; LMULMAX1-NEXT:    vse16.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <16 x half> undef, half 0.0, i32 0
   %b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer
   store <16 x half> %b, <16 x half>* %x
   ret void
 }
 
 define void @splat_zero_v8f32(<8 x float>* %x) {
 ; LMULMAX2-LABEL: splat_zero_v8f32:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_zero_v8f32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse32.v v25, (a1)
+; LMULMAX1-NEXT:    vse32.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <8 x float> undef, float 0.0, i32 0
   %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
   store <8 x float> %b, <8 x float>* %x
   ret void
 }
 
 define void @splat_zero_v4f64(<4 x double>* %x) {
 ; LMULMAX2-LABEL: splat_zero_v4f64:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_zero_v4f64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse64.v v25, (a1)
+; LMULMAX1-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <4 x double> undef, double 0.0, i32 0
   %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer
   store <4 x double> %b, <4 x double>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: fp2si_v8f32_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a2, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v25, (a2)
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v27, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v28, v25
-; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v25, v26
+; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v28, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v29, v26
+; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v29, v27
+; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v27, v25
+; LMULMAX1-NEXT:    vfwcvt.rtz.x.f.v v25, v26
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vse64.v v29, (a0)
 ; LMULMAX1-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 48
 ; LMULMAX1-NEXT:    vse64.v v28, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vse64.v v27, (a0)

 ; LMULMAX8-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: fp2ui_v8f32_v8i64:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a2, a0, 16
 ; LMULMAX1-NEXT:    vle32.v v25, (a2)
 ; LMULMAX1-NEXT:    vle32.v v26, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v27, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v28, v25
-; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v25, v26
+; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v28, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e32,mf2,ta,mu
-; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v29, v26
+; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v29, v27
+; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v27, v25
+; LMULMAX1-NEXT:    vfwcvt.rtz.xu.f.v v25, v26
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vse64.v v29, (a0)
 ; LMULMAX1-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 48
 ; LMULMAX1-NEXT:    vse64.v v28, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vse64.v v27, (a0)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v27, v26
 ; LMULMAX1-NEXT:    vfcvt.f.x.v v26, v27
-; LMULMAX1-NEXT:    vsext.vf4 v27, v25
-; LMULMAX1-NEXT:    vfcvt.f.x.v v27, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v28, v25
+; LMULMAX1-NEXT:    vsext.vf4 v28, v27
 ; LMULMAX1-NEXT:    vfcvt.f.x.v v28, v28
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsext.vf4 v29, v27
+; LMULMAX1-NEXT:    vfcvt.f.x.v v27, v29
 ; LMULMAX1-NEXT:    vsext.vf4 v29, v25
 ; LMULMAX1-NEXT:    vfcvt.f.x.v v25, v29
 ; LMULMAX1-NEXT:    addi a0, a1, 48
-; LMULMAX1-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vse64.v v28, (a0)
-; LMULMAX1-NEXT:    vse64.v v27, (a1)
+; LMULMAX1-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i16>, <8 x i16>* %x
   %d = sitofp <8 x i16> %a to <8 x double>
   store <8 x double> %d, <8 x double>* %y
   ret void
 }

 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vle16.v v25, (a0)
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vzext.vf4 v27, v26
 ; LMULMAX1-NEXT:    vfcvt.f.xu.v v26, v27
-; LMULMAX1-NEXT:    vzext.vf4 v27, v25
-; LMULMAX1-NEXT:    vfcvt.f.xu.v v27, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
-; LMULMAX1-NEXT:    vzext.vf4 v28, v25
+; LMULMAX1-NEXT:    vzext.vf4 v28, v27
 ; LMULMAX1-NEXT:    vfcvt.f.xu.v v28, v28
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e16,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
 ; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vzext.vf4 v29, v27
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v27, v29
 ; LMULMAX1-NEXT:    vzext.vf4 v29, v25
 ; LMULMAX1-NEXT:    vfcvt.f.xu.v v25, v29
 ; LMULMAX1-NEXT:    addi a0, a1, 48
-; LMULMAX1-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-NEXT:    vse64.v v27, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vse64.v v28, (a0)
-; LMULMAX1-NEXT:    vse64.v v27, (a1)
+; LMULMAX1-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i16>, <8 x i16>* %x
   %d = uitofp <8 x i16> %a to <8 x double>
   store <8 x double> %d, <8 x double>* %y
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

 ; RV32-LABEL: insertelt_v3i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.v.i v28, 0
 ; RV32-NEXT:    vsetivli a3, 2, e64,m2,tu,mu
 ; RV32-NEXT:    vslideup.vi v28, v26, 0
-; RV32-NEXT:    addi a3, a0, 20
-; RV32-NEXT:    vsetivli a4, 4, e32,m1,ta,mu
-; RV32-NEXT:    vlse32.v v26, (a3), zero
 ; RV32-NEXT:    lw a3, 16(a0)
+; RV32-NEXT:    addi a4, a0, 20
+; RV32-NEXT:    vsetivli a5, 4, e32,m1,ta,mu
+; RV32-NEXT:    vlse32.v v26, (a4), zero
 ; RV32-NEXT:    vmv.s.x v26, a3
 ; RV32-NEXT:    vsetivli a3, 4, e64,m2,tu,mu
 ; RV32-NEXT:    vslideup.vi v28, v26, 2
 ; RV32-NEXT:    vsetivli a3, 2, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vslide1up.vx v30, v26, a2
 ; RV32-NEXT:    vslide1up.vx v26, v30, a1
 ; RV32-NEXT:    vsetivli a3, 3, e64,m2,tu,mu
 ; RV32-NEXT:    vslideup.vi v28, v26, 2
-; RV32-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
-; RV32-NEXT:    vse64.v v28, (a0)
 ; RV32-NEXT:    sw a1, 16(a0)
 ; RV32-NEXT:    sw a2, 20(a0)
+; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; RV32-NEXT:    vse64.v v28, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v3i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    sd a1, 16(a0)
 ; RV64-NEXT:    ret
   %a = load <3 x i64>, <3 x i64>* %x, align 8
   %b = insertelement <3 x i64> %a, i64 %y, i32 2

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

 ; RV64-NEXT:    ret
   store <16 x i8> <i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1, i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* %x
   ret void
 }
 
 define void @buildvec_seq_v9i8(<9 x i8>* %x) {
 ; RV32-LABEL: buildvec_seq_v9i8:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    addi a1, zero, 3
+; RV32-NEXT:    sb a1, 8(a0)
 ; RV32-NEXT:    addi a1, zero, 73
 ; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v25, 2
 ; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
 ; RV32-NEXT:    addi a1, zero, 36
 ; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; RV32-NEXT:    vmerge.vim v25, v25, 3, v0
 ; RV32-NEXT:    vse8.v v25, (a0)
-; RV32-NEXT:    addi a1, zero, 3
-; RV32-NEXT:    sb a1, 8(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: buildvec_seq_v9i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 3
 ; RV64-NEXT:    sb a1, 8(a0)
 ; RV64-NEXT:    lui a1, 4104
 ; RV64-NEXT:    addiw a1, a1, 385

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

 ; LMULMAX2-NEXT:    vsext.vf4 v26, v25
 ; LMULMAX2-NEXT:    vse32.v v26, (a1)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: sext_v8i8_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a2, 8, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vle8.v v25, (a0)
-; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v26, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v26, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v27, v25
+; LMULMAX1-NEXT:    vsext.vf4 v27, v26
+; LMULMAX1-NEXT:    vsext.vf4 v26, v25
 ; LMULMAX1-NEXT:    addi a0, a1, 16
 ; LMULMAX1-NEXT:    vse32.v v27, (a0)
 ; LMULMAX1-NEXT:    vse32.v v26, (a1)
 ; LMULMAX1-NEXT:    ret
   %a = load <8 x i8>, <8 x i8>* %x
   %b = sext <8 x i8> %a to <8 x i32>
   store <8 x i32> %b, <8 x i32>* %z
   ret void

 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v28, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vsext.vf4 v29, v27
-; LMULMAX1-NEXT:    vsext.vf4 v27, v25
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 8
+; LMULMAX1-NEXT:    vslidedown.vi v27, v25, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v30, v25
+; LMULMAX1-NEXT:    vsext.vf4 v30, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v31, v25
-; LMULMAX1-NEXT:    vsext.vf4 v25, v26
+; LMULMAX1-NEXT:    vsext.vf4 v31, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 8, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 8
+; LMULMAX1-NEXT:    vslidedown.vi v27, v26, 8
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v8, v26
+; LMULMAX1-NEXT:    vsext.vf4 v8, v27
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e8,m1,ta,mu
-; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
 ; LMULMAX1-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; LMULMAX1-NEXT:    vsext.vf4 v9, v26
+; LMULMAX1-NEXT:    vsext.vf4 v9, v27
+; LMULMAX1-NEXT:    vsext.vf4 v27, v25
+; LMULMAX1-NEXT:    vsext.vf4 v25, v26
 ; LMULMAX1-NEXT:    addi a0, a1, 48
 ; LMULMAX1-NEXT:    vse32.v v9, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 32
 ; LMULMAX1-NEXT:    vse32.v v8, (a0)
 ; LMULMAX1-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-NEXT:    addi a0, a1, 112
 ; LMULMAX1-NEXT:    vse32.v v31, (a0)
 ; LMULMAX1-NEXT:    addi a0, a1, 96

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

 ; CHECK-LABEL: vrgather_shuffle_vv_v4i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.s.x v25, a0
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
 ; CHECK-NEXT:    vslideup.vi v26, v25, 3
-; CHECK-NEXT:    addi a0, zero, 8
-; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    lui a0, %hi(.LCPI6_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI6_0)
 ; CHECK-NEXT:    vsetivli a1, 4, e16,m1,ta,mu
 ; CHECK-NEXT:    vle16.v v27, (a0)
 ; CHECK-NEXT:    vrgather.vv v25, v8, v27
+; CHECK-NEXT:    addi a0, zero, 8
+; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli a0, 4, e16,m1,tu,mu
 ; CHECK-NEXT:    vrgather.vv v25, v9, v26, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    ret
   %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
   ret <4 x i16> %s
 }
 

 ; RV32-NEXT:    addi a0, zero, 36
 ; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    vsetivli a0, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v26, 0
 ; RV32-NEXT:    vmerge.vim v26, v26, 2, v0
 ; RV32-NEXT:    vsetivli a0, 8, e16,m1,tu,mu
 ; RV32-NEXT:    vslideup.vi v26, v25, 7
-; RV32-NEXT:    addi a0, zero, 164
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI11_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v8, v25
+; RV32-NEXT:    addi a0, zero, 164
+; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v12, v26, v0.t
 ; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vv_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 5
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vmv.s.x v28, a0
 ; RV64-NEXT:    addi a0, zero, 36
 ; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vmv.v.i v16, 0
 ; RV64-NEXT:    vmerge.vim v16, v16, 2, v0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV64-NEXT:    vslideup.vi v16, v28, 7
-; RV64-NEXT:    addi a0, zero, 164
-; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV64-NEXT:    addi a0, a0, %lo(.LCPI11_0)
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v20, (a0)
 ; RV64-NEXT:    vrgather.vv v28, v8, v20
+; RV64-NEXT:    addi a0, zero, 164
+; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV64-NEXT:    vrgather.vv v28, v12, v16, v0.t
 ; RV64-NEXT:    vmv4r.v v8, v28
 ; RV64-NEXT:    ret
   %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
   ret <8 x i64> %s
 }
 
 define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
 ; RV32-LABEL: vrgather_shuffle_xv_v8i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 6
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v25, a0
 ; RV32-NEXT:    addi a0, zero, 4
 ; RV32-NEXT:    vmv.s.x v26, a0
 ; RV32-NEXT:    vmv.v.i v27, 0
 ; RV32-NEXT:    vsetivli a0, 6, e16,m1,tu,mu
 ; RV32-NEXT:    vslideup.vi v27, v26, 5
 ; RV32-NEXT:    vsetivli a0, 7, e16,m1,tu,mu
 ; RV32-NEXT:    vslideup.vi v27, v25, 6
-; RV32-NEXT:    addi a0, zero, 113
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI12_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
 ; RV32-NEXT:    vmv.v.i v12, -1
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v12, v25
+; RV32-NEXT:    addi a0, zero, 113
+; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v8, v27, v0.t
 ; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_xv_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 6

 ; RV64-NEXT:    ret
   %s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3>
   ret <8 x i64> %s
 }
 
 define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
 ; RV32-LABEL: vrgather_shuffle_vx_v8i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a0, zero, 140
-; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI13_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
+; RV32-NEXT:    vmv4r.v v28, v8
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    vrgatherei16.vv v28, v8, v25
+; RV32-NEXT:    vrgatherei16.vv v8, v28, v25
+; RV32-NEXT:    addi a0, zero, 140
+; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
+; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI13_1)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI13_1)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
-; RV32-NEXT:    vmv.v.i v8, 5
+; RV32-NEXT:    vmv.v.i v28, 5
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
-; RV32-NEXT:    vrgatherei16.vv v28, v8, v25, v0.t
-; RV32-NEXT:    vmv4r.v v8, v28
+; RV32-NEXT:    vrgatherei16.vv v8, v28, v25, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_vx_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, zero, 115
 ; RV64-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; RV64-NEXT:    vmv.s.x v0, a0
 ; RV64-NEXT:    lui a0, %hi(.LCPI13_0)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_zero_v32i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse8.v v25, (a1)
+; LMULMAX1-NEXT:    vse8.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse8.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <32 x i8> undef, i8 0, i32 0
   %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
   store <32 x i8> %b, <32 x i8>* %x
   ret void
 }
 

 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_zero_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse16.v v25, (a1)
+; LMULMAX1-NEXT:    vse16.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <16 x i16> undef, i16 0, i32 0
   %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
   store <16 x i16> %b, <16 x i16>* %x
   ret void
 }
 

 ; LMULMAX2-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_zero_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse32.v v25, (a1)
+; LMULMAX1-NEXT:    vse32.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <8 x i32> undef, i32 0, i32 0
   %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %b, <8 x i32>* %x
   ret void
 }
 

 ; LMULMAX2-RV32-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-RV32-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_zero_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
-; LMULMAX1-RV32-NEXT:    vse32.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi a0, a0, 16
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX8-RV64-LABEL: splat_zero_v4i64:
 ; LMULMAX8-RV64:       # %bb.0:
 ; LMULMAX8-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX8-RV64-NEXT:    vmv.v.i v26, 0
 ; LMULMAX8-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX8-RV64-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: splat_zero_v4i64:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v26, 0
 ; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_zero_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
-; LMULMAX1-RV64-NEXT:    vse64.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    addi a0, a0, 16
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = insertelement <4 x i64> undef, i64 0, i32 0
   %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 

 ; LMULMAX2-NEXT:    vmv.v.i v26, -1
 ; LMULMAX2-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_allones_v32i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse8.v v25, (a1)
+; LMULMAX1-NEXT:    vse8.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse8.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <32 x i8> undef, i8 -1, i32 0
   %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
   store <32 x i8> %b, <32 x i8>* %x
   ret void
 }
 

 ; LMULMAX2-NEXT:    vmv.v.i v26, -1
 ; LMULMAX2-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_allones_v16i16:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse16.v v25, (a1)
+; LMULMAX1-NEXT:    vse16.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <16 x i16> undef, i16 -1, i32 0
   %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
   store <16 x i16> %b, <16 x i16>* %x
   ret void
 }
 

 ; LMULMAX2-NEXT:    vmv.v.i v26, -1
 ; LMULMAX2-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: splat_allones_v8i32:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-NEXT:    addi a1, a0, 16
-; LMULMAX1-NEXT:    vse32.v v25, (a1)
+; LMULMAX1-NEXT:    vse32.v v25, (a0)
+; LMULMAX1-NEXT:    addi a0, a0, 16
 ; LMULMAX1-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-NEXT:    ret
   %a = insertelement <8 x i32> undef, i32 -1, i32 0
   %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %b, <8 x i32>* %x
   ret void
 }
 

 ; LMULMAX2-RV32-NEXT:    vmv.v.i v26, -1
 ; LMULMAX2-RV32-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_allones_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
-; LMULMAX1-RV32-NEXT:    vse32.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi a0, a0, 16
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX8-RV64-LABEL: splat_allones_v4i64:
 ; LMULMAX8-RV64:       # %bb.0:
 ; LMULMAX8-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX8-RV64-NEXT:    vmv.v.i v26, -1
 ; LMULMAX8-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX8-RV64-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: splat_allones_v4i64:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v26, -1
 ; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_allones_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
-; LMULMAX1-RV64-NEXT:    vse64.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    addi a0, a0, 16
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = insertelement <4 x i64> undef, i64 -1, i32 0
   %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 

 ; nxv8i64 at index 0: the v16i64 type was used to get the LMUL, the size of
 ; which exceeded maximum-expected size of 512. The scalable container type of
 ; nxv8i64 should have been used instead.
 define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) {
 ; LMULMAX8-RV32-LABEL: vadd_vx_v16i64:
 ; LMULMAX8-RV32:       # %bb.0:
 ; LMULMAX8-RV32-NEXT:    vsetivli a4, 16, e64,m8,ta,mu
 ; LMULMAX8-RV32-NEXT:    vle64.v v8, (a0)
-; LMULMAX8-RV32-NEXT:    lui a0, 349525
-; LMULMAX8-RV32-NEXT:    addi a0, a0, 1365
-; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e32,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a0
 ; LMULMAX8-RV32-NEXT:    addi a0, zero, 32
-; LMULMAX8-RV32-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; LMULMAX8-RV32-NEXT:    vsetvli a4, a0, e32,m8,ta,mu
 ; LMULMAX8-RV32-NEXT:    vmv.v.x v16, a2
+; LMULMAX8-RV32-NEXT:    lui a2, 349525
+; LMULMAX8-RV32-NEXT:    addi a2, a2, 1365
+; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e32,m1,ta,mu
+; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a2
+; LMULMAX8-RV32-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
 ; LMULMAX8-RV32-NEXT:    vmerge.vxm v16, v16, a1, v0
 ; LMULMAX8-RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; LMULMAX8-RV32-NEXT:    vadd.vv v8, v8, v16
 ; LMULMAX8-RV32-NEXT:    vse64.v v8, (a3)
 ; LMULMAX8-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV32-LABEL: vadd_vx_v16i64:
 ; LMULMAX2-RV32:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

 ; RV32-NEXT:    lui a1, 349525
 ; RV32-NEXT:    addi a2, a1, 1365
 ; RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.x v26, a2
 ; RV32-NEXT:    addi a1, a1, 1366
 ; RV32-NEXT:    vmv.s.x v26, a1
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vmulh.vv v26, v25, v26
-; RV32-NEXT:    addi a1, zero, 1
-; RV32-NEXT:    addi a2, zero, 3
-; RV32-NEXT:    vsetivli a3, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a2
-; RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
+; RV32-NEXT:    addi a1, zero, 3
+; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
+; RV32-NEXT:    vmv.s.x v0, a1
+; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.v.i v27, -1
 ; RV32-NEXT:    vmerge.vim v27, v27, 0, v0
-; RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
+; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vmul.vv v25, v25, v27
 ; RV32-NEXT:    vadd.vv v25, v26, v25
-; RV32-NEXT:    addi a2, zero, 63
-; RV32-NEXT:    vsrl.vx v26, v25, a2
+; RV32-NEXT:    addi a1, zero, 63
+; RV32-NEXT:    vsrl.vx v26, v25, a1
+; RV32-NEXT:    addi a1, zero, 1
 ; RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v27, a1
 ; RV32-NEXT:    vmv.v.i v28, 0
 ; RV32-NEXT:    vsetivli a1, 3, e32,m1,tu,mu
 ; RV32-NEXT:    vslideup.vi v28, v27, 2
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vsra.vv v25, v25, v28
 ; RV32-NEXT:    vadd.vv v25, v25, v26

 }
 
 define void @mulhu_v32i8(<32 x i8>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhu_v32i8:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle8.v v26, (a0)
+; LMULMAX2-RV32-NEXT:    lui a2, 66049
+; LMULMAX2-RV32-NEXT:    addi a2, a2, 32
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
+; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    lui a2, %hi(.LCPI129_0)
+; LMULMAX2-RV32-NEXT:    addi a2, a2, %lo(.LCPI129_0)
+; LMULMAX2-RV32-NEXT:    vle8.v v28, (a2)
+; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
+; LMULMAX2-RV32-NEXT:    vmerge.vim v8, v30, 1, v0
+; LMULMAX2-RV32-NEXT:    vsrl.vv v8, v26, v8
+; LMULMAX2-RV32-NEXT:    vmulhu.vv v28, v8, v28
+; LMULMAX2-RV32-NEXT:    vsub.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT:    lui a2, 163907
+; LMULMAX2-RV32-NEXT:    addi a2, a2, -2044
+; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
+; LMULMAX2-RV32-NEXT:    addi a2, zero, -128
+; LMULMAX2-RV32-NEXT:    vsetvli a3, a1, e8,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmerge.vxm v30, v30, a2, v0
+; LMULMAX2-RV32-NEXT:    vmulhu.vv v26, v26, v30
+; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a2, 8208
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 513
 ; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 4
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV32-NEXT:    lui a2, 66785
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 78
 ; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 3, v0
 ; LMULMAX2-RV32-NEXT:    lui a2, 529160
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, 304
 ; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
-; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 2, v0
-; LMULMAX2-RV32-NEXT:    lui a2, 163907
-; LMULMAX2-RV32-NEXT:    addi a2, a2, -2044
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
-; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v30, 0
-; LMULMAX2-RV32-NEXT:    addi a2, zero, -128
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v8, v30, a2, v0
-; LMULMAX2-RV32-NEXT:    lui a2, 66049
-; LMULMAX2-RV32-NEXT:    addi a2, a2, 32
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV32-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    lui a1, %hi(.LCPI129_0)
-; LMULMAX2-RV32-NEXT:    addi a1, a1, %lo(.LCPI129_0)
-; LMULMAX2-RV32-NEXT:    vle8.v v10, (a1)
-; LMULMAX2-RV32-NEXT:    vmerge.vim v30, v30, 1, v0
-; LMULMAX2-RV32-NEXT:    vsrl.vv v30, v26, v30
-; LMULMAX2-RV32-NEXT:    vmulhu.vv v30, v30, v10
-; LMULMAX2-RV32-NEXT:    vsub.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT:    vmulhu.vv v26, v26, v8
-; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v30
+; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 2, v0
 ; LMULMAX2-RV32-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhu_v32i8:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle8.v v26, (a0)
+; LMULMAX2-RV64-NEXT:    lui a2, 66049
+; LMULMAX2-RV64-NEXT:    addiw a2, a2, 32
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
+; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; LMULMAX2-RV64-NEXT:    lui a2, %hi(.LCPI129_0)
+; LMULMAX2-RV64-NEXT:    addi a2, a2, %lo(.LCPI129_0)
+; LMULMAX2-RV64-NEXT:    vle8.v v28, (a2)
+; LMULMAX2-RV64-NEXT:    vmv.v.i v30, 0
+; LMULMAX2-RV64-NEXT:    vmerge.vim v8, v30, 1, v0
+; LMULMAX2-RV64-NEXT:    vsrl.vv v8, v26, v8
+; LMULMAX2-RV64-NEXT:    vmulhu.vv v28, v8, v28
+; LMULMAX2-RV64-NEXT:    vsub.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT:    lui a2, 163907
+; LMULMAX2-RV64-NEXT:    addiw a2, a2, -2044
+; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
+; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
+; LMULMAX2-RV64-NEXT:    addi a2, zero, -128
+; LMULMAX2-RV64-NEXT:    vsetvli a3, a1, e8,m2,ta,mu
+; LMULMAX2-RV64-NEXT:    vmerge.vxm v30, v30, a2, v0
+; LMULMAX2-RV64-NEXT:    vmulhu.vv v26, v26, v30
+; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a2, 8208
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 513
 ; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, 4
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 1, v0
 ; LMULMAX2-RV64-NEXT:    lui a2, 66785
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 78
 ; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 3, v0
 ; LMULMAX2-RV64-NEXT:    lui a2, 529160
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, 304
 ; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
-; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 2, v0
-; LMULMAX2-RV64-NEXT:    lui a2, 163907
-; LMULMAX2-RV64-NEXT:    addiw a2, a2, -2044
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
-; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.v.i v30, 0
-; LMULMAX2-RV64-NEXT:    addi a2, zero, -128
-; LMULMAX2-RV64-NEXT:    vmerge.vxm v8, v30, a2, v0
-; LMULMAX2-RV64-NEXT:    lui a2, 66049
-; LMULMAX2-RV64-NEXT:    addiw a2, a2, 32
-; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
 ; LMULMAX2-RV64-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; LMULMAX2-RV64-NEXT:    lui a1, %hi(.LCPI129_0)
-; LMULMAX2-RV64-NEXT:    addi a1, a1, %lo(.LCPI129_0)
-; LMULMAX2-RV64-NEXT:    vle8.v v10, (a1)
-; LMULMAX2-RV64-NEXT:    vmerge.vim v30, v30, 1, v0
-; LMULMAX2-RV64-NEXT:    vsrl.vv v30, v26, v30
-; LMULMAX2-RV64-NEXT:    vmulhu.vv v30, v30, v10
-; LMULMAX2-RV64-NEXT:    vsub.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT:    vmulhu.vv v26, v26, v8
-; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v30
+; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 2, v0
 ; LMULMAX2-RV64-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: mulhu_v32i8:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-NEXT:    addi a1, a0, 16

 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vdivu.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    vse64.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: mulhu_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    addi a1, zero, 2
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vle64.v v25, (a0)
-; LMULMAX1-RV64-NEXT:    addi a2, a0, 16
-; LMULMAX1-RV64-NEXT:    vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
+; LMULMAX1-RV64-NEXT:    vle64.v v26, (a1)
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v27, 0
-; LMULMAX1-RV64-NEXT:    addi a3, zero, -1
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 63
-; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a3
-; LMULMAX1-RV64-NEXT:    lui a3, 1044935
-; LMULMAX1-RV64-NEXT:    addiw a3, a3, 455
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 12
-; LMULMAX1-RV64-NEXT:    addi a3, a3, 455
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 12
-; LMULMAX1-RV64-NEXT:    addi a3, a3, 455
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 13
-; LMULMAX1-RV64-NEXT:    addi a3, a3, 911
-; LMULMAX1-RV64-NEXT:    vmv.v.x v28, a3
-; LMULMAX1-RV64-NEXT:    lui a3, 4681
-; LMULMAX1-RV64-NEXT:    addiw a3, a3, 585
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 12
-; LMULMAX1-RV64-NEXT:    addi a3, a3, 585
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 12
-; LMULMAX1-RV64-NEXT:    addi a3, a3, 585
-; LMULMAX1-RV64-NEXT:    slli a3, a3, 13
-; LMULMAX1-RV64-NEXT:    addi a3, a3, 1171
-; LMULMAX1-RV64-NEXT:    vmv.s.x v28, a3
+; LMULMAX1-RV64-NEXT:    addi a2, zero, -1
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 63
+; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a2
+; LMULMAX1-RV64-NEXT:    lui a2, 1044935
+; LMULMAX1-RV64-NEXT:    addiw a2, a2, 455
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, 455
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, 455
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 13
+; LMULMAX1-RV64-NEXT:    addi a2, a2, 911
+; LMULMAX1-RV64-NEXT:    vmv.v.x v28, a2
+; LMULMAX1-RV64-NEXT:    lui a2, 4681
+; LMULMAX1-RV64-NEXT:    addiw a2, a2, 585
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, 585
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, 585
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 13
+; LMULMAX1-RV64-NEXT:    addi a2, a2, 1171
+; LMULMAX1-RV64-NEXT:    vmv.s.x v28, a2
 ; LMULMAX1-RV64-NEXT:    vmulhu.vv v28, v26, v28
 ; LMULMAX1-RV64-NEXT:    vsub.vv v26, v26, v28
 ; LMULMAX1-RV64-NEXT:    vmulhu.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v28
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v27, 3
-; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a1
+; LMULMAX1-RV64-NEXT:    addi a2, zero, 2
+; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a2
 ; LMULMAX1-RV64-NEXT:    vsrl.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v27, 2
-; LMULMAX1-RV64-NEXT:    addi a1, zero, 1
-; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a1
-; LMULMAX1-RV64-NEXT:    lui a1, 1035469
-; LMULMAX1-RV64-NEXT:    addiw a1, a1, -819
-; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
-; LMULMAX1-RV64-NEXT:    addi a1, a1, -819
-; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
-; LMULMAX1-RV64-NEXT:    addi a1, a1, -819
-; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
-; LMULMAX1-RV64-NEXT:    addi a1, a1, -819
-; LMULMAX1-RV64-NEXT:    vmv.v.x v28, a1
-; LMULMAX1-RV64-NEXT:    lui a1, 1026731
-; LMULMAX1-RV64-NEXT:    addiw a1, a1, -1365
-; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
-; LMULMAX1-RV64-NEXT:    addi a1, a1, -1365
-; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
-; LMULMAX1-RV64-NEXT:    addi a1, a1, -1365
-; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
-; LMULMAX1-RV64-NEXT:    addi a1, a1, -1365
-; LMULMAX1-RV64-NEXT:    vmv.s.x v28, a1
+; LMULMAX1-RV64-NEXT:    addi a2, zero, 1
+; LMULMAX1-RV64-NEXT:    vmv.s.x v27, a2
+; LMULMAX1-RV64-NEXT:    lui a2, 1035469
+; LMULMAX1-RV64-NEXT:    addiw a2, a2, -819
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, -819
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, -819
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, -819
+; LMULMAX1-RV64-NEXT:    vmv.v.x v28, a2
+; LMULMAX1-RV64-NEXT:    lui a2, 1026731
+; LMULMAX1-RV64-NEXT:    addiw a2, a2, -1365
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, -1365
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, -1365
+; LMULMAX1-RV64-NEXT:    slli a2, a2, 12
+; LMULMAX1-RV64-NEXT:    addi a2, a2, -1365
+; LMULMAX1-RV64-NEXT:    vmv.s.x v28, a2
 ; LMULMAX1-RV64-NEXT:    vmulhu.vv v25, v25, v28
 ; LMULMAX1-RV64-NEXT:    vsrl.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT:    vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT:    vse64.v v26, (a1)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 
 define void @mulhs_v32i8(<32 x i8>* %x) {
 ; LMULMAX2-RV32-LABEL: mulhs_v32i8:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV32-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle8.v v26, (a0)
+; LMULMAX2-RV32-NEXT:    addi a2, zero, -123
+; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a2
 ; LMULMAX2-RV32-NEXT:    lui a2, 304453
 ; LMULMAX2-RV32-NEXT:    addi a2, a2, -1452
 ; LMULMAX2-RV32-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a2
+; LMULMAX2-RV32-NEXT:    addi a2, zero, 57
 ; LMULMAX2-RV32-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    vmerge.vxm v28, v28, a2, v0
+; LMULMAX2-RV32-NEXT:    vmulhu.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vmv.v.i v28, 7
 ; LMULMAX2-RV32-NEXT:    vmerge.vim v28, v28, 1, v0
-; LMULMAX2-RV32-NEXT:    addi a1, zero, -123
-; LMULMAX2-RV32-NEXT:    vmv.v.x v30, a1
-; LMULMAX2-RV32-NEXT:    addi a1, zero, 57
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v30, v30, a1, v0
-; LMULMAX2-RV32-NEXT:    vmulhu.vv v26, v26, v30
 ; LMULMAX2-RV32-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV64-LABEL: mulhs_v32i8:
 ; LMULMAX2-RV64:       # %bb.0:
 ; LMULMAX2-RV64-NEXT:    addi a1, zero, 32
 ; LMULMAX2-RV64-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
 ; LMULMAX2-RV64-NEXT:    vle8.v v26, (a0)
+; LMULMAX2-RV64-NEXT:    addi a2, zero, -123
+; LMULMAX2-RV64-NEXT:    vmv.v.x v28, a2
 ; LMULMAX2-RV64-NEXT:    lui a2, 304453
 ; LMULMAX2-RV64-NEXT:    addiw a2, a2, -1452
 ; LMULMAX2-RV64-NEXT:    vsetivli a3, 1, e32,m1,ta,mu
 ; LMULMAX2-RV64-NEXT:    vmv.s.x v0, a2
+; LMULMAX2-RV64-NEXT:    addi a2, zero, 57
 ; LMULMAX2-RV64-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; LMULMAX2-RV64-NEXT:    vmerge.vxm v28, v28, a2, v0
+; LMULMAX2-RV64-NEXT:    vmulhu.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vmv.v.i v28, 7
 ; LMULMAX2-RV64-NEXT:    vmerge.vim v28, v28, 1, v0
-; LMULMAX2-RV64-NEXT:    addi a1, zero, -123
-; LMULMAX2-RV64-NEXT:    vmv.v.x v30, a1
-; LMULMAX2-RV64-NEXT:    addi a1, zero, 57
-; LMULMAX2-RV64-NEXT:    vmerge.vxm v30, v30, a1, v0
-; LMULMAX2-RV64-NEXT:    vmulhu.vv v26, v26, v30
 ; LMULMAX2-RV64-NEXT:    vsrl.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse8.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: mulhs_v32i8:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle8.v v25, (a0)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

 ; LMULMAX2-NEXT:    addi a1, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vmclr.m v25
 ; LMULMAX2-NEXT:    vse1.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_zeros_v32i1:
 ; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmclr.m v25
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi a0, a0, 2
 ; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_zeros_v32i1:
 ; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmclr.m v25
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    addi a0, a0, 2
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   store <32 x i1> zeroinitializer, <32 x i1>* %x
   ret void
 }
 
 define void @splat_ones_v64i1(<64 x i1>* %x) {
 ; LMULMAX2-LABEL: splat_ones_v64i1:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    addi a1, a0, 4
 ; LMULMAX2-NEXT:    addi a2, zero, 32
 ; LMULMAX2-NEXT:    vsetvli a2, a2, e8,m2,ta,mu
 ; LMULMAX2-NEXT:    vmset.m v25
 ; LMULMAX2-NEXT:    vse1.v v25, (a1)
 ; LMULMAX2-NEXT:    vse1.v v25, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_ones_v64i1:
 ; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 6
-; LMULMAX1-RV32-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmset.m v25
+; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi a1, a0, 6
 ; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 4
 ; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV32-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT:    addi a0, a0, 2
 ; LMULMAX1-RV32-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: splat_ones_v64i1:
 ; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    addi a1, a0, 6
-; LMULMAX1-RV64-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
+; LMULMAX1-RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmset.m v25
+; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 6
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
-; LMULMAX1-RV64-NEXT:    addi a1, a0, 2
-; LMULMAX1-RV64-NEXT:    vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT:    addi a0, a0, 2
 ; LMULMAX1-RV64-NEXT:    vse1.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

 ; RV32-NEXT:    vloxei32.v v10, (a0), v16, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_v32i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vmv1r.v v25, v0
 ; RV64-NEXT:    vsetivli a1, 16, e8,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v8, 16
-; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
-; RV64-NEXT:    vsext.vf8 v16, v26
-; RV64-NEXT:    vsetivli a1, 16, e8,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v10, 16
+; RV64-NEXT:    vslidedown.vi v28, v8, 16
+; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
+; RV64-NEXT:    vsext.vf8 v16, v28
 ; RV64-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,tu,mu
 ; RV64-NEXT:    vloxei64.v v26, (a0), v16, v0.t
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,tu,mu
 ; RV64-NEXT:    vmv1r.v v0, v25

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

 ;
 ; RV64-LABEL: mscatter_baseidx_v32i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vsext.vf8 v16, v10
 ; RV64-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    vsetivli a1, 16, e8,m2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v10, 16
-; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
-; RV64-NEXT:    vsext.vf8 v16, v26
-; RV64-NEXT:    vsetivli a1, 16, e8,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v8, 16
+; RV64-NEXT:    vslidedown.vi v28, v10, 16
+; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
+; RV64-NEXT:    vsext.vf8 v8, v28
 ; RV64-NEXT:    vsetivli a1, 2, e8,m1,ta,mu
 ; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli a1, 8, e8,m1,ta,mu
-; RV64-NEXT:    vsoxei64.v v26, (a0), v16, v0.t
+; RV64-NEXT:    vsoxei64.v v26, (a0), v8, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
   call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> %val, <32 x i8*> %ptrs, i32 1, <32 x i1> %m)
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

 
 declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>)
 
 define i64 @vreduce_add_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_add_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_add_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)
 
 define i64 @vreduce_and_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_and_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_and_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)
 
 define i64 @vreduce_or_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_or_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_or_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)
 
 define i64 @vreduce_xor_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_xor_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_xor_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
 
 define i64 @vreduce_smin_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_smin_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)
 
 define i64 @vreduce_smax_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_smax_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smax_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
 
 define i64 @vreduce_umin_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_umin_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umin_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

 
 declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
 
 define i64 @vreduce_umax_v1i64(<1 x i64>* %x) {
 ; RV32-LABEL: vreduce_umax_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
+; RV32-NEXT:    addi a0, zero, 32
+; RV32-NEXT:    vsrl.vx v26, v25, a0
+; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_umax_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll

; CHECK-NEXT:    ret
   ret <2 x i64> %v
 }
 
 declare <4 x i64> @llvm.experimental.stepvector.v4i64()
 
 define <4 x i64> @stepvector_v4i64() {
 ; LMULMAX1-LABEL: stepvector_v4i64:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    addi a0, zero, 2
-; LMULMAX1-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; LMULMAX1-NEXT:    vmv.v.i v9, 3
+; LMULMAX1-NEXT:    addi a0, zero, 2
 ; LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; LMULMAX1-NEXT:    vid.v v8
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX2-LABEL: stepvector_v4i64:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; LMULMAX2-NEXT:    vid.v v8
 ; LMULMAX2-NEXT:    ret
   %v = call <4 x i64> @llvm.experimental.stepvector.v4i64()
   ret <4 x i64> %v
 }
 
 declare <8 x i64> @llvm.experimental.stepvector.v8i64()
 
 define <8 x i64> @stepvector_v8i64() {
 ; LMULMAX1-LABEL: stepvector_v8i64:
 ; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v9, 3
 ; LMULMAX1-NEXT:    addi a0, zero, 2
-; LMULMAX1-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; LMULMAX1-NEXT:    vmv.v.i v10, 5
-; LMULMAX1-NEXT:    addi a1, zero, 4
-; LMULMAX1-NEXT:    vmv.s.x v10, a1
+; LMULMAX1-NEXT:    addi a0, zero, 4
+; LMULMAX1-NEXT:    vmv.s.x v10, a0
 ; LMULMAX1-NEXT:    vmv.v.i v11, 7
-; LMULMAX1-NEXT:    addi a1, zero, 6
-; LMULMAX1-NEXT:    vmv.s.x v11, a1
-; LMULMAX1-NEXT:    vmv.v.i v9, 3
-; LMULMAX1-NEXT:    vmv.s.x v9, a0
+; LMULMAX1-NEXT:    addi a0, zero, 6
+; LMULMAX1-NEXT:    vmv.s.x v11, a0
 ; LMULMAX1-NEXT:    vid.v v8
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX2-LABEL: stepvector_v8i64:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    lui a0, %hi(.LCPI14_0)
 ; LMULMAX2-NEXT:    addi a0, a0, %lo(.LCPI14_0)
 ; LMULMAX2-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; LMULMAX2-NEXT:    vle64.v v10, (a0)
 ; LMULMAX2-NEXT:    vid.v v8
 ; LMULMAX2-NEXT:    ret
   %v = call <8 x i64> @llvm.experimental.stepvector.v8i64()
   ret <8 x i64> %v
 }
 
 declare <16 x i64> @llvm.experimental.stepvector.v16i64()
 
 define <16 x i64> @stepvector_v16i64() {
 ; LMULMAX1-LABEL: stepvector_v16i64:
 ; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v9, 3
 ; LMULMAX1-NEXT:    addi a0, zero, 2
-; LMULMAX1-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; LMULMAX1-NEXT:    vmv.v.i v10, 5
-; LMULMAX1-NEXT:    addi a1, zero, 4
-; LMULMAX1-NEXT:    vmv.s.x v10, a1
+; LMULMAX1-NEXT:    addi a0, zero, 4
+; LMULMAX1-NEXT:    vmv.s.x v10, a0
 ; LMULMAX1-NEXT:    vmv.v.i v11, 7
-; LMULMAX1-NEXT:    addi a1, zero, 6
-; LMULMAX1-NEXT:    vmv.s.x v11, a1
+; LMULMAX1-NEXT:    addi a0, zero, 6
+; LMULMAX1-NEXT:    vmv.s.x v11, a0
 ; LMULMAX1-NEXT:    vmv.v.i v12, 9
-; LMULMAX1-NEXT:    addi a1, zero, 8
-; LMULMAX1-NEXT:    vmv.s.x v12, a1
+; LMULMAX1-NEXT:    addi a0, zero, 8
+; LMULMAX1-NEXT:    vmv.s.x v12, a0
 ; LMULMAX1-NEXT:    vmv.v.i v13, 11
-; LMULMAX1-NEXT:    addi a1, zero, 10
-; LMULMAX1-NEXT:    vmv.s.x v13, a1
+; LMULMAX1-NEXT:    addi a0, zero, 10
+; LMULMAX1-NEXT:    vmv.s.x v13, a0
 ; LMULMAX1-NEXT:    vmv.v.i v14, 13
-; LMULMAX1-NEXT:    addi a1, zero, 12
-; LMULMAX1-NEXT:    vmv.s.x v14, a1
+; LMULMAX1-NEXT:    addi a0, zero, 12
+; LMULMAX1-NEXT:    vmv.s.x v14, a0
 ; LMULMAX1-NEXT:    vmv.v.i v15, 15
-; LMULMAX1-NEXT:    addi a1, zero, 14
-; LMULMAX1-NEXT:    vmv.s.x v15, a1
-; LMULMAX1-NEXT:    vmv.v.i v9, 3
-; LMULMAX1-NEXT:    vmv.s.x v9, a0
+; LMULMAX1-NEXT:    addi a0, zero, 14
+; LMULMAX1-NEXT:    vmv.s.x v15, a0
 ; LMULMAX1-NEXT:    vid.v v8
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX2-LABEL: stepvector_v16i64:
 ; LMULMAX2:       # %bb.0:
 ; LMULMAX2-NEXT:    lui a0, %hi(.LCPI15_0)
 ; LMULMAX2-NEXT:    addi a0, a0, %lo(.LCPI15_0)
 ; LMULMAX2-NEXT:    vsetivli a1, 4, e64,m2,ta,mu

llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll

declare void @llvm.riscv.vse.nxv1i64(
   <vscale x 1 x i64>*,
   i64);
 
 define i64 @test(<vscale x 1 x i64> %0) nounwind {
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.entry:
   ; CHECK:   liveins: $v8
   ; CHECK:   [[COPY:%[0-9]+]]:vr = COPY $v8
-  ; CHECK:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
-  ; CHECK:   dead %3:gpr = PseudoVSETIVLI 1, 88, implicit-def $vl, implicit-def $vtype
-  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, $noreg, 64, implicit $vl, implicit $vtype
+  ; CHECK:   dead %2:gpr = PseudoVSETIVLI 1, 88, implicit-def $vl, implicit-def $vtype
+  ; CHECK:   PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 64, implicit $vl, implicit $vtype
   ; CHECK:   [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load 8 from %ir.a)
   ; CHECK:   $x10 = COPY [[LD]]
   ; CHECK:   PseudoRET implicit $x10
 entry:
   %a = alloca i64
   %b = bitcast i64* %a to <vscale x 1 x i64>*
   call void @llvm.riscv.vse.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %b,
     i64 1)
   %c = load i64, i64* %a
   ret i64 %c
 }

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV32MV-NEXT:    vle16.v v25, (a1)
 ; RV32MV-NEXT:    lui a1, %hi(.LCPI4_0)
 ; RV32MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; RV32MV-NEXT:    vle16.v v26, (a1)
 ; RV32MV-NEXT:    vid.v v27
 ; RV32MV-NEXT:    vsub.vv v25, v25, v27
 ; RV32MV-NEXT:    vmul.vv v25, v25, v26
 ; RV32MV-NEXT:    vsll.vi v26, v25, 1
-; RV32MV-NEXT:    vmv.v.i v27, 10
 ; RV32MV-NEXT:    addi a1, zero, 9
+; RV32MV-NEXT:    vmv.v.i v27, 10
 ; RV32MV-NEXT:    vmv.s.x v27, a1
 ; RV32MV-NEXT:    vsll.vv v26, v26, v27
 ; RV32MV-NEXT:    addi a1, zero, 2047
 ; RV32MV-NEXT:    vand.vx v25, v25, a1
 ; RV32MV-NEXT:    vmv.v.i v27, 0
 ; RV32MV-NEXT:    addi a2, zero, 1
 ; RV32MV-NEXT:    vmv1r.v v28, v27
 ; RV32MV-NEXT:    vmv.s.x v28, a2

 ; RV64MV-NEXT:    vle16.v v25, (a1)
 ; RV64MV-NEXT:    lui a1, %hi(.LCPI4_0)
 ; RV64MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; RV64MV-NEXT:    vle16.v v26, (a1)
 ; RV64MV-NEXT:    vid.v v27
 ; RV64MV-NEXT:    vsub.vv v25, v25, v27
 ; RV64MV-NEXT:    vmul.vv v25, v25, v26
 ; RV64MV-NEXT:    vsll.vi v26, v25, 1
-; RV64MV-NEXT:    vmv.v.i v27, 10
 ; RV64MV-NEXT:    addi a1, zero, 9
+; RV64MV-NEXT:    vmv.v.i v27, 10
 ; RV64MV-NEXT:    vmv.s.x v27, a1
 ; RV64MV-NEXT:    vsll.vv v26, v26, v27
 ; RV64MV-NEXT:    addi a1, zero, 2047
 ; RV64MV-NEXT:    vand.vx v25, v25, a1
 ; RV64MV-NEXT:    vmv.v.i v27, 0
 ; RV64MV-NEXT:    addi a2, zero, 1
 ; RV64MV-NEXT:    vmv1r.v v28, v27
 ; RV64MV-NEXT:    vmv.s.x v28, a2