[RISCV] [1/2] Add IR intrinsic for Zbe extension

[LevyHsu]

Summary

RV32/64:

bcomress
bdecompress

RV64 ONLY:

bcomressw
bdecompressw

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

36

Can you line up the start of the SDT* argument on each of these lines so that they're in columns like the ones above. I don't care that they don't line up with the ones above. I just want these 4 new ones to be lined up.

[LevyHsu]

1. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
   • Format fix: Aligned SDT*** for:

riscv_bcompress
      riscv_bcompressw
      riscv_bdecompress
      riscv_bdecompressw

[craig.topper]

LGTM

clang/include/clang/Basic/BuiltinsRISCV.def

 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb,64bit")
 
 // Zbc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
 TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
 
+// Zbe extension
+TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
+TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",
+               "experimental-zbe,64bit")
+TARGET_BUILTIN(__builtin_riscv_bdecompress_32, "ZiZiZi", "nc",
+               "experimental-zbe")
+TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc",
+               "experimental-zbe,64bit")
+
 // Zbp extension
 TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp")
 TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
 TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp")

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
+  case RISCV::BI__builtin_riscv_bcompress_32:
+  case RISCV::BI__builtin_riscv_bcompress_64:
+  case RISCV::BI__builtin_riscv_bdecompress_32:
+  case RISCV::BI__builtin_riscv_bdecompress_64:
   case RISCV::BI__builtin_riscv_grev_32:
   case RISCV::BI__builtin_riscv_grev_64:
   case RISCV::BI__builtin_riscv_gorc_32:
   case RISCV::BI__builtin_riscv_gorc_64:
   case RISCV::BI__builtin_riscv_shfl_32:
   case RISCV::BI__builtin_riscv_shfl_64:
   case RISCV::BI__builtin_riscv_unshfl_32:
   case RISCV::BI__builtin_riscv_unshfl_64:
case RISCV::BI__builtin_riscv_clmul:
       break;
     case RISCV::BI__builtin_riscv_clmulh:
       ID = Intrinsic::riscv_clmulh;
       break;
     case RISCV::BI__builtin_riscv_clmulr:
       ID = Intrinsic::riscv_clmulr;
       break;
 
+    // Zbe
+    case RISCV::BI__builtin_riscv_bcompress_32:
+    case RISCV::BI__builtin_riscv_bcompress_64:
+      ID = Intrinsic::riscv_bcompress;
+      break;
+    case RISCV::BI__builtin_riscv_bdecompress_32:
+    case RISCV::BI__builtin_riscv_bdecompress_64:
+      ID = Intrinsic::riscv_bdecompress;
+      break;
+
     // Zbp
     case RISCV::BI__builtin_riscv_grev_32:
     case RISCV::BI__builtin_riscv_grev_64:
       ID = Intrinsic::riscv_grev;
       break;
     case RISCV::BI__builtin_riscv_gorc_32:
     case RISCV::BI__builtin_riscv_gorc_64:
       ID = Intrinsic::riscv_gorc;

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbe -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBE
+
+// RV32ZBE-LABEL: @bcompress(
+// RV32ZBE-NEXT:  entry:
+// RV32ZBE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBE-NEXT:    ret i32 [[TMP2]]
+//
+long bcompress(long rs1, long rs2) {
+  return __builtin_riscv_bcompress_32(rs1, rs2);
+}
+
+// RV32ZBE-LABEL: @bdecompress(
+// RV32ZBE-NEXT:  entry:
+// RV32ZBE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV32ZBE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV32ZBE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV32ZBE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV32ZBE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBE-NEXT:    ret i32 [[TMP2]]
+//
+long bdecompress(long rs1, long rs2) {
+  return __builtin_riscv_bdecompress_32(rs1, rs2);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbe -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBE
+
+// RV64ZBE-LABEL: @bcompressw(
+// RV64ZBE-NEXT:  entry:
+// RV64ZBE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZBE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZBE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBE-NEXT:    ret i32 [[TMP2]]
+//
+int bcompressw(int rs1, int rs2) {
+  return __builtin_riscv_bcompress_32(rs1, rs2);
+}
+
+// RV64ZBE-LABEL: @bdecompressw(
+// RV64ZBE-NEXT:  entry:
+// RV64ZBE-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBE-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBE-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBE-NEXT:    store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
+// RV64ZBE-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
+// RV64ZBE-NEXT:    [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
+// RV64ZBE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBE-NEXT:    ret i32 [[TMP2]]
+//
+int bdecompressw(int rs1, int rs2) {
+  return __builtin_riscv_bdecompress_32(rs1, rs2);
+}
+
+// RV64ZBE-LABEL: @bcompress(
+// RV64ZBE-NEXT:  entry:
+// RV64ZBE-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBE-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBE-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBE-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBE-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBE-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBE-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.bcompress.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBE-NEXT:    ret i64 [[TMP2]]
+//
+long bcompress(long rs1, long rs2) {
+  return __builtin_riscv_bcompress_64(rs1, rs2);
+}
+
+// RV64ZBE-LABEL: @bdecompress(
+// RV64ZBE-NEXT:  entry:
+// RV64ZBE-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBE-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBE-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
+// RV64ZBE-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
+// RV64ZBE-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
+// RV64ZBE-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
+// RV64ZBE-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.bdecompress.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBE-NEXT:    ret i64 [[TMP2]]
+//
+long bdecompress(long rs1, long rs2) {
+  return __builtin_riscv_bdecompress_64(rs1, rs2);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
 
   // Zbc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbe
+  def int_riscv_bcompress   : BitManipGPRGPRIntrinsics;
+  def int_riscv_bdecompress : BitManipGPRGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
   def int_riscv_shfl  : BitManipGPRGPRIntrinsics;
   def int_riscv_unshfl  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_n  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_b  : BitManipGPRGPRIntrinsics;
   def int_riscv_xperm_h  : BitManipGPRGPRIntrinsics;

llvm/lib/Target/RISCV/RISCVISelLowering.h

enum NodeType : unsigned {
   GREV,
   GREVW,
   GORC,
   GORCW,
   SHFL,
   SHFLW,
   UNSHFL,
   UNSHFLW,
+  // Bit Compress/Decompress implement the generic bit extract and bit deposit
+  // functions. This operation is also referred to as bit gather/scatter, bit
+  // pack/unpack, parallel extract/deposit, compress/expand, or right
+  // compress/right expand.
+  BCOMPRESS,
+  BCOMPRESSW,
+  BDECOMPRESS,
+  BDECOMPRESSW,
   // Vector Extension
   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
   // for the VL value to be used for the operation.
   VMV_V_X_VL,
   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
   // for the VL value to be used for the operation.
   VFMV_V_F_VL,
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (!Subtarget.hasStdExtZbb()) {
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
   if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
 
+  if (Subtarget.hasStdExtZbe() && Subtarget.is64Bit())
+    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
+
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::ADD, MVT::i32, Custom);
     setOperationAction(ISD::SUB, MVT::i32, Custom);
     setOperationAction(ISD::SHL, MVT::i32, Custom);
     setOperationAction(ISD::SRA, MVT::i32, Custom);
     setOperationAction(ISD::SRL, MVT::i32, Custom);
 
     setOperationAction(ISD::UADDO, MVT::i32, Custom);
case Intrinsic::riscv_gorc: {
     return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
   }
   case Intrinsic::riscv_shfl:
   case Intrinsic::riscv_unshfl: {
     unsigned Opc =
         IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
     return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
   }
+  case Intrinsic::riscv_bcompress:
+  case Intrinsic::riscv_bdecompress: {
+    unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS
+                                                       : RISCVISD::BDECOMPRESS;
+    return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
+  }
   case Intrinsic::riscv_vmv_x_s:
     assert(Op.getValueType() == XLenVT && "Unexpected VT!");
     return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
                        Op.getOperand(1));
   case Intrinsic::riscv_vmv_v_x:
     return lowerScalarSplat(Op.getOperand(1), Op.getOperand(2),
                             Op.getSimpleValueType(), DL, DAG, Subtarget);
   case Intrinsic::riscv_vfmv_v_f:
case Intrinsic::riscv_unshfl: {
                              DAG.getConstant(0xf, DL, MVT::i64));
         Opc =
             IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
       }
       SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       break;
     }
+    case Intrinsic::riscv_bcompress:
+    case Intrinsic::riscv_bdecompress: {
+      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+             "Unexpected custom legalisation");
+      SDValue NewOp1 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue NewOp2 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
+      unsigned Opc = IntNo == Intrinsic::riscv_bcompress
+                         ? RISCVISD::BCOMPRESSW
+                         : RISCVISD::BDECOMPRESSW;
+      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+      break;
+    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();
       if (VT.bitsLT(XLenVT)) {
         // Simple case just extract using vmv.x.s and truncate.
         SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
                                       Subtarget.getXLenVT(), N->getOperand(1));
         Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));
unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
   case RISCVISD::ROLW:
   case RISCVISD::RORW:
   case RISCVISD::GREVW:
   case RISCVISD::GORCW:
   case RISCVISD::FSLW:
   case RISCVISD::FSRW:
   case RISCVISD::SHFLW:
   case RISCVISD::UNSHFLW:
+  case RISCVISD::BCOMPRESSW:
+  case RISCVISD::BDECOMPRESSW:
     // TODO: As the result is sign-extended, this is conservatively correct. A
     // more precise answer could be calculated for SRAW depending on known
     // bits in the shift amount.
     return 33;
   case RISCVISD::SHFL:
   case RISCVISD::UNSHFL: {
     // There is no SHFLIW, but a i64 SHFLI with bit 4 of the control word
     // cleared doesn't affect bit 31. The upper 32 bits will be shuffled, but
#define NODE_NAME_CASE(NODE)                                                   \
   NODE_NAME_CASE(GREV)
   NODE_NAME_CASE(GREVW)
   NODE_NAME_CASE(GORC)
   NODE_NAME_CASE(GORCW)
   NODE_NAME_CASE(SHFL)
   NODE_NAME_CASE(SHFLW)
   NODE_NAME_CASE(UNSHFL)
   NODE_NAME_CASE(UNSHFLW)
+  NODE_NAME_CASE(BCOMPRESS)
+  NODE_NAME_CASE(BCOMPRESSW)
+  NODE_NAME_CASE(BDECOMPRESS)
+  NODE_NAME_CASE(BDECOMPRESSW)
   NODE_NAME_CASE(VMV_V_X_VL)
   NODE_NAME_CASE(VFMV_V_F_VL)
   NODE_NAME_CASE(VMV_X_S)
   NODE_NAME_CASE(VMV_S_X_VL)
   NODE_NAME_CASE(VFMV_S_F_VL)
   NODE_NAME_CASE(SPLAT_VECTOR_I64)
   NODE_NAME_CASE(READ_VLENB)
   NODE_NAME_CASE(TRUNCATE_VECTOR_VL)

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def riscv_grev   : SDNode<"RISCVISD::GREV",   SDTIntBinOp>;
 def riscv_grevw  : SDNode<"RISCVISD::GREVW",  SDT_RISCVIntBinOpW>;
 def riscv_gorc   : SDNode<"RISCVISD::GORC",   SDTIntBinOp>;
 def riscv_gorcw  : SDNode<"RISCVISD::GORCW",  SDT_RISCVIntBinOpW>;
 def riscv_shfl   : SDNode<"RISCVISD::SHFL",   SDTIntBinOp>;
 def riscv_shflw  : SDNode<"RISCVISD::SHFLW",  SDT_RISCVIntBinOpW>;
 def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
 def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
+def riscv_bcompress    : SDNode<"RISCVISD::BCOMPRESS",   SDTIntBinOp>;
+def riscv_bcompressw   : SDNode<"RISCVISD::BCOMPRESSW",  SDT_RISCVIntBinOpW>;
+def riscv_bdecompress  : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
+def riscv_bdecompressw : SDNode<"RISCVISD::BDECOMPRESSW",SDT_RISCVIntBinOpW>;
 
 def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
   let Name = "UImmLog2XLenHalf";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidUImmLog2XLenHalf";
 }
 
 def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{

 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbc] in {
 def : PatGprGpr<int_riscv_clmul, CLMUL>;
 def : PatGprGpr<int_riscv_clmulh, CLMULH>;
 def : PatGprGpr<int_riscv_clmulr, CLMULR>;
 } // Predicates = [HasStdExtZbc]
 
+let Predicates = [HasStdExtZbe] in {
+def : PatGprGpr<riscv_bcompress, BCOMPRESS>;
+def : PatGprGpr<riscv_bdecompress, BDECOMPRESS>;
+} // Predicates = [HasStdExtZbe]
+
+let Predicates = [HasStdExtZbe, IsRV64] in {
+def : PatGprGpr<riscv_bcompressw, BCOMPRESSW>;
+def : PatGprGpr<riscv_bdecompressw, BDECOMPRESSW>;
+} // Predicates = [HasStdExtZbe, IsRV64]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr<int_riscv_crc32_b, CRC32B>;
 def : PatGpr<int_riscv_crc32_h, CRC32H>;
 def : PatGpr<int_riscv_crc32_w, CRC32W>;
 def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
 def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
 def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
 } // Predicates = [HasStdExtZbr]
 
 let Predicates = [HasStdExtZbr, IsRV64] in {
 def : PatGpr<int_riscv_crc32_d, CRC32D>;
 def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
 } // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBE
+
+declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+
+define i32 @bcompress32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: bcompress32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    bcompress a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBE-LABEL: bcompress32:
+; RV32IBE:       # %bb.0:
+; RV32IBE-NEXT:    bcompress a0, a0, a1
+; RV32IBE-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+
+define i32 @bdecompress32(i32 %a, i32 %b) nounwind {
+; RV32IB-LABEL: bdecompress32:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    bdecompress a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBE-LABEL: bdecompress32:
+; RV32IBE:       # %bb.0:
+; RV32IBE-NEXT:    bdecompress a0, a0, a1
+; RV32IBE-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBE
+
+declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+
+define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: bcompress32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bcompressw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBE-LABEL: bcompress32:
+; RV64IBE:       # %bb.0:
+; RV64IBE-NEXT:    bcompressw a0, a0, a1
+; RV64IBE-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+
+define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
+; RV64IB-LABEL: bdecompress32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bdecompressw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBE-LABEL: bdecompress32:
+; RV64IBE:       # %bb.0:
+; RV64IBE-NEXT:    bdecompressw a0, a0, a1
+; RV64IBE-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
+
+define i64 @bcompress64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bcompress64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bcompress a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBE-LABEL: bcompress64:
+; RV64IBE:       # %bb.0:
+; RV64IBE-NEXT:    bcompress a0, a0, a1
+; RV64IBE-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
+
+define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bdecompress64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    bdecompress a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBE-LABEL: bdecompress64:
+; RV64IBE:       # %bb.0:
+; RV64IBE-NEXT:    bdecompress a0, a0, a1
+; RV64IBE-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}