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Differential D100618

[RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte.
ClosedPublic

Authored by craig.topper on Apr 15 2021, 9:20 PM.

Details

Reviewers
frasercrmck
HsiangKai
khchen
arcbbb
evandro
rogfer01
Commits
rG7ed01a420a2d: [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte.
Summary

As noted in the FIXME there's a sort of agreement that the any
extra bits stored will be 0.

The generated code is pretty terrible. I was really hoping we
could use a tail undisturbed trick, but tail undisturbed no
longer applies to masked destinations in the current draft
spec.

Fingers crossed that it isn't common to do this. I doubt IR
from clang or the vectorizer would ever create this kind of store.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 15 2021, 9:20 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptApr 15 2021, 9:20 PM
craig.topper requested review of this revision.Apr 15 2021, 9:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 15 2021, 9:20 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B99073: Diff 337978.Apr 15 2021, 10:09 PM
HsiangKai added inline comments.Apr 16 2021, 12:59 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
3723–3729

nit: ... need to pad the unused ...

frasercrmck accepted this revision.Apr 16 2021, 1:18 AM

LGTM, thanks. I'd hope there's a better way of lowering this but it's not coming to me at this time. As you say, it's probably quite rare.

This revision is now accepted and ready to land.Apr 16 2021, 1:18 AM
This revision was landed with ongoing or failed builds.Apr 19 2021, 11:05 AM
Closed by commit rG7ed01a420a2d: [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG7ed01a420a2d: [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte..

Revision Contents

Diff 338564

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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} }
SDValue SDValue
RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op, RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
auto *Store = cast<StoreSDNode>(Op); auto *Store = cast<StoreSDNode>(Op);
SDLoc DL(Op); SDLoc DL(Op);
MVT VT = Store->getValue().getSimpleValueType(); SDValue StoreVal = Store->getValue();
MVT VT = StoreVal.getSimpleValueType();
// FIXME: We probably need to zero any extra bits in a byte for mask stores. // If the size less than a byte, we need to the unused bits with 0s.
// This is tricky to do. if (VT.getVectorElementType() == MVT::i1 && VT.getVectorNumElements() < 8) {
VT = MVT::v8i1;
StoreVal = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
DAG.getConstant(0, DL, VT), StoreVal,
DAG.getIntPtrConstant(0, DL));
}
HsiangKaiUnsubmitted
Not Done
ReplyInline Actions

nit: ... need to pad the unused ...

HsiangKai: nit: ... need to pad the unused ...
MVT ContainerVT = getContainerForFixedLengthVector(VT); MVT ContainerVT = getContainerForFixedLengthVector(VT);
SDValue VL = SDValue VL =
DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
SDValue NewValue = SDValue NewValue =
convertToScalableVector(ContainerVT, Store->getValue(), DAG, Subtarget); convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);
return DAG.getMemIntrinsicNode( return DAG.getMemIntrinsicNode(
RISCVISD::VSE_VL, DL, DAG.getVTList(MVT::Other), RISCVISD::VSE_VL, DL, DAG.getVTList(MVT::Other),
{Store->getChain(), NewValue, Store->getBasePtr(), VL}, {Store->getChain(), NewValue, Store->getBasePtr(), VL},
Store->getMemoryVT(), Store->getMemOperand()); Store->getMemoryVT(), Store->getMemOperand());
} }
SDValue RISCVTargetLowering::lowerMLOAD(SDValue Op, SelectionDAG &DAG) const { SDValue RISCVTargetLowering::lowerMLOAD(SDValue Op, SelectionDAG &DAG) const {
auto *Load = cast<MaskedLoadSDNode>(Op); auto *Load = cast<MaskedLoadSDNode>(Op);
▲ Show 20 Lines • Show All 4,229 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

Show First 20 Lines • Show All 561 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
ret <16 x i64> %z ret <16 x i64> %z
} }
define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) { define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) {
; CHECK-LABEL: truncstore_v2i8_v2i1: ; CHECK-LABEL: truncstore_v2i8_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vand.vi v25, v8, 1
; CHECK-NEXT: vmsne.vi v26, v25, 0 ; CHECK-NEXT: vmsne.vi v0, v25, 0
; CHECK-NEXT: vse1.v v26, (a0) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i8> %x to <2 x i1> %y = trunc <2 x i8> %x to <2 x i1>
store <2 x i1> %y, <2 x i1>* %z store <2 x i1> %y, <2 x i1>* %z
ret void ret void
} }
define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) { define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i16_v2i8: ; CHECK-LABEL: truncstore_v2i16_v2i8:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

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} }
define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) { define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-LABEL: extract_v2i1_v64i1_0: ; LMULMAX2-LABEL: extract_v2i1_v64i1_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu ; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; LMULMAX2-NEXT: vle1.v v25, (a0) ; LMULMAX2-NEXT: vle1.v v0, (a0)
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; LMULMAX2-NEXT: vmv.v.i v25, 0
; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX2-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
; LMULMAX2-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
; LMULMAX2-NEXT: vse1.v v25, (a1) ; LMULMAX2-NEXT: vse1.v v25, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i1_v64i1_0: ; LMULMAX1-LABEL: extract_v2i1_v64i1_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli a2, 16, e8,m1,ta,mu ; LMULMAX1-NEXT: vsetivli a2, 16, e8,m1,ta,mu
; LMULMAX1-NEXT: vle1.v v25, (a0) ; LMULMAX1-NEXT: vle1.v v0, (a0)
; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
; LMULMAX1-NEXT: vse1.v v25, (a1) ; LMULMAX1-NEXT: vse1.v v25, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) { define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-LABEL: extract_v2i1_v64i1_2: ; LMULMAX2-LABEL: extract_v2i1_v64i1_2:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu ; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; LMULMAX2-NEXT: vle1.v v0, (a0) ; LMULMAX2-NEXT: vle1.v v0, (a0)
; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m2,ta,mu ; LMULMAX2-NEXT: vsetivli a0, 2, e8,m2,ta,mu
; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2 ; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; LMULMAX2-NEXT: vmsne.vi v0, v26, 0
; LMULMAX2-NEXT: vmv.v.i v25, 0
; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX2-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
; LMULMAX2-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
; LMULMAX2-NEXT: vse1.v v25, (a1) ; LMULMAX2-NEXT: vse1.v v25, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i1_v64i1_2: ; LMULMAX1-LABEL: extract_v2i1_v64i1_2:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli a2, 16, e8,m1,ta,mu ; LMULMAX1-NEXT: vsetivli a2, 16, e8,m1,ta,mu
; LMULMAX1-NEXT: vle1.v v0, (a0) ; LMULMAX1-NEXT: vle1.v v0, (a0)
; LMULMAX1-NEXT: vmv.v.i v25, 0 ; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 ; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2
; LMULMAX1-NEXT: vmsne.vi v26, v25, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
; LMULMAX1-NEXT: vse1.v v26, (a1) ; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
; LMULMAX1-NEXT: vse1.v v25, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) { define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-LABEL: extract_v2i1_v64i1_42: ; LMULMAX2-LABEL: extract_v2i1_v64i1_42:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a0, a0, 4 ; LMULMAX2-NEXT: addi a0, a0, 4
; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu ; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; LMULMAX2-NEXT: vle1.v v0, (a0) ; LMULMAX2-NEXT: vle1.v v0, (a0)
; LMULMAX2-NEXT: vmv.v.i v26, 0 ; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m2,ta,mu ; LMULMAX2-NEXT: vsetivli a0, 2, e8,m2,ta,mu
; LMULMAX2-NEXT: vslidedown.vi v26, v26, 10 ; LMULMAX2-NEXT: vslidedown.vi v26, v26, 10
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; LMULMAX2-NEXT: vmsne.vi v0, v26, 0
; LMULMAX2-NEXT: vmv.v.i v25, 0
; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX2-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
; LMULMAX2-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 ; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
; LMULMAX2-NEXT: vse1.v v25, (a1) ; LMULMAX2-NEXT: vse1.v v25, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i1_v64i1_42: ; LMULMAX1-LABEL: extract_v2i1_v64i1_42:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 4 ; LMULMAX1-NEXT: addi a0, a0, 4
; LMULMAX1-NEXT: vsetivli a2, 16, e8,m1,ta,mu ; LMULMAX1-NEXT: vsetivli a2, 16, e8,m1,ta,mu
; LMULMAX1-NEXT: vle1.v v0, (a0) ; LMULMAX1-NEXT: vle1.v v0, (a0)
; LMULMAX1-NEXT: vmv.v.i v25, 0 ; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; LMULMAX1-NEXT: vslidedown.vi v25, v25, 10 ; LMULMAX1-NEXT: vslidedown.vi v25, v25, 10
; LMULMAX1-NEXT: vmsne.vi v26, v25, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
; LMULMAX1-NEXT: vse1.v v26, (a1) ; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v26, 0
; LMULMAX1-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
; LMULMAX1-NEXT: vse1.v v25, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_0: ; CHECK-LABEL: extract_v2i1_nxv2i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v0, (a0) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_2: ; CHECK-LABEL: extract_v2i1_nxv2i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 ; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 2, e8,mf4,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v25, 2 ; CHECK-NEXT: vslidedown.vi v25, v25, 2
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v26, v25, 0 ; CHECK-NEXT: vmsne.vi v0, v25, 0
; CHECK-NEXT: vse1.v v26, (a0) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_0: ; CHECK-LABEL: extract_v2i1_nxv64i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v0, (a0) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_2: ; CHECK-LABEL: extract_v2i1_nxv64i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli a1, 2, e8,m8,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m8,ta,mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0) ; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_42: ; CHECK-LABEL: extract_v2i1_nxv64i1_42:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a1, zero, 42 ; CHECK-NEXT: addi a1, zero, 42
; CHECK-NEXT: vsetivli a2, 2, e8,m8,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e8,m8,ta,mu
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0) ; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv32i1_26: ; CHECK-LABEL: extract_v2i1_nxv32i1_26:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 0 ; CHECK-NEXT: vmv.v.i v28, 0
; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 ; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
; CHECK-NEXT: vsetivli a1, 2, e8,m4,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m4,ta,mu
; CHECK-NEXT: vslidedown.vi v28, v28, 26 ; CHECK-NEXT: vslidedown.vi v28, v28, 26
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v28, 0 ; CHECK-NEXT: vmsne.vi v0, v28, 0
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0) ; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) { define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

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} }
define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) { define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32: ; CHECK-LABEL: fcmp_une_vv_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a3, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vle32.v v26, (a1)
; CHECK-NEXT: vmfne.vv v27, v25, v26 ; CHECK-NEXT: vmfne.vv v0, v25, v26
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v27, (a2) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y %b = load <4 x float>, <4 x float>* %y
%c = fcmp une <4 x float> %a, %b %c = fcmp une <4 x float> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) { define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32_nonans: ; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a3, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vle32.v v26, (a1)
; CHECK-NEXT: vmfne.vv v27, v25, v26 ; CHECK-NEXT: vmfne.vv v0, v25, v26
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v27, (a2) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y %b = load <4 x float>, <4 x float>* %y
%c = fcmp nnan une <4 x float> %a, %b %c = fcmp nnan une <4 x float> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) { define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64: ; CHECK-LABEL: fcmp_ogt_vv_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli a3, 2, e64,m1,ta,mu
; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vle64.v v25, (a0)
; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vle64.v v26, (a1)
; CHECK-NEXT: vmflt.vv v27, v26, v25 ; CHECK-NEXT: vmflt.vv v0, v26, v25
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v27, (a2) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y %b = load <2 x double>, <2 x double>* %y
%c = fcmp ogt <2 x double> %a, %b %c = fcmp ogt <2 x double> %a, %b
store <2 x i1> %c, <2 x i1>* %z store <2 x i1> %c, <2 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) { define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans: ; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli a3, 2, e64,m1,ta,mu
; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vle64.v v25, (a0)
; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vle64.v v26, (a1)
; CHECK-NEXT: vmflt.vv v27, v26, v25 ; CHECK-NEXT: vmflt.vv v0, v26, v25
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v27, (a2) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y %b = load <2 x double>, <2 x double>* %y
%c = fcmp nnan ogt <2 x double> %a, %b %c = fcmp nnan ogt <2 x double> %a, %b
store <2 x i1> %c, <2 x i1>* %z store <2 x i1> %c, <2 x i1>* %z
ret void ret void
} }
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} }
define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) { define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64: ; CHECK-LABEL: fcmp_ole_vv_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e64,m2,ta,mu ; CHECK-NEXT: vsetivli a3, 4, e64,m2,ta,mu
; CHECK-NEXT: vle64.v v26, (a0) ; CHECK-NEXT: vle64.v v26, (a0)
; CHECK-NEXT: vle64.v v28, (a1) ; CHECK-NEXT: vle64.v v28, (a1)
; CHECK-NEXT: vmfle.vv v25, v26, v28 ; CHECK-NEXT: vmfle.vv v0, v26, v28
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2) ; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y %b = load <4 x double>, <4 x double>* %y
%c = fcmp ole <4 x double> %a, %b %c = fcmp ole <4 x double> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) { define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans: ; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e64,m2,ta,mu ; CHECK-NEXT: vsetivli a3, 4, e64,m2,ta,mu
; CHECK-NEXT: vle64.v v26, (a0) ; CHECK-NEXT: vle64.v v26, (a0)
; CHECK-NEXT: vle64.v v28, (a1) ; CHECK-NEXT: vle64.v v28, (a1)
; CHECK-NEXT: vmfle.vv v25, v26, v28 ; CHECK-NEXT: vmfle.vv v0, v26, v28
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2) ; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y %b = load <4 x double>, <4 x double>* %y
%c = fcmp nnan ole <4 x double> %a, %b %c = fcmp nnan ole <4 x double> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
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; CHECK-LABEL: fcmp_ord_vv_v4f16: ; CHECK-LABEL: fcmp_ord_vv_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a3, 4, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a1) ; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmfeq.vv v27, v25, v25 ; CHECK-NEXT: vmfeq.vv v27, v25, v25
; CHECK-NEXT: vmfeq.vv v25, v26, v26 ; CHECK-NEXT: vmfeq.vv v25, v26, v26
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v25, v25, v27 ; CHECK-NEXT: vmand.mm v0, v25, v27
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2) ; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x %a = load <4 x half>, <4 x half>* %x
%b = load <4 x half>, <4 x half>* %y %b = load <4 x half>, <4 x half>* %y
%c = fcmp ord <4 x half> %a, %b %c = fcmp ord <4 x half> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) { define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_uno_vv_v4f16: ; CHECK-LABEL: fcmp_uno_vv_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a3, 2, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a1) ; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: vle16.v v26, (a0) ; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmfne.vv v27, v25, v25 ; CHECK-NEXT: vmfne.vv v27, v25, v25
; CHECK-NEXT: vmfne.vv v25, v26, v26 ; CHECK-NEXT: vmfne.vv v25, v26, v26
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v25, v25, v27 ; CHECK-NEXT: vmor.mm v0, v25, v27
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a2) ; CHECK-NEXT: vse1.v v25, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x %a = load <2 x half>, <2 x half>* %x
%b = load <2 x half>, <2 x half>* %y %b = load <2 x half>, <2 x half>* %y
%c = fcmp uno <2 x half> %a, %b %c = fcmp uno <2 x half> %a, %b
store <2 x i1> %c, <2 x i1>* %z store <2 x i1> %c, <2 x i1>* %z
ret void ret void
} }
Show All 32 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) { define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32: ; CHECK-LABEL: fcmp_une_vf_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vmfne.vf v26, v25, fa0 ; CHECK-NEXT: vmfne.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0 %b = insertelement <4 x float> undef, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
%d = fcmp une <4 x float> %a, %c %d = fcmp une <4 x float> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) { define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32_nonans: ; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vmfne.vf v26, v25, fa0 ; CHECK-NEXT: vmfne.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0 %b = insertelement <4 x float> undef, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
%d = fcmp nnan une <4 x float> %a, %c %d = fcmp nnan une <4 x float> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64: ; CHECK-LABEL: fcmp_ogt_vf_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vle64.v v25, (a0)
; CHECK-NEXT: vmfgt.vf v26, v25, fa0 ; CHECK-NEXT: vmfgt.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0 %b = insertelement <2 x double> undef, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
%d = fcmp ogt <2 x double> %a, %c %d = fcmp ogt <2 x double> %a, %c
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans: ; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vle64.v v25, (a0)
; CHECK-NEXT: vmfgt.vf v26, v25, fa0 ; CHECK-NEXT: vmfgt.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0 %b = insertelement <2 x double> undef, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
%d = fcmp nnan ogt <2 x double> %a, %c %d = fcmp nnan ogt <2 x double> %a, %c
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) { define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64: ; CHECK-LABEL: fcmp_ole_vf_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu
; CHECK-NEXT: vle64.v v26, (a0) ; CHECK-NEXT: vle64.v v26, (a0)
; CHECK-NEXT: vmfle.vf v25, v26, fa0 ; CHECK-NEXT: vmfle.vf v0, v26, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0 %b = insertelement <4 x double> undef, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
%d = fcmp ole <4 x double> %a, %c %d = fcmp ole <4 x double> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) { define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans: ; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu
; CHECK-NEXT: vle64.v v26, (a0) ; CHECK-NEXT: vle64.v v26, (a0)
; CHECK-NEXT: vmfle.vf v25, v26, fa0 ; CHECK-NEXT: vmfle.vf v0, v26, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0 %b = insertelement <4 x double> undef, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
%d = fcmp nnan ole <4 x double> %a, %c %d = fcmp nnan ole <4 x double> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
; CHECK-LABEL: fcmp_ord_vf_v4f16: ; CHECK-LABEL: fcmp_ord_vf_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v27, v26, fa0 ; CHECK-NEXT: vmfeq.vf v27, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v25, v25 ; CHECK-NEXT: vmfeq.vv v26, v25, v25
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v25, v26, v27 ; CHECK-NEXT: vmand.mm v0, v26, v27
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x %a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> undef, half %y, i32 0 %b = insertelement <4 x half> undef, half %y, i32 0
%c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
%d = fcmp ord <4 x half> %a, %c %d = fcmp ord <4 x half> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) { define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_uno_vf_v4f16: ; CHECK-LABEL: fcmp_uno_vf_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v27, v26, fa0 ; CHECK-NEXT: vmfne.vf v27, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v25, v25 ; CHECK-NEXT: vmfne.vv v26, v25, v25
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v25, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v27
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x %a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> undef, half %y, i32 0 %b = insertelement <2 x half> undef, half %y, i32 0
%c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer %c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer
%d = fcmp uno <2 x half> %a, %c %d = fcmp uno <2 x half> %a, %c
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
Show All 33 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) { define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32: ; CHECK-LABEL: fcmp_une_fv_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vmfne.vf v26, v25, fa0 ; CHECK-NEXT: vmfne.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0 %b = insertelement <4 x float> undef, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
%d = fcmp une <4 x float> %c, %a %d = fcmp une <4 x float> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) { define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32_nonans: ; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vmfne.vf v26, v25, fa0 ; CHECK-NEXT: vmfne.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0 %b = insertelement <4 x float> undef, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
%d = fcmp nnan une <4 x float> %c, %a %d = fcmp nnan une <4 x float> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64: ; CHECK-LABEL: fcmp_ogt_fv_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vle64.v v25, (a0)
; CHECK-NEXT: vmflt.vf v26, v25, fa0 ; CHECK-NEXT: vmflt.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0 %b = insertelement <2 x double> undef, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
%d = fcmp ogt <2 x double> %c, %a %d = fcmp ogt <2 x double> %c, %a
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans: ; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; CHECK-NEXT: vle64.v v25, (a0) ; CHECK-NEXT: vle64.v v25, (a0)
; CHECK-NEXT: vmflt.vf v26, v25, fa0 ; CHECK-NEXT: vmflt.vf v0, v25, fa0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vse1.v v26, (a1) ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0 %b = insertelement <2 x double> undef, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
%d = fcmp nnan ogt <2 x double> %c, %a %d = fcmp nnan ogt <2 x double> %c, %a
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }
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ret void ret void
} }
define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) { define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64: ; CHECK-LABEL: fcmp_ole_fv_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu
; CHECK-NEXT: vle64.v v26, (a0) ; CHECK-NEXT: vle64.v v26, (a0)
; CHECK-NEXT: vmfge.vf v25, v26, fa0 ; CHECK-NEXT: vmfge.vf v0, v26, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0 %b = insertelement <4 x double> undef, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
%d = fcmp ole <4 x double> %c, %a %d = fcmp ole <4 x double> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) { define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans: ; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e64,m2,ta,mu
; CHECK-NEXT: vle64.v v26, (a0) ; CHECK-NEXT: vle64.v v26, (a0)
; CHECK-NEXT: vmfge.vf v25, v26, fa0 ; CHECK-NEXT: vmfge.vf v0, v26, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0 %b = insertelement <4 x double> undef, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
%d = fcmp nnan ole <4 x double> %c, %a %d = fcmp nnan ole <4 x double> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
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; CHECK-LABEL: fcmp_ord_fv_v4f16: ; CHECK-LABEL: fcmp_ord_fv_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vv v27, v25, v25 ; CHECK-NEXT: vmfeq.vv v27, v25, v25
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v25, v25, v27 ; CHECK-NEXT: vmand.mm v0, v25, v27
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x %a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> undef, half %y, i32 0 %b = insertelement <4 x half> undef, half %y, i32 0
%c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer %c = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer
%d = fcmp ord <4 x half> %c, %a %d = fcmp ord <4 x half> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) { define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_uno_fv_v4f16: ; CHECK-LABEL: fcmp_uno_fv_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vv v27, v25, v25 ; CHECK-NEXT: vmfne.vv v27, v25, v25
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v25, v25, v27 ; CHECK-NEXT: vmor.mm v0, v25, v27
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x %a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> undef, half %y, i32 0 %b = insertelement <2 x half> undef, half %y, i32 0
%c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer %c = shufflevector <2 x half> %b, <2 x half> undef, <2 x i32> zeroinitializer
%d = fcmp uno <2 x half> %c, %a %d = fcmp uno <2 x half> %c, %a
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) { define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
; CHECK-LABEL: load_store_v1i1: ; CHECK-LABEL: load_store_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 1, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 1, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0) ; CHECK-NEXT: vle1.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 1, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <1 x i1>, <1 x i1>* %x %a = load <1 x i1>, <1 x i1>* %x
store <1 x i1> %a, <1 x i1>* %y store <1 x i1> %a, <1 x i1>* %y
ret void ret void
} }
define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) { define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
; CHECK-LABEL: load_store_v2i1: ; CHECK-LABEL: load_store_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0) ; CHECK-NEXT: vle1.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x i1>, <2 x i1>* %x %a = load <2 x i1>, <2 x i1>* %x
store <2 x i1> %a, <2 x i1>* %y store <2 x i1> %a, <2 x i1>* %y
ret void ret void
} }
define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) { define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
; CHECK-LABEL: load_store_v4i1: ; CHECK-LABEL: load_store_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 4, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0) ; CHECK-NEXT: vle1.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i1>, <4 x i1>* %x %a = load <4 x i1>, <4 x i1>* %x
store <4 x i1> %a, <4 x i1>* %y store <4 x i1> %a, <4 x i1>* %y
ret void ret void
} }
define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) { define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
define void @splat_ones_v1i1(<1 x i1>* %x) { define void @splat_ones_v1i1(<1 x i1>* %x) {
; CHECK-LABEL: splat_ones_v1i1: ; CHECK-LABEL: splat_ones_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 1, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 1, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v25 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 1, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0) ; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <1 x i1> <i1 1>, <1 x i1>* %x store <1 x i1> <i1 1>, <1 x i1>* %x
ret void ret void
} }
define void @splat_zeros_v2i1(<2 x i1>* %x) { define void @splat_zeros_v2i1(<2 x i1>* %x) {
; CHECK-LABEL: splat_zeros_v2i1: ; CHECK-LABEL: splat_zeros_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vmclr.m v25 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 2, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0) ; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x i1> zeroinitializer, <2 x i1>* %x store <2 x i1> zeroinitializer, <2 x i1>* %x
ret void ret void
} }
define void @splat_ones_v4i1(<4 x i1>* %x) { define void @splat_ones_v4i1(<4 x i1>* %x) {
; CHECK-LABEL: splat_ones_v4i1: ; CHECK-LABEL: splat_ones_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 4, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v25 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a1, 4, e8,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
; CHECK-NEXT: vse1.v v25, (a0) ; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
ret void ret void
} }
define void @splat_zeros_v8i1(<8 x i1>* %x) { define void @splat_zeros_v8i1(<8 x i1>* %x) {
; CHECK-LABEL: splat_zeros_v8i1: ; CHECK-LABEL: splat_zeros_v8i1:
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