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[RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte.
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Authored by craig.topper on Thu, Apr 15, 9:20 PM.

Details

Summary

As noted in the FIXME there's a sort of agreement that the any
extra bits stored will be 0.

The generated code is pretty terrible. I was really hoping we
could use a tail undisturbed trick, but tail undisturbed no
longer applies to masked destinations in the current draft
spec.

Fingers crossed that it isn't common to do this. I doubt IR
from clang or the vectorizer would ever create this kind of store.

Diff Detail

Event Timeline

craig.topper created this revision.Thu, Apr 15, 9:20 PM
craig.topper requested review of this revision.Thu, Apr 15, 9:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptThu, Apr 15, 9:20 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
HsiangKai added inline comments.Fri, Apr 16, 12:59 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
3723–3729

nit: ... need to pad the unused ...

frasercrmck accepted this revision.Fri, Apr 16, 1:18 AM

LGTM, thanks. I'd hope there's a better way of lowering this but it's not coming to me at this time. As you say, it's probably quite rare.

This revision is now accepted and ready to land.Fri, Apr 16, 1:18 AM
This revision was landed with ongoing or failed builds.Mon, Apr 19, 11:05 AM
This revision was automatically updated to reflect the committed changes.