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[RISCV] Custom isel the rest of the vector load/store intrinsics.
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Authored by craig.topper on Feb 19 2021, 4:11 PM.

Details

Summary

A previous patch moved the index versions. This moves the rest.
I also removed the custom lowering for VLEFF since we can now
do everything directly in the isel handling.

I had to update getLMUL to handle mask registers to index the
pseudo table correctly for VLE1/VSE1.

This is good for another 15K reduction in llc size.

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Event Timeline

craig.topper created this revision.Feb 19 2021, 4:11 PM
craig.topper requested review of this revision.Feb 19 2021, 4:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 19 2021, 4:11 PM
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Propagate memory operands if we happen to have them
clang-format

frasercrmck accepted this revision.Feb 22 2021, 2:23 AM

LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
67

This'll need a rebase as it's now in RISCVISelLowering. But this will allow me to get rid of getRegClassIDForVecVT, so thanks!

This revision is now accepted and ready to land.Feb 22 2021, 2:23 AM
This revision was landed with ongoing or failed builds.Feb 22 2021, 9:54 AM
This revision was automatically updated to reflect the committed changes.