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Differential D96108

[RISCV] Add support for splat fixed length build_vectors using RVV.
ClosedPublic

Authored by craig.topper on Feb 4 2021, 10:58 PM.

Details

Reviewers
frasercrmck
rogfer01
evandro
HsiangKai
khchen
Commits
rG8d8cafa32e83: [RISCV] Add support for splat fixed length build_vectors using RVV.
Summary

Building on the fixed vector support from D95705

I've added ISD nodes for vmv.v.x and vfmv.v.f and switched to
lowering the intrinsics to it. This allows us to share the same
isel patterns for both.

This doesn't handle splats of i64 on RV32 yet. The build_vector
gets converted to a vXi32 build_vector+bitcast during type
legalization. Not sure the best way to handle this at the moment.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 4 2021, 10:58 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 24 others. · View Herald TranscriptFeb 4 2021, 10:58 PM
craig.topper requested review of this revision.Feb 4 2021, 10:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 4 2021, 10:58 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B88033: Diff 321662.Feb 4 2021, 10:59 PM
craig.topper added a parent revision: D96103: [RISCV] Add support for fixed vector FMA..Feb 4 2021, 11:08 PM
craig.topper planned changes to this revision.Feb 5 2021, 11:41 AM

Forgot to add the fp tests.

craig.topper updated this revision to Diff 321866.Feb 5 2021, 1:36 PM

Add FP splat test

Harbormaster completed remote builds in B88133: Diff 321866.Feb 5 2021, 1:37 PM
craig.topper added a child revision: D96186: [RISCV] Add support for selecting vrgather.vx/vi for fixed vector splat shuffles..Feb 5 2021, 3:28 PM
frasercrmck accepted this revision.Feb 8 2021, 1:54 AM

LGTM

This revision is now accepted and ready to land.Feb 8 2021, 1:54 AM
This revision was landed with ongoing or failed builds.Feb 8 2021, 11:14 AM
Closed by commit rG8d8cafa32e83: [RISCV] Add support for splat fixed length build_vectors using RVV. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG8d8cafa32e83: [RISCV] Add support for splat fixed length build_vectors using RVV..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
6 lines
146 lines
17 lines
test/
CodeGen/
RISCV/
rvv/
437 lines
459 lines

Diff 321662

llvm/lib/Target/RISCV/RISCVISelLowering.h

//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
Lint: Lint
Inline Actions

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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesenum NodeType : unsigned {
// DAGs. Each node takes an input operand and a TargetConstant immediate // DAGs. Each node takes an input operand and a TargetConstant immediate
// shift amount, and outputs a bit-manipulated version of input. All operands // shift amount, and outputs a bit-manipulated version of input. All operands
// are of type XLenVT. // are of type XLenVT.
GREVI, GREVI,
GREVIW, GREVIW,
GORCI, GORCI,
GORCIW, GORCIW,
// Vector Extension // Vector Extension
// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
// for the VL value to be used for the operation.
VMV_V_X_VL,
// VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
// for the VL value to be used for the operation.
VFMV_V_F_VL,
// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT
// sign extended from the vector element size. NOTE: The result size will // sign extended from the vector element size. NOTE: The result size will
// never be less than the vector element size. // never be less than the vector element size.
VMV_X_S, VMV_X_S,
// Splats an i64 scalar to a vector type (with element type i64) where the // Splats an i64 scalar to a vector type (with element type i64) where the
// scalar is a sign-extended i32. // scalar is a sign-extended i32.
SPLAT_VECTOR_I64, SPLAT_VECTOR_I64,
// Read VLENB CSR // Read VLENB CSR
▲ Show 20 Lines • Show All 302 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
Lint: Lint
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 486 Lines • ▼ Show 20 Lines if (Subtarget.useRVVForFixedLengthVectors()) {
// By default everything must be expanded. // By default everything must be expanded.
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op)
setOperationAction(Op, VT, Expand); setOperationAction(Op, VT, Expand);
// We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed. // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom); setOperationAction(ISD::STORE, VT, Custom);
setOperationAction(ISD::ADD, VT, Custom); setOperationAction(ISD::ADD, VT, Custom);
setOperationAction(ISD::MUL, VT, Custom); setOperationAction(ISD::MUL, VT, Custom);
setOperationAction(ISD::SUB, VT, Custom); setOperationAction(ISD::SUB, VT, Custom);
setOperationAction(ISD::AND, VT, Custom); setOperationAction(ISD::AND, VT, Custom);
setOperationAction(ISD::OR, VT, Custom); setOperationAction(ISD::OR, VT, Custom);
setOperationAction(ISD::XOR, VT, Custom); setOperationAction(ISD::XOR, VT, Custom);
Show All 12 Lines if (Subtarget.useRVVForFixedLengthVectors()) {
// By default everything must be expanded. // By default everything must be expanded.
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op)
setOperationAction(Op, VT, Expand); setOperationAction(Op, VT, Expand);
// We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed. // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom); setOperationAction(ISD::STORE, VT, Custom);
setOperationAction(ISD::FADD, VT, Custom); setOperationAction(ISD::FADD, VT, Custom);
setOperationAction(ISD::FSUB, VT, Custom); setOperationAction(ISD::FSUB, VT, Custom);
setOperationAction(ISD::FMUL, VT, Custom); setOperationAction(ISD::FMUL, VT, Custom);
setOperationAction(ISD::FDIV, VT, Custom); setOperationAction(ISD::FDIV, VT, Custom);
setOperationAction(ISD::FNEG, VT, Custom); setOperationAction(ISD::FNEG, VT, Custom);
setOperationAction(ISD::FMA, VT, Custom); setOperationAction(ISD::FMA, VT, Custom);
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines case ISD::SETGE:
return RISCV::BGE; return RISCV::BGE;
case ISD::SETULT: case ISD::SETULT:
return RISCV::BLTU; return RISCV::BLTU;
case ISD::SETUGE: case ISD::SETUGE:
return RISCV::BGEU; return RISCV::BGEU;
} }
} }
// Return the largest legal scalable vector type that matches VT's element type.
static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT,
const RISCVSubtarget &Subtarget) {
assert(VT.isFixedLengthVector() &&
DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
"Expected legal fixed length vector!");
unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
assert(LMul <= 8 && isPowerOf2_32(LMul) && "Unexpected LMUL!");
switch (VT.getVectorElementType().SimpleTy) {
default:
llvm_unreachable("unexpected element type for RVV container");
case MVT::i8:
return MVT::getScalableVectorVT(MVT::i8, LMul * 8);
case MVT::i16:
return MVT::getScalableVectorVT(MVT::i16, LMul * 4);
case MVT::i32:
return MVT::getScalableVectorVT(MVT::i32, LMul * 2);
case MVT::i64:
return MVT::getScalableVectorVT(MVT::i64, LMul);
case MVT::f16:
return MVT::getScalableVectorVT(MVT::f16, LMul * 4);
case MVT::f32:
return MVT::getScalableVectorVT(MVT::f32, LMul * 2);
case MVT::f64:
return MVT::getScalableVectorVT(MVT::f64, LMul);
}
}
// Grow V to consume an entire RVV register.
static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(VT.isScalableVector() &&
"Expected to convert into a scalable vector!");
assert(V.getValueType().isFixedLengthVector() &&
"Expected a fixed length vector operand!");
SDLoc DL(V);
SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero);
}
// Shrink V so it's just big enough to maintain a VT's worth of data.
static SDValue convertFromScalableVector(EVT VT, SDValue V, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(VT.isFixedLengthVector() &&
"Expected to convert into a fixed length vector!");
assert(V.getValueType().isScalableVector() &&
"Expected a scalable vector operand!");
SDLoc DL(V);
SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero);
}
static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
MVT VT = Op.getSimpleValueType();
assert(VT.isFixedLengthVector() && "Unexpected vector!");
if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
SDLoc DL(Op);
SDValue VL =
DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
unsigned Opc = VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL
: RISCVISD::VMV_V_X_VL;
Splat = DAG.getNode(Opc, DL, ContainerVT, Splat, VL);
return convertFromScalableVector(VT, Splat, DAG, Subtarget);
}
return SDValue();
}
SDValue RISCVTargetLowering::LowerOperation(SDValue Op, SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: default:
report_fatal_error("unimplemented operand"); report_fatal_error("unimplemented operand");
case ISD::GlobalAddress: case ISD::GlobalAddress:
return lowerGlobalAddress(Op, DAG); return lowerGlobalAddress(Op, DAG);
case ISD::BlockAddress: case ISD::BlockAddress:
▲ Show 20 Lines • Show All 219 Lines • ▼ Show 20 Lines if (SrcEltSize > EltSize && (SrcEltSize / EltSize >= 4)) {
MVT::getVectorVT(MVT::getIntegerVT(SrcEltVT.getSizeInBits() / 2), MVT::getVectorVT(MVT::getIntegerVT(SrcEltVT.getSizeInBits() / 2),
VT.getVectorElementCount()); VT.getVectorElementCount());
SDValue FP2Int = DAG.getNode(Op.getOpcode(), DL, IVecVT, Src); SDValue FP2Int = DAG.getNode(Op.getOpcode(), DL, IVecVT, Src);
return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int); return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int);
} }
return Op; return Op;
} }
case ISD::BUILD_VECTOR:
return lowerBUILD_VECTOR(Op, DAG, Subtarget);
case ISD::LOAD: case ISD::LOAD:
return lowerFixedLengthVectorLoadToRVV(Op, DAG); return lowerFixedLengthVectorLoadToRVV(Op, DAG);
case ISD::STORE: case ISD::STORE:
return lowerFixedLengthVectorStoreToRVV(Op, DAG); return lowerFixedLengthVectorStoreToRVV(Op, DAG);
case ISD::ADD: case ISD::ADD:
return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL); return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL);
case ISD::SUB: case ISD::SUB:
return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL); return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL);
▲ Show 20 Lines • Show All 674 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::thread_pointer: { case Intrinsic::thread_pointer: {
EVT PtrVT = getPointerTy(DAG.getDataLayout()); EVT PtrVT = getPointerTy(DAG.getDataLayout());
return DAG.getRegister(RISCV::X4, PtrVT); return DAG.getRegister(RISCV::X4, PtrVT);
} }
case Intrinsic::riscv_vmv_x_s: case Intrinsic::riscv_vmv_x_s:
assert(Op.getValueType() == Subtarget.getXLenVT() && "Unexpected VT!"); assert(Op.getValueType() == Subtarget.getXLenVT() && "Unexpected VT!");
return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
Op.getOperand(1)); Op.getOperand(1));
case Intrinsic::riscv_vmv_v_x: {
SDValue Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(),
Op.getOperand(1));
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, Op.getValueType(),
Scalar, Op.getOperand(2));
}
case Intrinsic::riscv_vfmv_v_f:
return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, Op.getValueType(),
Op.getOperand(1), Op.getOperand(2));
} }
} }
SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
SDLoc DL(Op); SDLoc DL(Op);
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines SDValue ReadVL =
SDValue(DAG.getMachineNode(RISCV::PseudoReadVL, DL, Op->getValueType(1), SDValue(DAG.getMachineNode(RISCV::PseudoReadVL, DL, Op->getValueType(1),
Load.getValue(2)), Load.getValue(2)),
0); 0);
return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL);
} }
} }
} }
// Return the largest legal scalable vector type that matches VT's element type.
static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT,
const RISCVSubtarget &Subtarget) {
assert(VT.isFixedLengthVector() &&
DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
"Expected legal fixed length vector!");
unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
assert(LMul <= 8 && isPowerOf2_32(LMul) && "Unexpected LMUL!");
switch (VT.getVectorElementType().SimpleTy) {
default:
llvm_unreachable("unexpected element type for RVV container");
case MVT::i8:
return MVT::getScalableVectorVT(MVT::i8, LMul * 8);
case MVT::i16:
return MVT::getScalableVectorVT(MVT::i16, LMul * 4);
case MVT::i32:
return MVT::getScalableVectorVT(MVT::i32, LMul * 2);
case MVT::i64:
return MVT::getScalableVectorVT(MVT::i64, LMul);
case MVT::f16:
return MVT::getScalableVectorVT(MVT::f16, LMul * 4);
case MVT::f32:
return MVT::getScalableVectorVT(MVT::f32, LMul * 2);
case MVT::f64:
return MVT::getScalableVectorVT(MVT::f64, LMul);
}
}
// Grow V to consume an entire RVV register.
static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(VT.isScalableVector() &&
"Expected to convert into a scalable vector!");
assert(V.getValueType().isFixedLengthVector() &&
"Expected a fixed length vector operand!");
SDLoc DL(V);
SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero);
}
// Shrink V so it's just big enough to maintain a VT's worth of data.
static SDValue convertFromScalableVector(EVT VT, SDValue V, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(VT.isFixedLengthVector() &&
"Expected to convert into a fixed length vector!");
assert(V.getValueType().isScalableVector() &&
"Expected a scalable vector operand!");
SDLoc DL(V);
SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero);
}
SDValue SDValue
RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op, RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
auto *Load = cast<LoadSDNode>(Op); auto *Load = cast<LoadSDNode>(Op);
SDLoc DL(Op); SDLoc DL(Op);
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
▲ Show 20 Lines • Show All 2,596 Lines • ▼ Show 20 Lines#define NODE_NAME_CASE(NODE) \
NODE_NAME_CASE(FMV_X_ANYEXTH) NODE_NAME_CASE(FMV_X_ANYEXTH)
NODE_NAME_CASE(FMV_W_X_RV64) NODE_NAME_CASE(FMV_W_X_RV64)
NODE_NAME_CASE(FMV_X_ANYEXTW_RV64) NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
NODE_NAME_CASE(READ_CYCLE_WIDE) NODE_NAME_CASE(READ_CYCLE_WIDE)
NODE_NAME_CASE(GREVI) NODE_NAME_CASE(GREVI)
NODE_NAME_CASE(GREVIW) NODE_NAME_CASE(GREVIW)
NODE_NAME_CASE(GORCI) NODE_NAME_CASE(GORCI)
NODE_NAME_CASE(GORCIW) NODE_NAME_CASE(GORCIW)
NODE_NAME_CASE(VMV_V_X_VL)
NODE_NAME_CASE(VFMV_V_F_VL)
NODE_NAME_CASE(VMV_X_S) NODE_NAME_CASE(VMV_X_S)
NODE_NAME_CASE(SPLAT_VECTOR_I64) NODE_NAME_CASE(SPLAT_VECTOR_I64)
NODE_NAME_CASE(READ_VLENB) NODE_NAME_CASE(READ_VLENB)
NODE_NAME_CASE(TRUNCATE_VECTOR) NODE_NAME_CASE(TRUNCATE_VECTOR)
NODE_NAME_CASE(VLEFF) NODE_NAME_CASE(VLEFF)
NODE_NAME_CASE(VLEFF_MASK) NODE_NAME_CASE(VLEFF_MASK)
NODE_NAME_CASE(VSLIDEUP) NODE_NAME_CASE(VSLIDEUP)
NODE_NAME_CASE(VSLIDEDOWN) NODE_NAME_CASE(VSLIDEDOWN)
▲ Show 20 Lines • Show All 540 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

//===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===// //===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ///
/// This file contains the required infrastructure to support code generation /// This file contains the required infrastructure to support code generation
/// for the standard 'V' (Vector) extension, version 0.10. This version is still /// for the standard 'V' (Vector) extension, version 0.10. This version is still
/// experimental as the 'V' extension hasn't been ratified yet. /// experimental as the 'V' extension hasn't been ratified yet.
/// ///
/// This file is included from RISCVInstrInfoV.td /// This file is included from RISCVInstrInfoV.td
/// ///
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
SDTCisVT<1, XLenVT>,
SDTCisVT<2, XLenVT>]>>;
def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
SDTCisEltOfVec<1, 0>,
SDTCisVT<2, XLenVT>]>>;
def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>, SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
SDTCisInt<1>]>>; SDTCisInt<1>]>>;
def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
def riscv_vleff : SDNode<"RISCVISD::VLEFF", def riscv_vleff : SDNode<"RISCVISD::VLEFF",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>,
▲ Show 20 Lines • Show All 4,000 Lines • ▼ Show 20 Lines
foreach vti = AllVectors in { foreach vti = AllVectors in {
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1),
(XLenVT (VLOp GPR:$vl)))), (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
$rs1, GPR:$vl, vti.SEW)>; $rs1, GPR:$vl, vti.SEW)>;
} }
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (int_riscv_vmv_v_x GPR:$rs2, (XLenVT (VLOp GPR:$vl)))), def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
$rs2, GPR:$vl, vti.SEW)>; $rs2, GPR:$vl, vti.SEW)>;
def : Pat<(vti.Vector (int_riscv_vmv_v_x simm5:$imm5, (XLenVT (VLOp GPR:$vl)))), def : Pat<(vti.Vector (riscv_vmv_v_x_vl simm5:$imm5, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
simm5:$imm5, GPR:$vl, vti.SEW)>; simm5:$imm5, GPR:$vl, vti.SEW)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 13.1. Vector Single-Width Saturating Add and Subtract // 13.1. Vector Single-Width Saturating Add and Subtract
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>;
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$rs2),
(instr fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.SEW)>; (instr fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.SEW)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
// If we're splatting fpimm0, use vmv.v.x vd, x0. // If we're splatting fpimm0, use vmv.v.x vd, x0.
def : Pat<(fvti.Vector (int_riscv_vfmv_v_f def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Scalar (fpimm0)), (XLenVT (VLOp GPR:$vl)))), (fvti.Scalar (fpimm0)), (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
0, GPR:$vl, fvti.SEW)>; 0, GPR:$vl, fvti.SEW)>;
def : Pat<(fvti.Vector (int_riscv_vfmv_v_f def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Scalar fvti.ScalarRegClass:$rs2), (XLenVT (VLOp GPR:$vl)))), (fvti.Scalar fvti.ScalarRegClass:$rs2), (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
fvti.LMul.MX) fvti.LMul.MX)
(fvti.Scalar fvti.ScalarRegClass:$rs2), (fvti.Scalar fvti.ScalarRegClass:$rs2),
GPR:$vl, fvti.SEW)>; GPR:$vl, fvti.SEW)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
define void @splat_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: splat_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 16
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 %y, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @splat_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: splat_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 8
; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 %y, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @splat_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: splat_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 4
; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 %y, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %b, <4 x i32>* %x
ret void
}
; FIXME: Support i64 splats on riscv32
;define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
; %a = insertelement <2 x i64> undef, i64 %y, i32 0
; %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
; store <2 x i64> %b, <2 x i64>* %x
; ret void
;}
define void @splat_v32i8(<32 x i8>* %x, i8 %y) {
; LMULMAX2-LABEL: splat_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 16
; LMULMAX1-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse8.v v25, (a1)
; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 %y, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @splat_v16i16(<16 x i16>* %x, i16 %y) {
; LMULMAX2-LABEL: splat_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 16
; LMULMAX2-NEXT: vsetvli a2, a2, e16,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 8
; LMULMAX1-NEXT: vsetvli a2, a2, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 %y, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @splat_v8i32(<8 x i32>* %x, i32 %y) {
; LMULMAX2-LABEL: splat_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 8
; LMULMAX2-NEXT: vsetvli a2, a2, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 4
; LMULMAX1-NEXT: vsetvli a2, a2, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 %y, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
store <8 x i32> %b, <8 x i32>* %x
ret void
}
; FIXME: Support i64 splats on riscv32
;define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
; %a = insertelement <4 x i64> undef, i64 %y, i32 0
; %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
; store <4 x i64> %b, <4 x i64>* %x
; ret void
;}
define void @splat_zero_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: splat_zero_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 0, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @splat_zero_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: splat_zero_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 0, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @splat_zero_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: splat_zero_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 0, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @splat_zero_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: splat_zero_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 0, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @splat_zero_v32i8(<32 x i8>* %x) {
; LMULMAX2-LABEL: splat_zero_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 16
; LMULMAX1-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse8.v v25, (a1)
; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 0, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @splat_zero_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: splat_zero_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 16
; LMULMAX2-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 8
; LMULMAX1-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 0, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @splat_zero_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: splat_zero_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 4
; LMULMAX1-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 0, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @splat_zero_v4i64(<4 x i64>* %x) {
; LMULMAX2-LABEL: splat_zero_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 4
; LMULMAX1-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x i64> undef, i64 0, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
store <4 x i64> %b, <4 x i64>* %x
ret void
}
define void @splat_allones_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: splat_allones_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 -1, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @splat_allones_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: splat_allones_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 -1, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @splat_allones_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: splat_allones_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 -1, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @splat_allones_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: splat_allones_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 -1, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @splat_allones_v32i8(<32 x i8>* %x) {
; LMULMAX2-LABEL: splat_allones_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 16
; LMULMAX1-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse8.v v25, (a1)
; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 -1, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @splat_allones_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: splat_allones_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 16
; LMULMAX2-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 8
; LMULMAX1-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 -1, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @splat_allones_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: splat_allones_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 4
; LMULMAX1-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 -1, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @splat_allones_v4i64(<4 x i64>* %x) {
; LMULMAX2-LABEL: splat_allones_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 4
; LMULMAX1-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x i64> undef, i64 -1, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
store <4 x i64> %b, <4 x i64>* %x
ret void
}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
define void @splat_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: splat_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 16
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 %y, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @splat_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: splat_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 8
; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 %y, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @splat_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: splat_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 4
; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 %y, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
; CHECK-LABEL: splat_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 2
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vse64.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 %y, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @splat_v32i8(<32 x i8>* %x, i8 %y) {
; LMULMAX2-LABEL: splat_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 16
; LMULMAX1-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse8.v v25, (a1)
; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 %y, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @splat_v16i16(<16 x i16>* %x, i16 %y) {
; LMULMAX2-LABEL: splat_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 16
; LMULMAX2-NEXT: vsetvli a2, a2, e16,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 8
; LMULMAX1-NEXT: vsetvli a2, a2, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 %y, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @splat_v8i32(<8 x i32>* %x, i32 %y) {
; LMULMAX2-LABEL: splat_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 8
; LMULMAX2-NEXT: vsetvli a2, a2, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 4
; LMULMAX1-NEXT: vsetvli a2, a2, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 %y, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
; LMULMAX2-LABEL: splat_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 4
; LMULMAX2-NEXT: vsetvli a2, a2, e64,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vse64.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, zero, 2
; LMULMAX1-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.x v25, a1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse64.v v25, (a1)
; LMULMAX1-NEXT: vse64.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x i64> undef, i64 %y, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
store <4 x i64> %b, <4 x i64>* %x
ret void
}
define void @splat_zero_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: splat_zero_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 0, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @splat_zero_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: splat_zero_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 0, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @splat_zero_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: splat_zero_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 0, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @splat_zero_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: splat_zero_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 2
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vse64.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 0, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @splat_zero_v32i8(<32 x i8>* %x) {
; LMULMAX2-LABEL: splat_zero_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 16
; LMULMAX1-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse8.v v25, (a1)
; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 0, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @splat_zero_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: splat_zero_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 16
; LMULMAX2-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 8
; LMULMAX1-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 0, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @splat_zero_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: splat_zero_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 4
; LMULMAX1-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 0, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @splat_zero_v4i64(<4 x i64>* %x) {
; LMULMAX2-LABEL: splat_zero_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 4
; LMULMAX2-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vse64.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 2
; LMULMAX1-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse64.v v25, (a1)
; LMULMAX1-NEXT: vse64.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x i64> undef, i64 0, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
store <4 x i64> %b, <4 x i64>* %x
ret void
}
define void @splat_allones_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: splat_allones_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 16
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 -1, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
store <16 x i8> %b, <16 x i8>* %x
ret void
}
define void @splat_allones_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: splat_allones_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 -1, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
store <8 x i16> %b, <8 x i16>* %x
ret void
}
define void @splat_allones_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: splat_allones_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 4
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 -1, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %b, <4 x i32>* %x
ret void
}
define void @splat_allones_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: splat_allones_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 2
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vse64.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 -1, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
store <2 x i64> %b, <2 x i64>* %x
ret void
}
define void @splat_allones_v32i8(<32 x i8>* %x) {
; LMULMAX2-LABEL: splat_allones_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse8.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 16
; LMULMAX1-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse8.v v25, (a1)
; LMULMAX1-NEXT: vse8.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 -1, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
store <32 x i8> %b, <32 x i8>* %x
ret void
}
define void @splat_allones_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: splat_allones_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 16
; LMULMAX2-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse16.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 8
; LMULMAX1-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v25, (a1)
; LMULMAX1-NEXT: vse16.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 -1, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
store <16 x i16> %b, <16 x i16>* %x
ret void
}
define void @splat_allones_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: splat_allones_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 8
; LMULMAX2-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 4
; LMULMAX1-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: vse32.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 -1, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
store <8 x i32> %b, <8 x i32>* %x
ret void
}
define void @splat_allones_v4i64(<4 x i64>* %x) {
; LMULMAX2-LABEL: splat_allones_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 4
; LMULMAX2-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; LMULMAX2-NEXT: vmv.v.i v26, -1
; LMULMAX2-NEXT: vse64.v v26, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, zero, 2
; LMULMAX1-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v25, -1
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse64.v v25, (a1)
; LMULMAX1-NEXT: vse64.v v25, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x i64> undef, i64 -1, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
store <4 x i64> %b, <4 x i64>* %x
ret void
}