[RISCV] Use v8-v23 as argument registers to conform to the proposal.

[HsiangKai]

Summary

The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171

There are lots of test files need to be updated. It is too large to contain all of these test files in one commit to upload. I only add vadd test files to demonstrate the modification. If this patch is accepted, I will update all of these test files and commit them to the repository.

[kito-cheng]

Add a dedicated test file to demonstrate and verify the ABI would be better.

[craig.topper]

LGTM

[HsiangKai]

In D95134#2512496, @kito-cheng wrote:

Add a dedicated test file to demonstrate and verify the ABI would be better.

I would add test cases for ABI in D94465. In D94465, we could demonstrate how to pass vector arguments between caller and callee. In addition, we could show how to pass vector arguments through memory by reference.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static const MCPhysReg ArgFPR32s[] = {
   RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
 };
 static const MCPhysReg ArgFPR64s[] = {
   RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
   RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
 };
 // This is an interim calling convention and it may be changed in the future.
 static const MCPhysReg ArgVRs[] = {
-  RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20,
-  RISCV::V21, RISCV::V22, RISCV::V23
-};
-static const MCPhysReg ArgVRM2s[] = {
-  RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2
-};
-static const MCPhysReg ArgVRM4s[] = {RISCV::V16M4, RISCV::V20M4};
-static const MCPhysReg ArgVRM8s[] = {RISCV::V16M8};
+    RISCV::V8,  RISCV::V9,  RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
+    RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
+    RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23};
+static const MCPhysReg ArgVRM2s[] = {RISCV::V8M2,  RISCV::V10M2, RISCV::V12M2,
+                                     RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
+                                     RISCV::V20M2, RISCV::V22M2};
+static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
+                                     RISCV::V20M4};
+static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8};
 
 // Pass a 2*XLEN argument that has been split into two XLEN values through
 // registers or the stack as necessary.
 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
                                 ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
                                 MVT ValVT2, MVT LocVT2,
                                 ISD::ArgFlagsTy ArgFlags2) {
   unsigned XLenInBytes = XLen / 8;

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
 declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     <vscale x 1 x i8> %2,
     <vscale x 1 x i1> %3,
     i32 %4)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     <vscale x 2 x i8> %2,
     <vscale x 2 x i1> %3,
     i32 %4)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     <vscale x 4 x i8> %2,
     <vscale x 4 x i1> %3,
     i32 %4)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     <vscale x 8 x i8> %2,
     <vscale x 8 x i1> %3,
     i32 %4)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     <vscale x 16 x i8> %2,
     <vscale x 16 x i1> %3,
     i32 %4)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   i32);
 
 define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     i32 %2)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i32);
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     <vscale x 32 x i8> %2,
     <vscale x 32 x i1> %3,
     i32 %4)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   i32);
 
 define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     i32 %2)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   <vscale x 64 x i1>,
   i32);
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     <vscale x 64 x i8> %2,
     <vscale x 64 x i1> %3,
     i32 %4)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     <vscale x 1 x i16> %2,
     <vscale x 1 x i1> %3,
     i32 %4)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     <vscale x 2 x i16> %2,
     <vscale x 2 x i1> %3,
     i32 %4)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     <vscale x 4 x i16> %2,
     <vscale x 4 x i1> %3,
     i32 %4)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     <vscale x 8 x i16> %2,
     <vscale x 8 x i1> %3,
     i32 %4)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     <vscale x 16 x i16> %2,
     <vscale x 16 x i1> %3,
     i32 %4)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   i32);
 
 define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     i32 %2)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i32);
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     <vscale x 32 x i16> %2,
     <vscale x 32 x i1> %3,
     i32 %4)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     <vscale x 1 x i32> %2,
     <vscale x 1 x i1> %3,
     i32 %4)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     <vscale x 2 x i32> %2,
     <vscale x 2 x i1> %3,
     i32 %4)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     <vscale x 4 x i32> %2,
     <vscale x 4 x i1> %3,
     i32 %4)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     <vscale x 8 x i32> %2,
     <vscale x 8 x i1> %3,
     i32 %4)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     <vscale x 16 x i32> %2,
     <vscale x 16 x i1> %3,
     i32 %4)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
   <vscale x 1 x i8>,
   i8,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   i8,
   <vscale x 1 x i1>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     i8 %2,
     <vscale x 1 x i1> %3,
     i32 %4)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
   <vscale x 2 x i8>,
   i8,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   i8,
   <vscale x 2 x i1>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     i8 %2,
     <vscale x 2 x i1> %3,
     i32 %4)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
   <vscale x 4 x i8>,
   i8,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   i8,
   <vscale x 4 x i1>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     i8 %2,
     <vscale x 4 x i1> %3,
     i32 %4)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
   <vscale x 8 x i8>,
   i8,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   i8,
   <vscale x 8 x i1>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     i8 %2,
     <vscale x 8 x i1> %3,
     i32 %4)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
   <vscale x 16 x i8>,
   i8,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   i8,
   <vscale x 16 x i1>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     i8 %2,
     <vscale x 16 x i1> %3,
     i32 %4)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
   <vscale x 32 x i8>,
   i8,
   i32);
 
 define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   i8,
   <vscale x 32 x i1>,
   i32);
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     i8 %2,
     <vscale x 32 x i1> %3,
     i32 %4)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
   <vscale x 64 x i8>,
   i8,
   i32);
 
 define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     i8 %1,
     i32 %2)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   i8,
   <vscale x 64 x i1>,
   i32);
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     i8 %2,
     <vscale x 64 x i1> %3,
     i32 %4)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
   <vscale x 1 x i16>,
   i16,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   i16,
   <vscale x 1 x i1>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i16 %2,
     <vscale x 1 x i1> %3,
     i32 %4)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
   <vscale x 2 x i16>,
   i16,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   i16,
   <vscale x 2 x i1>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     i16 %2,
     <vscale x 2 x i1> %3,
     i32 %4)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
   <vscale x 4 x i16>,
   i16,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   i16,
   <vscale x 4 x i1>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     i16 %2,
     <vscale x 4 x i1> %3,
     i32 %4)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
   <vscale x 8 x i16>,
   i16,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   i16,
   <vscale x 8 x i1>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     i16 %2,
     <vscale x 8 x i1> %3,
     i32 %4)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
   <vscale x 16 x i16>,
   i16,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   i16,
   <vscale x 16 x i1>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     i16 %2,
     <vscale x 16 x i1> %3,
     i32 %4)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
   <vscale x 32 x i16>,
   i16,
   i32);
 
 define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 %1,
     i32 %2)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   i16,
   <vscale x 32 x i1>,
   i32);
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     i16 %2,
     <vscale x 32 x i1> %3,
     i32 %4)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
   <vscale x 1 x i32>,
   i32,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   i32,
   <vscale x 1 x i1>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i32 %2,
     <vscale x 1 x i1> %3,
     i32 %4)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
   <vscale x 2 x i32>,
   i32,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   i32,
   <vscale x 2 x i1>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     i32 %2,
     <vscale x 2 x i1> %3,
     i32 %4)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
   <vscale x 4 x i32>,
   i32,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   i32,
   <vscale x 4 x i1>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     i32 %2,
     <vscale x 4 x i1> %3,
     i32 %4)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
   <vscale x 8 x i32>,
   i32,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   i32,
   <vscale x 8 x i1>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     i32 %2,
     <vscale x 8 x i1> %3,
     i32 %4)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
   <vscale x 16 x i32>,
   i32,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     i32 %1,
     i32 %2)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   i32,
   <vscale x 16 x i1>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     i32 %2,
     <vscale x 16 x i1> %3,
     i32 %4)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     i8 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     i8 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     i8 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     i8 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     i8 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     i8 -9,
     <vscale x 32 x i1> %2,
     i32 %3)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, -9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     i8 -9,
     i32 %1)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     i8 -9,
     <vscale x 64 x i1> %2,
     i32 %3)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i16 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     i16 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     i16 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     i16 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     i16 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     i16 -9,
     <vscale x 32 x i1> %2,
     i32 %3)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i32 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     i32 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     i32 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     i32 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     i32 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i32> %a
 }

llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
 declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     <vscale x 1 x i8> %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     <vscale x 2 x i8> %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     <vscale x 4 x i8> %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     <vscale x 8 x i8> %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     <vscale x 16 x i8> %2,
     <vscale x 16 x i1> %3,
     i64 %4)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   i64);
 
 define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     i64 %2)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i64);
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     <vscale x 32 x i8> %2,
     <vscale x 32 x i1> %3,
     i64 %4)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   i64);
 
 define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     i64 %2)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   <vscale x 64 x i1>,
   i64);
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     <vscale x 64 x i8> %2,
     <vscale x 64 x i1> %3,
     i64 %4)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     <vscale x 1 x i16> %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     <vscale x 2 x i16> %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     <vscale x 4 x i16> %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     <vscale x 8 x i16> %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     <vscale x 16 x i16> %2,
     <vscale x 16 x i1> %3,
     i64 %4)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   i64);
 
 define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     i64 %2)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i64);
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     <vscale x 32 x i16> %2,
     <vscale x 32 x i1> %3,
     i64 %4)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     <vscale x 1 x i32> %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     <vscale x 2 x i32> %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     <vscale x 4 x i32> %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     <vscale x 8 x i32> %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     <vscale x 16 x i32> %2,
     <vscale x 16 x i1> %3,
     i64 %4)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64> %1,
     <vscale x 1 x i64> %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64> %1,
     <vscale x 2 x i64> %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64> %1,
     <vscale x 4 x i64> %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
   %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu
-; CHECK:       vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
   %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64> %1,
     <vscale x 8 x i64> %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i64> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
   <vscale x 1 x i8>,
   i8,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>,
   i8,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     i8 %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
   <vscale x 2 x i8>,
   i8,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>,
   i8,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     i8 %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
   <vscale x 4 x i8>,
   i8,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>,
   i8,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     i8 %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
   <vscale x 8 x i8>,
   i8,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>,
   i8,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     i8 %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
   <vscale x 16 x i8>,
   i8,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>,
   i8,
   <vscale x 16 x i1>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     i8 %2,
     <vscale x 16 x i1> %3,
     i64 %4)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
   <vscale x 32 x i8>,
   i8,
   i64);
 
 define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>,
   i8,
   <vscale x 32 x i1>,
   i64);
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     i8 %2,
     <vscale x 32 x i1> %3,
     i64 %4)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
   <vscale x 64 x i8>,
   i8,
   i64);
 
 define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     i8 %1,
     i64 %2)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>,
   i8,
   <vscale x 64 x i1>,
   i64);
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     i8 %2,
     <vscale x 64 x i1> %3,
     i64 %4)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
   <vscale x 1 x i16>,
   i16,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>,
   i16,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i16 %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
   <vscale x 2 x i16>,
   i16,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>,
   i16,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     i16 %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
   <vscale x 4 x i16>,
   i16,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>,
   i16,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     i16 %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
   <vscale x 8 x i16>,
   i16,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>,
   i16,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     i16 %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
   <vscale x 16 x i16>,
   i16,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>,
   i16,
   <vscale x 16 x i1>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     i16 %2,
     <vscale x 16 x i1> %3,
     i64 %4)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
   <vscale x 32 x i16>,
   i16,
   i64);
 
 define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 %1,
     i64 %2)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>,
   i16,
   <vscale x 32 x i1>,
   i64);
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     i16 %2,
     <vscale x 32 x i1> %3,
     i64 %4)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
   <vscale x 1 x i32>,
   i32,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>,
   i32,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i32 %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
   <vscale x 2 x i32>,
   i32,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>,
   i32,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     i32 %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
   <vscale x 4 x i32>,
   i32,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>,
   i32,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     i32 %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
   <vscale x 8 x i32>,
   i32,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>,
   i32,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     i32 %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
   <vscale x 16 x i32>,
   i32,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     i32 %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>,
   i32,
   <vscale x 16 x i1>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     i32 %2,
     <vscale x 16 x i1> %3,
     i64 %4)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
   <vscale x 1 x i64>,
   i64,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
     <vscale x 1 x i64> %0,
     i64 %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,
   i64,
   <vscale x 1 x i1>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64> %1,
     i64 %2,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
   <vscale x 2 x i64>,
   i64,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
     <vscale x 2 x i64> %0,
     i64 %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>,
   i64,
   <vscale x 2 x i1>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64> %1,
     i64 %2,
     <vscale x 2 x i1> %3,
     i64 %4)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
   <vscale x 4 x i64>,
   i64,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
     <vscale x 4 x i64> %0,
     i64 %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>,
   i64,
   <vscale x 4 x i1>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64> %1,
     i64 %2,
     <vscale x 4 x i1> %3,
     i64 %4)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
   <vscale x 8 x i64>,
   i64,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
   %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
     <vscale x 8 x i64> %0,
     i64 %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>,
   i64,
   <vscale x 8 x i1>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m8,tu,mu
+; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu
-; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
   %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64> %1,
     i64 %2,
     <vscale x 8 x i1> %3,
     i64 %4)
 
   ret <vscale x 8 x i64> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     i8 9,
     <vscale x 1 x i1> %2,
     i64 %3)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
     i8 9,
     <vscale x 2 x i1> %2,
     i64 %3)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
     i8 9,
     <vscale x 4 x i1> %2,
     i64 %3)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
     i8 9,
     <vscale x 8 x i1> %2,
     i64 %3)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
     i8 9,
     <vscale x 16 x i1> %2,
     i64 %3)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
     i8 9,
     <vscale x 32 x i1> %2,
     i64 %3)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
     i8 9,
     <vscale x 64 x i1> %2,
     i64 %3)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
     i16 9,
     <vscale x 1 x i1> %2,
     i64 %3)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
     i16 9,
     <vscale x 2 x i1> %2,
     i64 %3)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
     i16 9,
     <vscale x 4 x i1> %2,
     i64 %3)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
     i16 9,
     <vscale x 8 x i1> %2,
     i64 %3)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
     i16 9,
     <vscale x 16 x i1> %2,
     i64 %3)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
     i16 9,
     <vscale x 32 x i1> %2,
     i64 %3)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
     i32 9,
     <vscale x 1 x i1> %2,
     i64 %3)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
     i32 9,
     <vscale x 2 x i1> %2,
     i64 %3)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
     i32 9,
     <vscale x 4 x i1> %2,
     i64 %3)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
     i32 9,
     <vscale x 8 x i1> %2,
     i64 %3)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
     i32 9,
     <vscale x 16 x i1> %2,
     i64 %3)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
     <vscale x 1 x i64> %0,
     i64 9,
     i64 %1)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64> %1,
     i64 9,
     <vscale x 1 x i1> %2,
     i64 %3)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
     <vscale x 2 x i64> %0,
     i64 9,
     i64 %1)
 
   ret <vscale x 2 x i64> %a
 }
 
 define <vscale x 2 x i64> @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64> %1,
     i64 9,
     <vscale x 2 x i1> %2,
     i64 %3)
 
   ret <vscale x 2 x i64> %a
 }
 
 define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
     <vscale x 4 x i64> %0,
     i64 9,
     i64 %1)
 
   ret <vscale x 4 x i64> %a
 }
 
 define <vscale x 4 x i64> @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64> %1,
     i64 9,
     <vscale x 4 x i1> %2,
     i64 %3)
 
   ret <vscale x 4 x i64> %a
 }
 
 define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v8, v8, 9
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
     <vscale x 8 x i64> %0,
     i64 9,
     i64 %1)
 
   ret <vscale x 8 x i64> %a
 }
 
 define <vscale x 8 x i64> @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,tu,mu
+; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
   %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64> %1,
     i64 9,
     <vscale x 8 x i1> %2,
     i64 %3)
 
   ret <vscale x 8 x i64> %a
 }