[CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse

[CarolineConcatto]

Summary

This patch adds a new intrinsic experimental.vector.reduce that takes a single
vector and returns a vector of matching type but with the original lane order
reversed. For example:

vector.reverse(<A,B,C,D>) ==> <D,C,B,A>

The new intrinsic supports fixed and scalable vectors types.
The fixed-width vector relies on shufflevector to maintain existing behaviour.
Scalable vector uses the new ISD node - VECTOR_REVERSE.

This new intrinsic is one of the named shufflevector intrinsics proposed on the
mailing-list in the RFC at [1].

Patch by Paul Walker (@paulwalker-arm).

[1] https://lists.llvm.org/pipermail/llvm-dev/2020-November/146864.html

[craig.topper]

llvm/include/llvm/IR/Intrinsics.td

1640

Should this use DefaultAttrsIntrinsic?

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

99

Can we keep consistent formatting with the rest of this switch?

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

10858

Put VT.getVectorNumElements() in a variable since its used here and in the loop body.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

251–252

Why not put this in TargetSelectionDAG.td?

[david-arm]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

10848

I think we can drop the "experimental" here now?

10850

Perhaps worth explaining that we're using VECTOR_SHUFFLE to implement the VECTOR_REVERSE operation for fixed length vectors? It confused me a bit at first trying to understand why we jump suddenly into VECTOR_SHUFFLE that's all.

10856

VECTOR_REVERSE?

llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

293

I think this can just be "vector_reverse" because it's a generic opcode and not experimental?

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

5891

Just for reference, if all the lowering operation does is create the ISD_VECTOR_REVERSE with the same arguments then you can actually just mark the operation as Legal and avoid creating the LowerVECTOR_REVERSE function as it should happen automatically. If we have plans to use SVE for fixed length vectors in future then it might be useful to keep this custom function anyway.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

251–252

Yeah, I think you need to add something to llvm/include/llvm/Target/TargetSelectionDAG.td along the lines of

def vector_reverse : SDNode<"ISD::VECTOR_REVERSE",

SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>,[]>;

because you've added a generic ISD opcode in this patch. In places where you've got patterns using "AArch64rev" you can just then use "vector_reverse" instead.

[david-arm]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

10856

Sorry, ignore the comment above!

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

252

nit: whitespace

[CarolineConcatto]

-remove AArch64 custom lowering
-move SNode vector_reverse to TargetSelectionDAG.td

[CarolineConcatto]

-fix style on LegalizeIntegerTypes.cpp

[CarolineConcatto]

-fix table gen style for TargetSelectionDAG.td

[CarolineConcatto]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

10850

@david-arm
I've updated the commit message and the comments as well.
Is that good?

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

5891

Thank you @david-arm for pointing that.
It is true that we can remove the custom lowering for aarch64 and have it as legal.
This simplifies the code.

[david-arm]

LGTM!

[fhahn]

Mirroring my comments for D94708: if the intrinsics needs to support fixed vectors, it would be good to have some tests for platforms other than AArch64 and also support in GlobalISel, which is the default on AArch64 with -O0 IIRC (or do the transform to shuffles as an IR transform).

[david-arm]

In D94883#2512711, @fhahn wrote:

Mirroring my comments for D94708: if the intrinsics needs to support fixed vectors, it would be good to have some tests for platforms other than AArch64 and also support in GlobalISel, which is the default on AArch64 with -O0 IIRC (or do the transform to shuffles as an IR transform).

Hi @fhahn, I agree with your point about -O0, but I'm not sure why we need tests for other platforms? Carol has an extensive set of tests for both fixed width and scalable vectors. The lowering is identical for fixed width vectors regardless of the target so all it would be testing is the different codegen of vector shuffles.

[paulwalker-arm]

In D94883#2512892, @david-arm wrote:

In D94883#2512711, @fhahn wrote:

Mirroring my comments for D94708: if the intrinsics needs to support fixed vectors, it would be good to have some tests for platforms other than AArch64 and also support in GlobalISel, which is the default on AArch64 with -O0 IIRC (or do the transform to shuffles as an IR transform).

Hi @fhahn, I agree with your point about -O0, but I'm not sure why we need tests for other platforms? Carol has an extensive set of tests for both fixed width and scalable vectors. The lowering is identical for fixed width vectors regardless of the target so all it would be testing is the different codegen of vector shuffles.

I agree, such extra tests seem wasteful as I'd expect ISD::VECTOR_SHUFFLE to already be sufficiently tested for all targets.

[fhahn]

In D94883#2515074, @paulwalker-arm wrote:

In D94883#2512892, @david-arm wrote:

In D94883#2512711, @fhahn wrote:

Mirroring my comments for D94708: if the intrinsics needs to support fixed vectors, it would be good to have some tests for platforms other than AArch64 and also support in GlobalISel, which is the default on AArch64 with -O0 IIRC (or do the transform to shuffles as an IR transform).

Hi @fhahn, I agree with your point about -O0, but I'm not sure why we need tests for other platforms? Carol has an extensive set of tests for both fixed width and scalable vectors. The lowering is identical for fixed width vectors regardless of the target so all it would be testing is the different codegen of vector shuffles.

I agree, such extra tests seem wasteful as I'd expect ISD::VECTOR_SHUFFLE to already be sufficiently tested for all targets.

Given the current implementation details that's true, but the implementation could change and having a few tests for other targets guards against the implementation changing in a way that makes it only work on a certain target for example. I'm not saying that is very likely, but something like that could get missed as backends transition to GlobalISel at different times, for example.

I'm not saying we need extensive tests for all targets, just suggesting to add a small sanity test for a different commonly used backend, like X86. Adding such a test seems cheap, but please feel free to ignore the suggestion.

Taking a step back, are there plans to use the intrinsics for fixed vectors?

[paulwalker-arm]

In D94883#2515136, @fhahn wrote:

Taking a step back, are there plans to use the intrinsics for fixed vectors?

I'd like to say yes but at this stage it is too early to say. What we definitely need is a unified interface so that transforms can be written without needing to worry about the type of vector. If a pass uses an IRBuilder then great, we can hide the "do I create a shufflevector or intrinsic" code behind suitably names functions (e.g. craeteVectorSplice()...). For passes that want to create a node directly then we'd recommend just creating an intrinsic call with the expectation that those working with fixed length vectors are transformed to shufflevector sufficiently early to maintain existing code quality.

Once we're at a stage where the expected shuffle optimisations apply equally well to the intrinsic variants, there's consensus of how LLVM will represent step vector like constants and ultimately the final decision on if/how shufflevector can operate on scalable vectors, we should be in a position to determine whether it is worth unifying shuffles paths (i.e. minimise the use of shufflevector).

Just an extra note to say that whilst the above is true for the intrinsics, it doesn't necessarily hold for the ISD nodes, where I believe the common case will be to rely on VECTOR_SHUFFLE to implement the vector intrinsics that operate on fixed length vectors.

[CarolineConcatto]

-add -O0 and X86 test for vector.reverse

[CarolineConcatto]

Thank you all for the comments.
I've added tests for -O0 in AArch64 and fixed-width test for X86.
ATM the X86 test has no specific target feature.

[craig.topper]

llvm/test/CodeGen/X86/named-vector-shuffles.ll

65 ↗

(On Diff #319320)

You can probably drop this. Vectors of f16 aren't legal on X86.

[fhahn]

In D94883#2518090, @paulwalker-arm wrote:

In D94883#2515136, @fhahn wrote:

Taking a step back, are there plans to use the intrinsics for fixed vectors?

I'd like to say yes but at this stage it is too early to say. What we definitely need is a unified interface so that transforms can be written without needing to worry about the type of vector. If a pass uses an IRBuilder then great, we can hide the "do I create a shufflevector or intrinsic" code behind suitably names functions (e.g. craeteVectorSplice()...). For passes that want to create a node directly then we'd recommend just creating an intrinsic call with the expectation that those working with fixed length vectors are transformed to shufflevector sufficiently early to maintain existing code quality.

Hm, making things slightly easier for passes not using IRBuilder doesn't seem like the strongest motivation to me, especially if it also comes with new pass ordering constraints (doing the conversion during instruction selection seems like it would mean we potentially miss existing folds in InstCombine & co). Also, even if passes not using IRBuilder, creating an intrinsic call without it is probably more work than just instantiating IRBuilder and using it directly?

It seems to me like only allowing them for scalable vectors initially would define away a couple of potential problems (like introducing new pass-ordering constraints, uncertainty whether to use shuffle vector or the intrinsics). Personally I'd prefer one way of doing things rather than having to chose whether to use an intrinsic or a shuffle for fixed vectors. If it is uncertain whether the intrinsic will actually be used for fixed vectors, having it first restricted to the actual use case (scalable vectors) and extend it to fixed vectors once it is needed seems like a slightly more incremental/conservative approach.

But if others think having them for fixed with vectors is useful, that's fine by me, especially because they are still experimental and we can remove fixed vector support again if it is not used.

[CarolineConcatto]

-remove test for f16 on X86 as they are not legal.

[CarolineConcatto]

llvm/test/CodeGen/X86/named-vector-shuffles.ll

65 ↗

(On Diff #319320)

Thank you @craig.topper. I've removed the test for f16 tests on X86

[sdesmalen]

In D94883#2524665, @fhahn wrote:

It seems to me like only allowing them for scalable vectors initially would define away a couple of potential problems (like introducing new pass-ordering constraints, uncertainty whether to use shuffle vector or the intrinsics). Personally I'd prefer one way of doing things rather than having to chose whether to use an intrinsic or a shuffle for fixed vectors. If it is uncertain whether the intrinsic will actually be used for fixed vectors, having it first restricted to the actual use case (scalable vectors) and extend it to fixed vectors once it is needed seems like a slightly more incremental/conservative approach.

But if others think having them for fixed with vectors is useful, that's fine by me, especially because they are still experimental and we can remove fixed vector support again if it is not used.

While these intrinsics are marked experimental they probably shouldn't be created for fixed-width vectors by passes or front-ends until we have a better understanding what direction to take for shuffles. At the same time, the name doesn't suggest the intrinsic is limited to scalable-vectors only, and it is quite trivial to make this work for fixed-width vectors, so I don't see a reason not to support this. Perhaps the LangRef description can mention this consideration?

llvm/docs/LangRef.rst

16246

nxv4i32

16254

Maybe add:

These intrinsics work for both fixed and scalable vectors. While this intrinsic is marked as experimental the recommended way to express reverse operations for fixed-width vectors is still to use a shufflevector, as that may allow for more optimization opportunities.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

10850–10852

nit: remove comment.

10859

nit: s/behaviours/behavior/

llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

1 ↗

(On Diff #319807)

nit: can you rename this file (and the one for neon and x86) to: named-vector-shuffle-reverse-sve.ll, named-vector-shuffle-reverse-neon.ll and named-vector-shuffle-reverse.ll respectively?

[CarolineConcatto]

-change the names of the tests to named-vector-shuffle-reverse
-add text in LangRef about the use of experimental.vector.reverse

[sdesmalen]

Cheers, it looks good to me now!

[fhahn]

In D94883#2553696, @sdesmalen wrote:

In D94883#2524665, @fhahn wrote:

It seems to me like only allowing them for scalable vectors initially would define away a couple of potential problems (like introducing new pass-ordering constraints, uncertainty whether to use shuffle vector or the intrinsics). Personally I'd prefer one way of doing things rather than having to chose whether to use an intrinsic or a shuffle for fixed vectors. If it is uncertain whether the intrinsic will actually be used for fixed vectors, having it first restricted to the actual use case (scalable vectors) and extend it to fixed vectors once it is needed seems like a slightly more incremental/conservative approach.

But if others think having them for fixed with vectors is useful, that's fine by me, especially because they are still experimental and we can remove fixed vector support again if it is not used.

While these intrinsics are marked experimental they probably shouldn't be created for fixed-width vectors by passes or front-ends until we have a better understanding what direction to take for shuffles. At the same time, the name doesn't suggest the intrinsic is limited to scalable-vectors only, and it is quite trivial to make this work for fixed-width vectors, so I don't see a reason not to support this. Perhaps the LangRef description can mention this consideration?

Making it explicit in the langref sounds good to me, thanks!

LGTM.

[paulwalker-arm]

One minor issue that can be fixed when merging.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

293

Stylistically this should be on the same line as the case to match all the other entries, even those with longer names.

llvm/docs/LangRef.rst

 vector length of the result type. If the result type is a scalable vector,
 ``idx`` is first scaled by the result type's runtime scaling factor. Elements
 ``idx`` through (``idx`` + num_elements(result_type) - 1) must be valid vector
 indices. If this condition cannot be determined statically but is false at
 runtime, then the result vector is undefined. The ``idx`` parameter must be a
 vector index constant type (for most targets this will be an integer pointer
 type).
 
+'``llvm.experimental.vector.reverse``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic.
+
+::
+
+      declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
+      declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
+
+Overview:
+"""""""""
+
+The '``llvm.experimental.vector.reverse.*``' intrinsics reverse a vector.
+The intrinsic takes a single vector and returns a vector of matching type but
+with the original lane order reversed. These intrinsics work for both fixed
+and scalable vectors. While this intrinsic is marked as experimental the
+recommended way to express reverse operations for fixed-width vectors is still
+to use a shufflevector, as that may allow for more optimization opportunities.
+
+Arguments:
+""""""""""
+
+The argument to this intrinsic must be a vector.
+
 Matrix Intrinsics
 -----------------
 
 Operations on matrixes requiring shape information (like number of rows/columns
 or the memory layout) can be expressed using the matrix intrinsics. These
 intrinsics require matrix dimensions to be passed as immediate arguments, and
 matrixes are passed and returned as vectors. This means that for a ``R`` x
 ``C`` matrix, element ``i`` of column ``j`` is at index ``j * R + i`` in the

llvm/include/llvm/CodeGen/ISDOpcodes.h

enum NodeType {
   /// condition cannot be determined statically but is false at runtime, then
   /// the result vector is undefined. The IDX parameter must be a vector index
   /// constant type, which for most targets will be an integer pointer type.
   ///
   /// This operation supports extracting a fixed-width vector from a scalable
   /// vector, but not the other way around.
   EXTRACT_SUBVECTOR,
 
+  /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR,
+  /// whose elements are shuffled using the following algorithm:
+  ///   RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i]
+  VECTOR_REVERSE,
+
   /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
   /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of constant int
   /// values that indicate which value (or undef) each result element will
   /// get.  These constant ints are accessible through the
   /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
   /// 'vperm' instruction, except that the indices must be constants and are
   /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
   VECTOR_SHUFFLE,

llvm/include/llvm/IR/Intrinsics.td

def int_preserve_union_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                                  ImmArg<ArgIndex<1>>]>;
 def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                                  [llvm_anyptr_ty, llvm_i32_ty,
                                                   llvm_i32_ty],
                                                  [IntrNoMem,
                                                   ImmArg<ArgIndex<1>>,
                                                   ImmArg<ArgIndex<2>>]>;
 
+//===------------ Intrinsics to perform common vector shuffles ------------===//
+
+def int_experimental_vector_reverse : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                                   [LLVMMatchType<0>],
+                                   [IntrNoMem]>;
+
 //===---------- Intrinsics to query properties of scalable vectors --------===//
 def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
 
 //===---------- Intrinsics to perform subvector insertion/extraction ------===//
 def int_experimental_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                                                            [LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty],
                                                            [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 

llvm/include/llvm/Target/TargetSelectionDAG.td

 ]>;
 def SDTVecReduce : SDTypeProfile<1, 1, [    // vector reduction
   SDTCisInt<0>, SDTCisVec<1>
 ]>;
 def SDTFPVecReduce : SDTypeProfile<1, 1, [  // FP vector reduction
   SDTCisFP<0>, SDTCisVec<1>
 ]>;
 
+def SDTVecReverse : SDTypeProfile<1, 1, [  // vector reverse
+  SDTCisVec<0>, SDTCisSameAs<0,1>
+]>;
 
 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
   SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
 ]>;
 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
   SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
 ]>;
 

 def ld         : SDNode<"ISD::LOAD"       , SDTLoad,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def st         : SDNode<"ISD::STORE"      , SDTStore,
                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def ist        : SDNode<"ISD::STORE"      , SDTIStore,
                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
+def vector_reverse : SDNode<"ISD::VECTOR_REVERSE", SDTVecReverse>;
 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
                               []>;
 
 // vector_extract/vector_insert are deprecated. extractelt/insertelt
 // are preferred.
 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",

llvm/lib/Analysis/InstructionSimplify.cpp

case Intrinsic::rint: {
     //
     // Converting from int always results in a finite integral number or
     // infinity. For either of those inputs, these rounding functions always
     // return the same value, so the rounding can be eliminated.
     if (match(Op0, m_SIToFP(m_Value())) || match(Op0, m_UIToFP(m_Value())))
       return Op0;
     break;
   }
+  case Intrinsic::experimental_vector_reverse:
+    // experimental.vector.reverse(experimental.vector.reverse(x)) -> x
+    if (match(Op0,
+              m_Intrinsic<Intrinsic::experimental_vector_reverse>(m_Value(X))))
+      return X;
+    break;
   default:
     break;
   }
 
   return nullptr;
 }
 
 static Intrinsic::ID getMaxMinOpposite(Intrinsic::ID IID) {

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

#endif
   case ISD::SRL:         Res = PromoteIntRes_SRL(N); break;
   case ISD::TRUNCATE:    Res = PromoteIntRes_TRUNCATE(N); break;
   case ISD::UNDEF:       Res = PromoteIntRes_UNDEF(N); break;
   case ISD::VAARG:       Res = PromoteIntRes_VAARG(N); break;
   case ISD::VSCALE:      Res = PromoteIntRes_VSCALE(N); break;
 
   case ISD::EXTRACT_SUBVECTOR:
                          Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
+  case ISD::VECTOR_REVERSE:
+                         Res = PromoteIntRes_VECTOR_REVERSE(N); break;
   case ISD::VECTOR_SHUFFLE:
                          Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
   case ISD::INSERT_VECTOR_ELT:
                          Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
   case ISD::BUILD_VECTOR:
                          Res = PromoteIntRes_BUILD_VECTOR(N); break;
   case ISD::SCALAR_TO_VECTOR:
                          Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
for (unsigned i = 0; i != OutNumElems; ++i) {
     SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem);
     // Insert the converted element to the new vector.
     Ops.push_back(Op);
   }
 
   return DAG.getBuildVector(NOutVT, dl, Ops);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
+  SDLoc dl(N);
+
+  SDValue V0 = GetPromotedInteger(N->getOperand(0));
+  EVT OutVT = V0.getValueType();
+
+  return DAG.getNode(ISD::VECTOR_REVERSE, dl, OutVT, V0);
+}
 
 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
   ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
   EVT VT = N->getValueType(0);
   SDLoc dl(N);
 
   ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
 

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   void PromoteIntegerResult(SDNode *N, unsigned ResNo);
   SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
   SDValue PromoteIntRes_AssertSext(SDNode *N);
   SDValue PromoteIntRes_AssertZext(SDNode *N);
   SDValue PromoteIntRes_Atomic0(AtomicSDNode *N);
   SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
   SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
   SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
+  SDValue PromoteIntRes_VECTOR_REVERSE(SDNode *N);
   SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
   SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
   SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
   SDValue PromoteIntRes_SPLAT_VECTOR(SDNode *N);
   SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
   SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
   SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
   SDValue PromoteIntRes_BITCAST(SDNode *N);
private:
   void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_ScalarOp(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
+  void SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
                                   SDValue &Hi);
   void SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi);
   void SplitVecRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo, SDValue &Hi);
 
   // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
   bool SplitVectorOperand(SDNode *N, unsigned OpNo);
   SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo);

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

case ISD::MLOAD:
     SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
     break;
   case ISD::MGATHER:
     SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
     break;
   case ISD::SETCC:
     SplitVecRes_SETCC(N, Lo, Hi);
     break;
+  case ISD::VECTOR_REVERSE:
+    SplitVecRes_VECTOR_REVERSE(N, Lo, Hi);
+    break;
   case ISD::VECTOR_SHUFFLE:
     SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
     break;
   case ISD::VAARG:
     SplitVecRes_VAARG(N, Lo, Hi);
     break;
 
   case ISD::ANY_EXTEND_VECTOR_INREG:
Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
                            DAG.getVectorIdxConstant(Idx, dl));
 
   SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
     DAG.getUNDEF(EltVT);
   for ( ; Idx < WidenNumElts; ++Idx)
     Ops[Idx] = FillVal;
   return DAG.getBuildVector(NVT, dl, Ops);
 }
+
+void DAGTypeLegalizer::SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo,
+                                                  SDValue &Hi) {
+  SDValue InLo, InHi;
+  GetSplitVector(N->getOperand(0), InLo, InHi);
+  SDLoc DL(N);
+
+  Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, InHi.getValueType(), InHi);
+  Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, InLo.getValueType(), InLo);
+}

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

private:
   void visitStackmap(const CallInst &I);
   void visitPatchpoint(const CallBase &CB, const BasicBlock *EHPadBB = nullptr);
 
   // These two are implemented in StatepointLowering.cpp
   void visitGCRelocate(const GCRelocateInst &Relocate);
   void visitGCResult(const GCResultInst &I);
 
   void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
+  void visitVectorReverse(const CallInst &I);
 
   void visitUserOp1(const Instruction &I) {
     llvm_unreachable("UserOp1 should not exist at instruction selection time!");
   }
   void visitUserOp2(const Instruction &I) {
     llvm_unreachable("UserOp2 should not exist at instruction selection time!");
   }
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::experimental_vector_extract: {
 
     SDValue Vec = getValue(I.getOperand(0));
     SDValue Index = getValue(I.getOperand(1));
     EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
 
     setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index));
     return;
   }
+  case Intrinsic::experimental_vector_reverse:
+    visitVectorReverse(I);
+    return;
   }
 }
 
 void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
     const ConstrainedFPIntrinsic &FPI) {
   SDLoc sdl = getCurSDLoc();
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
       splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
       continue;
     }
 
     lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);
   }
 }
 
+void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) {
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
+
+  SDLoc DL = getCurSDLoc();
+  SDValue V = getValue(I.getOperand(0));
+  assert(VT == V.getValueType() && "Malformed vector.reverse!");
+
+  if (VT.isScalableVector()) {
+    setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V));
+    return;
+  }
+
+  // Use VECTOR_SHUFFLE for the fixed-length vector
+  // to maintain existing behavior.
+  SmallVector<int, 8> Mask;
+  unsigned NumElts = VT.getVectorMinNumElements();
+  for (unsigned i = 0; i != NumElts; ++i)
+    Mask.push_back(NumElts - 1 - i);
+
+  setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask));
+}
+
 void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
   SmallVector<EVT, 4> ValueVTs;
   ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
                   ValueVTs);
   unsigned NumValues = ValueVTs.size();
   if (NumValues == 0) return;
 
   SmallVector<SDValue, 4> Values(NumValues);

llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

#endif
   case ISD::INSERT_VECTOR_ELT:          return "insert_vector_elt";
   case ISD::EXTRACT_VECTOR_ELT:         return "extract_vector_elt";
   case ISD::CONCAT_VECTORS:             return "concat_vectors";
   case ISD::INSERT_SUBVECTOR:           return "insert_subvector";
   case ISD::EXTRACT_SUBVECTOR:          return "extract_subvector";
   case ISD::SCALAR_TO_VECTOR:           return "scalar_to_vector";
   case ISD::VECTOR_SHUFFLE:             return "vector_shuffle";
   case ISD::SPLAT_VECTOR:               return "splat_vector";
+  case ISD::VECTOR_REVERSE:             return "vector_reverse";
   case ISD::CARRY_FALSE:                return "carry_false";
   case ISD::ADDC:                       return "addc";
   case ISD::ADDE:                       return "adde";
   case ISD::ADDCARRY:                   return "addcarry";
   case ISD::SADDO_CARRY:                return "saddo_carry";
   case ISD::SADDO:                      return "saddo";
   case ISD::UADDO:                      return "uaddo";
   case ISD::SSUBO:                      return "ssubo";
   case ISD::USUBO:                      return "usubo";

llvm/lib/Target/AArch64/AArch64FastISel.cpp

if (Ret->getNumOperands() > 0) {
     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
       return false;
 
     EVT RVEVT = TLI.getValueType(DL, RV->getType());
     if (!RVEVT.isSimple())
       return false;
 
     // Vectors (of > 1 lane) in big endian need tricky handling.
-    if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
+    if (RVEVT.isVector() && RVEVT.getVectorElementCount().isVector() &&
         !Subtarget->isLittleEndian())
       return false;
 
     MVT RVVT = RVEVT.getSimpleVT();
     if (RVVT == MVT::f128)
       return false;
 
     MVT DestVT = VA.getValVT();

llvm/lib/Target/AArch64/AArch64ISelLowering.h

enum NodeType : unsigned {
   SUNPKLO,
   UUNPKHI,
   UUNPKLO,
 
   CLASTA_N,
   CLASTB_N,
   LASTA,
   LASTB,
-  REV,
   TBL,
 
   // Floating-point reductions.
   FADDA_PRED,
   FADDV_PRED,
   FMAXV_PRED,
   FMAXNMV_PRED,
   FMINV_PRED,

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case AArch64ISD::FIRST_NUMBER:
     MAKE_CASE(AArch64ISD::UMINV_PRED)
     MAKE_CASE(AArch64ISD::ORV_PRED)
     MAKE_CASE(AArch64ISD::EORV_PRED)
     MAKE_CASE(AArch64ISD::ANDV_PRED)
     MAKE_CASE(AArch64ISD::CLASTA_N)
     MAKE_CASE(AArch64ISD::CLASTB_N)
     MAKE_CASE(AArch64ISD::LASTA)
     MAKE_CASE(AArch64ISD::LASTB)
-    MAKE_CASE(AArch64ISD::REV)
     MAKE_CASE(AArch64ISD::REINTERPRET_CAST)
     MAKE_CASE(AArch64ISD::TBL)
     MAKE_CASE(AArch64ISD::FADD_PRED)
     MAKE_CASE(AArch64ISD::FADDA_PRED)
     MAKE_CASE(AArch64ISD::FADDV_PRED)
     MAKE_CASE(AArch64ISD::FDIV_PRED)
     MAKE_CASE(AArch64ISD::FMA_PRED)
     MAKE_CASE(AArch64ISD::FMAXV_PRED)
return DAG.getNode(AArch64ISD::CLASTB_N, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
   case Intrinsic::aarch64_sve_lasta:
     return DAG.getNode(AArch64ISD::LASTA, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_sve_lastb:
     return DAG.getNode(AArch64ISD::LASTB, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_sve_rev:
-    return DAG.getNode(AArch64ISD::REV, dl, Op.getValueType(),
+    return DAG.getNode(ISD::VECTOR_REVERSE, dl, Op.getValueType(),
                        Op.getOperand(1));
   case Intrinsic::aarch64_sve_tbl:
     return DAG.getNode(AArch64ISD::TBL, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_sve_trn1:
     return DAG.getNode(AArch64ISD::TRN1, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_sve_trn2:
SDValue AArch64TargetLowering::getAddrTiny(NodeTy *N, SelectionDAG &DAG,
                                            unsigned Flags) const {
   LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrTiny\n");
   SDLoc DL(N);
   EVT Ty = getPointerTy(DAG.getDataLayout());
   SDValue Sym = getTargetNode(N, Ty, DAG, Flags);
   return DAG.getNode(AArch64ISD::ADR, DL, Ty, Sym);
 }
 
 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
                                                   SelectionDAG &DAG) const {
   GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
   const GlobalValue *GV = GN->getGlobal();
   unsigned OpFlags = Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
 
   if (OpFlags != AArch64II::MO_NO_FLAG)
     assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
            "unexpected offset in global node");

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 def AArch64scvtf_mt  : SDNode<"AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU", SDT_AArch64FCVT>;
 def AArch64fcvtzu_mt : SDNode<"AArch64ISD::FCVTZU_MERGE_PASSTHRU", SDT_AArch64FCVT>;
 def AArch64fcvtzs_mt : SDNode<"AArch64ISD::FCVTZS_MERGE_PASSTHRU", SDT_AArch64FCVT>;
 
 def SDT_AArch64ReduceWithInit : SDTypeProfile<1, 3, [SDTCisVec<1>, SDTCisVec<3>]>;
 def AArch64clasta_n   : SDNode<"AArch64ISD::CLASTA_N",   SDT_AArch64ReduceWithInit>;
 def AArch64clastb_n   : SDNode<"AArch64ISD::CLASTB_N",   SDT_AArch64ReduceWithInit>;
 def AArch64fadda_p    : SDNode<"AArch64ISD::FADDA_PRED", SDT_AArch64ReduceWithInit>;
 
-def SDT_AArch64Rev   : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
-def AArch64rev       : SDNode<"AArch64ISD::REV", SDT_AArch64Rev>;
-
 def SDT_AArch64PTest : SDTypeProfile<0, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 def AArch64ptest     : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
 
 def SDT_AArch64DUP_PRED  : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 3>, SDTCisVec<1>, SDTCVecEltisVT<1,i1>]>;
 def AArch64dup_mt : SDNode<"AArch64ISD::DUP_MERGE_PASSTHRU", SDT_AArch64DUP_PRED>;
 
 def SDT_IndexVector : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<2>]>;
 def index_vector : SDNode<"AArch64ISD::INDEX_VECTOR", SDT_IndexVector, []>;
 
let Predicates = [HasSVE] in {
   defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
   defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext>;
 
   defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", AArch64rbit_mt>;
   defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", AArch64revb_mt>;
   defm REVH_ZPmZ : sve_int_perm_rev_revh<"revh", int_aarch64_sve_revh>;
   defm REVW_ZPmZ : sve_int_perm_rev_revw<"revw", int_aarch64_sve_revw>;
 
-  defm REV_PP : sve_int_perm_reverse_p<"rev", AArch64rev>;
-  defm REV_ZZ : sve_int_perm_reverse_z<"rev", AArch64rev>;
+  defm REV_PP : sve_int_perm_reverse_p<"rev", vector_reverse>;
+  defm REV_ZZ : sve_int_perm_reverse_z<"rev", vector_reverse>;
 
   defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo", AArch64sunpklo>;
   defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi", AArch64sunpkhi>;
   defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo", AArch64uunpklo>;
   defm UUNPKHI_ZZ : sve_int_perm_unpk<0b11, "uunpkhi", AArch64uunpkhi>;
 
   defm PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo", int_aarch64_sve_punpklo>;
   defm PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi", int_aarch64_sve_punpkhi>;

llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs  < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SELDAG  %s
+; RUN: llc -verify-machineinstrs -O0 < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FASTISEL %s
+
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; VECTOR_REVERSE
+;
+
+define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
+; CHECK-LABEL: .LCPI0_0:
+; CHECK:        .byte   15                      // 0xf
+; CHECK-NEXT:   .byte   14                      // 0xe
+; CHECK-NEXT:   .byte   13                      // 0xd
+; CHECK-NEXT:   .byte   12                      // 0xc
+; CHECK-NEXT:   .byte   11                      // 0xb
+; CHECK-NEXT:   .byte   10                      // 0xa
+; CHECK-NEXT:   .byte   9                       // 0x9
+; CHECK-NEXT:   .byte   8                       // 0x8
+; CHECK-NEXT:   .byte   7                       // 0x7
+; CHECK-NEXT:   .byte   6                       // 0x6
+; CHECK-NEXT:   .byte   5                       // 0x5
+; CHECK-NEXT:   .byte   4                       // 0x4
+; CHECK-NEXT:   .byte   3                       // 0x3
+; CHECK-NEXT:   .byte   2                       // 0x2
+; CHECK-NEXT:   .byte   1                       // 0x1
+; CHECK-NEXT:   .byte   0                       // 0x0
+; CHECK-LABEL: reverse_v16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI0_0
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT:    ret
+
+  %res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a)
+  ret <16 x i8> %res
+}
+
+define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
+; CHECK-LABEL: .LCPI1_0:
+; CHECK:        .byte   14                      // 0xe
+; CHECK-NEXT:   .byte   15                      // 0xf
+; CHECK-NEXT:   .byte   12                      // 0xc
+; CHECK-NEXT:   .byte   13                      // 0xd
+; CHECK-NEXT:   .byte   10                      // 0xa
+; CHECK-NEXT:   .byte   11                      // 0xb
+; CHECK-NEXT:   .byte   8                       // 0x8
+; CHECK-NEXT:   .byte   9                       // 0x9
+; CHECK-NEXT:   .byte   6                       // 0x6
+; CHECK-NEXT:   .byte   7                       // 0x7
+; CHECK-NEXT:   .byte   4                       // 0x4
+; CHECK-NEXT:   .byte   5                       // 0x5
+; CHECK-NEXT:   .byte   2                       // 0x2
+; CHECK-NEXT:   .byte   3                       // 0x3
+; CHECK-NEXT:   .byte   0                       // 0x0
+; CHECK-NEXT:   .byte   1                       // 0x1
+; CHECK-LABEL: reverse_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI1_0
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
+; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT:    ret
+
+  %res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
+  ret <8 x i16> %res
+}
+
+define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
+; CHECK-LABEL: reverse_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev64 v0.4s, v0.4s
+; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    ret
+
+  %res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
+  ret <4 x i32> %res
+}
+
+define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
+; CHECK-LABEL: reverse_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    ret
+
+  %res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
+  ret <2 x i64> %res
+}
+
+define <8 x half> @reverse_v8f16(<8 x half> %a) #0 {
+; CHECK-LABEL: .LCPI4_0:
+; CHECK:        .byte   14                      // 0xe
+; CHECK-NEXT:   .byte   15                      // 0xf
+; CHECK-NEXT:   .byte   12                      // 0xc
+; CHECK-NEXT:   .byte   13                      // 0xd
+; CHECK-NEXT:   .byte   10                      // 0xa
+; CHECK-NEXT:   .byte   11                      // 0xb
+; CHECK-NEXT:   .byte   8                       // 0x8
+; CHECK-NEXT:   .byte   9                       // 0x9
+; CHECK-NEXT:   .byte   6                       // 0x6
+; CHECK-NEXT:   .byte   7                       // 0x7
+; CHECK-NEXT:   .byte   4                       // 0x4
+; CHECK-NEXT:   .byte   5                       // 0x5
+; CHECK-NEXT:   .byte   2                       // 0x2
+; CHECK-NEXT:   .byte   3                       // 0x3
+; CHECK-NEXT:   .byte   0                       // 0x0
+; CHECK-NEXT:   .byte   1                       // 0x1
+; CHECK-LABEL: reverse_v8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI4_0
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
+; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT:    ret
+
+  %res = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> %a)
+  ret <8 x half> %res
+}
+
+define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
+; CHECK-LABEL: reverse_v4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev64 v0.4s, v0.4s
+; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    ret
+
+  %res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
+  ret <4 x float> %res
+}
+
+define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
+; CHECK-LABEL: reverse_v2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    ret
+
+  %res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
+  ret <2 x double> %res
+}
+
+; Verify promote type legalisation works as expected.
+define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
+; CHECK-LABEL: reverse_v2i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev64 v0.2s, v0.2s
+; CHECK-NEXT:    ret
+
+  %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
+  ret <2 x i8> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
+; CHECK-LABEL: reverse_v8i32:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    rev64 v1.4s, v1.4s
+; CHECK-SELDAG-NEXT:    rev64 v2.4s, v0.4s
+; CHECK-SELDAG-NEXT:    ext v0.16b, v1.16b, v1.16b, #8
+; CHECK-SELDAG-NEXT:    ext v1.16b, v2.16b, v2.16b, #8
+; CHECK-SELDAG-NEXT:    ret
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    sub    sp, sp, #16
+; CHECK-FASTISEL-NEXT:    str    q1, [sp]
+; CHECK-FASTISEL-NEXT:    mov    v1.16b, v0.16b
+; CHECK-FASTISEL-NEXT:    ldr    q0, [sp]
+; CHECK-FASTISEL-NEXT:    rev64    v0.4s, v0.4s
+; CHECK-FASTISEL-NEXT:    ext    v0.16b, v0.16b, v0.16b, #8
+; CHECK-FASTISEL-NEXT:    rev64    v1.4s, v1.4s
+; CHECK-FASTISEL-NEXT:    ext    v1.16b, v1.16b, v1.16b, #8
+; CHECK-FASTISEL-NEXT:    add    sp, sp, #16
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
+  ret <8 x i32> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
+; CHECK-LABEL: reverse_v16f32:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    rev64 v3.4s, v3.4s
+; CHECK-SELDAG-NEXT:    rev64 v2.4s, v2.4s
+; CHECK-SELDAG-NEXT:    rev64 v4.4s, v1.4s
+; CHECK-SELDAG-NEXT:    rev64 v5.4s, v0.4s
+; CHECK-SELDAG-NEXT:    ext v0.16b, v3.16b, v3.16b, #8
+; CHECK-SELDAG-NEXT:    ext v1.16b, v2.16b, v2.16b, #8
+; CHECK-SELDAG-NEXT:    ext v2.16b, v4.16b, v4.16b, #8
+; CHECK-SELDAG-NEXT:    ext v3.16b, v5.16b, v5.16b, #8
+; CHECK-SELDAG-NEXT:    ret
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    sub    sp, sp, #32
+; CHECK-FASTISEL-NEXT:    str    q3, [sp, #16]
+; CHECK-FASTISEL-NEXT:    str    q2, [sp]
+; CHECK-FASTISEL-NEXT:    mov    v2.16b, v1.16b
+; CHECK-FASTISEL-NEXT:    ldr    q1, [sp]
+; CHECK-FASTISEL-NEXT:    mov    v3.16b, v0.16b
+; CHECK-FASTISEL-NEXT:    ldr    q0, [sp, #16]
+; CHECK-FASTISEL-NEXT:    rev64    v0.4s, v0.4s
+; CHECK-FASTISEL-NEXT:    ext    v0.16b, v0.16b, v0.16b, #8
+; CHECK-FASTISEL-NEXT:    rev64    v1.4s, v1.4s
+; CHECK-FASTISEL-NEXT:    ext    v1.16b, v1.16b, v1.16b, #8
+; CHECK-FASTISEL-NEXT:    rev64    v2.4s, v2.4s
+; CHECK-FASTISEL-NEXT:    ext    v2.16b, v2.16b, v2.16b, #8
+; CHECK-FASTISEL-NEXT:    rev64    v3.4s, v3.4s
+; CHECK-FASTISEL-NEXT:    ext    v3.16b, v3.16b, v3.16b, #8
+; CHECK-FASTISEL-NEXT:    add    sp, sp, #32
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+
+
+declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
+declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>)
+declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>)
+declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>)
+declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>)
+declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>)
+declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>)
+declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>)
+declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>)
+declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>)
+
+attributes #0 = { nounwind "target-features"="+neon" }

llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs  < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SELDAG  %s
+; RUN: llc -verify-machineinstrs -O0 < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FASTISEL %s
+
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; VECTOR_REVERSE - PPR
+;
+
+define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) #0 {
+; CHECK-LABEL: reverse_nxv2i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev p0.d, p0.d
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)
+  ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) #0 {
+; CHECK-LABEL: reverse_nxv4i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev p0.s, p0.s
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
+  ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) #0 {
+; CHECK-LABEL: reverse_nxv8i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev p0.h, p0.h
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
+  ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) #0 {
+; CHECK-LABEL: reverse_nxv16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev p0.b, p0.b
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)
+  ret <vscale x 16 x i1> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) #0 {
+; CHECK-LABEL: reverse_nxv32i1:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    rev p2.b, p1.b
+; CHECK-SELDAG-NEXT:    rev p1.b, p0.b
+; CHECK-SELDAG-NEXT:    mov p0.b, p2.b
+; CHECK-SELDAG-NEXT:    ret
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    str    x29, [sp, #-16]
+; CHECK-FASTISEL-NEXT:    addvl    sp, sp, #-1
+; CHECK-FASTISEL-NEXT:    str    p1, [sp, #7, mul vl]
+; CHECK-FASTISEL-NEXT:    mov    p1.b, p0.b
+; CHECK-FASTISEL-NEXT:    ldr    p0, [sp, #7, mul vl]
+; CHECK-FASTISEL-NEXT:    rev    p0.b, p0.b
+; CHECK-FASTISEL-NEXT:    rev    p1.b, p1.b
+; CHECK-FASTISEL-NEXT:    addvl    sp, sp, #1
+; CHECK-FASTISEL-NEXT:    ldr    x29, [sp], #16
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
+  ret <vscale x 32 x i1> %res
+}
+
+;
+; VECTOR_REVERSE - ZPR
+;
+
+define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) #0 {
+; CHECK-LABEL: reverse_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.b, z0.b
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> %a)
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: reverse_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.h, z0.h
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> %a)
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: reverse_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.s, z0.s
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) #0 {
+; CHECK-LABEL: reverse_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.d, z0.d
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)
+  ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) #0 {
+; CHECK-LABEL: reverse_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.h, z0.h
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half> %a)
+  ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) #0 {
+; CHECK-LABEL: reverse_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.s, z0.s
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a)  ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) #0 {
+; CHECK-LABEL: reverse_nxv2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.d, z0.d
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double> %a)
+  ret <vscale x 2 x double> %res
+}
+
+; Verify promote type legalisation works as expected.
+define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) #0 {
+; CHECK-LABEL: reverse_nxv2i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rev z0.d, z0.d
+; CHECK-NEXT:    ret
+
+  %res = call <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8> %a)
+  ret <vscale x 2 x i8> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) #0 {
+; CHECK-LABEL: reverse_nxv8i32:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    rev z2.s, z1.s
+; CHECK-SELDAG-NEXT:    rev z1.s, z0.s
+; CHECK-SELDAG-NEXT:    mov z0.d, z2.d
+; CHECK-SELDAG-NEXT:    ret
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    str    x29, [sp, #-16]
+; CHECK-FASTISEL-NEXT:    addvl    sp, sp, #-1
+; CHECK-FASTISEL-NEXT:    str    z1, [sp]
+; CHECK-FASTISEL-NEXT:    mov    z1.d, z0.d
+; CHECK-FASTISEL-NEXT:    ldr    z0, [sp]
+; CHECK-FASTISEL-NEXT:    rev    z0.s, z0.s
+; CHECK-FASTISEL-NEXT:    rev    z1.s, z1.s
+; CHECK-FASTISEL-NEXT:    addvl    sp, sp, #1
+; CHECK-FASTISEL-NEXT:    ldr    x29, [sp], #16
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)
+  ret <vscale x 8 x i32> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) #0 {
+; CHECK-LABEL: reverse_nxv16f32:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    rev z5.s, z3.s
+; CHECK-SELDAG-NEXT:    rev z4.s, z2.s
+; CHECK-SELDAG-NEXT:    rev z2.s, z1.s
+; CHECK-SELDAG-NEXT:    rev z3.s, z0.s
+; CHECK-SELDAG-NEXT:    mov z0.d, z5.d
+; CHECK-SELDAG-NEXT:    mov z1.d, z4.d
+; CHECK-SELDAG-NEXT:    ret
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    str    x29, [sp, #-16]
+; CHECK-FASTISEL-NEXT:    addvl    sp, sp, #-2
+; CHECK-FASTISEL-NEXT:    str    z3, [sp, #1, mul vl]
+; CHECK-FASTISEL-NEXT:    str    z2, [sp]
+; CHECK-FASTISEL-NEXT:    mov    z2.d, z1.d
+; CHECK-FASTISEL-NEXT:    ldr    z1, [sp]
+; CHECK-FASTISEL-NEXT:    mov    z3.d, z0.d
+; CHECK-FASTISEL-NEXT:    ldr    z0, [sp, #1, mul vl]
+; CHECK-FASTISEL-NEXT:    rev    z0.s, z0.s
+; CHECK-FASTISEL-NEXT:    rev    z1.s, z1.s
+; CHECK-FASTISEL-NEXT:    rev    z2.s, z2.s
+; CHECK-FASTISEL-NEXT:    rev    z3.s, z3.s
+; CHECK-FASTISEL-NEXT:    addvl    sp, sp, #2
+; CHECK-FASTISEL-NEXT:    ldr    x29, [sp], #16
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float> %a)
+  ret <vscale x 16 x float> %res
+}
+
+
+declare <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1>)
+declare <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1>)
+declare <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1>)
+declare <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1>)
+declare <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1>)
+declare <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8>)
+declare <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8>)
+declare <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32>)
+declare <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64>)
+declare <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float>)
+declare <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float>)
+declare <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double>)
+
+
+attributes #0 = { nounwind "target-features"="+sve" }

llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs  < %s 2>%t | FileCheck %s
+
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+
+target triple = "x86_64-unknown-unknown"
+
+;
+; VECTOR_REVERSE
+;
+
+define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
+; CHECK-LABEL: reverse_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pxor      %xmm1, %xmm1
+; CHECK-NEXT:    movdqa    %xmm0, %xmm2
+; CHECK-NEXT:    punpcklbw  %xmm1, %xmm
+; CHECK-NEXT:    pshufd     $78, %xmm2, %xmm2
+; CHECK-NEXT:    pshuflw    $27, %xmm2, %xmm2
+; CHECK-NEXT:    pshufhw    $27, %xmm2, %xmm2
+; CHECK-NEXT:    punpckhbw  %xmm1, %xmm0
+; CHECK-NEXT:    pshufd     $78, %xmm0, %xmm0
+; CHECK-NEXT:    pshuflw    $27, %xmm0, %xmm0
+; CHECK-NEXT:    pshufhw    $27, %xmm0, %xmm0
+; CHECK-NEXT:    packuswb   %xmm2, %xmm0
+; CHECK-NEXT:    retq
+
+  %res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a)
+  ret <16 x i8> %res
+}
+
+define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
+; CHECK-LABEL: reverse_v8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pshufd     $78, %xmm0, %xmm
+; CHECK-NEXT:    pshuflw    $27, %xmm0, %xmm0
+; CHECK-NEXT:    pshufhw    $27, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
+  ret <8 x i16> %res
+}
+
+define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
+; CHECK-LABEL: reverse_v4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pshufd    $27, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
+  ret <4 x i32> %res
+}
+
+define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
+; CHECK-LABEL: reverse_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pshufd    $78, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
+  ret <2 x i64> %res
+}
+
+define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
+; CHECK-LABEL: reverse_v4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shufps    $27, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
+  ret <4 x float> %res
+}
+
+define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
+; CHECK-LABEL: reverse_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shufps    $78, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
+  ret <2 x double> %res
+}
+
+; Verify promote type legalisation works as expected.
+define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
+; CHECK-LABEL: reverse_v2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movdqa   %xmm0, %xmm1
+; CHECK-NEXT:    psrlw    $8, %xmm1
+; CHECK-NEXT:    psllw    $8, %xmm0
+; CHECK-NEXT:    por      %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
+  ret <2 x i8> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
+; CHECK-LABEL: reverse_v8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pshufd    $27, %xmm1, %xmm2
+; CHECK-NEXT:    pshufd    $27, %xmm0, %xmm1
+; CHECK-NEXT:    movdqa %xmm2, %xmm0
+; CHECK-NEXT:    retq
+  %res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
+  ret <8 x i32> %res
+}
+
+; Verify splitvec type legalisation works as expected.
+define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
+; CHECK-LABEL: reverse_v16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movaps    %xmm1, %xmm4
+; CHECK-NEXT:    movaps    %xmm0, %xmm5
+; CHECK-NEXT:    shufps    $27, %xmm3, %xmm
+; CHECK-NEXT:    shufps    $27, %xmm2, %xmm2
+; CHECK-NEXT:    shufps    $27, %xmm1, %xmm4
+; CHECK-NEXT:    shufps    $27, %xmm0, %xmm5
+; CHECK-NEXT:    movaps    %xmm3, %xmm0
+; CHECK-NEXT:    movaps    %xmm2, %xmm1
+; CHECK-NEXT:    movaps    %xmm4, %xmm2
+; CHECK-NEXT:    movaps    %xmm5, %xmm3
+
+  %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
+  ret <16 x float> %res
+}
+
+
+declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
+declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>)
+declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>)
+declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>)
+declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>)
+declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>)
+declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>)
+declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>)
+declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>)
+declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>)
+
+attributes #0 = { nounwind }

llvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll

+; RUN: opt  -instsimplify -S < %s 2>%t | FileCheck %s
+
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+; Test back to back reverse shuffles are eliminated.
+define <vscale x 4 x i32> @shuffle_b2b_reverse(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @shuffle_b2b_reverse(
+; CHECK: ret <vscale x 4 x i32> %a
+  %rev = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
+  %rev.rev = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %rev)
+  ret <vscale x 4 x i32> %rev.rev
+}
+
+declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32>)