[RISCV] Add ISel patterns for scalable mask exts & truncs

[frasercrmck]

Summary

Original patch by @rogfer01.

This patch adds support for sign-, zero-, and any-extension from
scalable mask vector types to integer vector types, as well as
truncation in the opposite direction.

Authored-by: Roger Ferrer Ibanez <[e-mail]>
Co-Authored-by: Fraser Cormack <[e-mail]>

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

516 ↗

(On Diff #316366)

trunc would probably be better custom lowered. We should be able to remove the AND if the input has enough 0 bits. Not sure if SimplifyDemandedBits is capable of that for scalable vectors yet.

sext/zext/anyext might also be better custom lowered just to cut down on patterns. Our isel table is approaching 1MB. The next largest target is at about 600K.

[frasercrmck]

• replace patterns with custom-lowering

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

516 ↗

(On Diff #316366)

Yeah, fair enough. These are good candidates for that since they're just re-expressed as standard nodes. I've done both in custom lowering functions.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

377

Technically this should only be for the legal types. But I guess we don't expect to see scalable vectors that need to be type legalized?

1233

I don't think we should be creating scalars with MVT::i64 type on RV32 here. It will usually work because a round of type legalization is called after vector op legalization. Which will legalize the ISD::SPLAT_VECTOR. But if for some reason a mask extension is ever introduced during LegalizeDAG, the scalar type wouldn't get legalized. Can we just detect this case and emit SPLAT_VECTOR_I64 here?

[frasercrmck]

• rebase on main
• fix conflicts

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

377

Not at this stage. I agree it would be better, though. Having an array or vector of legal vector types would be useful, to start with. Should I fold that into this patch or clean it up later?

1233

True. It's quite fiddly but I'm not sure we can avoid that. I'm a bit concerned that if we wanted to do this generically we can't always use SPLAT_VECTOR_I64 since the scalar won't always be (provably) a sign-extended 32-bit value. Also I don't think there's a way of detecting the level we're at, so we'd be creating SPLAT_VECTOR_I64 quite early on, or expanding the sequence for non-sign-extended values, which might inhibit generic SPLAT_VECTOR combines.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1233

The constants used here are sign extended though right? You are correct there's no way to tell what level we're at in Lowering. Only DAG combine has a level we can check.

Assuming the type is legal, this code will first run in LegalizeVectorOps. It will produce a SPLAT_VECTOR. Then we'll immediately run scalar type legalization which will turn it into SPLAT_VECTOR_I64. I don't think there's a DAG combine in between.

I think the only optimizations that will have an opportunity to see the SPLAT_VECTOR would be in LegalizeVectorOps. If I remember right, that visits operands before users. (LegalizeDAG is the opposite). So if we do what I suggested, I think we would make the SPLAT_VECTOR_I64 and the VSELECT before the users of the VSELECT are visited. So if the legalization of the user of the VSELECT did some optimization that looked through the VSELECT and found the unknown SPLAT_VECTOR_I64 instead of SPLAT_VECTOR then whatever optimization it was trying to do would break. Not sure how likely that is, legalization doesn't typically look very deep through operands beyond maybe calling computeKnownBits.

1251

Weren't these checked in the caller? Could we just assert here?

1255

Is the FIXME telling me why the code is written then way it is? Or is trying to tell me we need to make additional changes to be careful?

[frasercrmck]

• rebase on main
• only custom-lower for legal types
• improve handling of illegal scalar types and splats thereof

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1233

These constants are only ever sign-extended, yes. In this context it should be fine, but I was extending the scope somewhat to make it a generic scalar splat helper function. And in that case we'd have to think about how to handle difficult operands and when it gets called.

I've made the check for legality raised earlier so we can better constrain the scope of this function. The code now also only ever creates scalars of XLenVT, and does either SPLAT_VECTOR or SPLAT_VECTOR_I64 depending on the setup.

1251

Yes, they were checked. I didn't fix that up when I rebased. Thanks for the spot!

1255

It's not well worded. It's why the code is written the way it is since it's not immediately obvious to a reader. I must have been hinting at a theoretical fix that didn't necessitate this kind of thing. Once I incorporate your above suggestion I'll remove the FIXME.

[craig.topper]

LGTM with that one comment.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1229

Why do we need to check that both VecVT and Src.getValueType() are vectors? Don't they always match?

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1229

I'd sure hope so. I think I generally tend towards avoiding making assumptions but I see how that often results in redundancy. We'd be in a pickle if the types didn't match up. I'll fix that up before pushing. Cheers.

llvm/lib/Target/RISCV/RISCVISelLowering.h

private:
   SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
+                             int64_t ExtTrueVal) const;
+  SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
   bool isEligibleForTailCallOptimization(
       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 
   /// Generate error diagnostics if any register used by CC has been marked

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtV()) {
     for (auto VT : MVT::integer_scalable_vector_valuetypes()) {
       setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
 
       setOperationAction(ISD::SMIN, VT, Legal);
       setOperationAction(ISD::SMAX, VT, Legal);
       setOperationAction(ISD::UMIN, VT, Legal);
       setOperationAction(ISD::UMAX, VT, Legal);
 
-      // Lower RVV truncates as a series of "RISCVISD::TRUNCATE_VECTOR"
+      if (isTypeLegal(VT)) {
+        // Custom-lower extensions and truncations from/to mask types.
+        setOperationAction(ISD::ANY_EXTEND, VT, Custom);
+        setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
+        setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
+
+        // We custom-lower all legally-typed vector truncates:
+        // 1. Mask VTs are custom-expanded into a series of standard nodes
+        // 2. Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR"
         // nodes which truncate by one power of two at a time.
         setOperationAction(ISD::TRUNCATE, VT, Custom);
       }
+    }
 
     // We must custom-lower SPLAT_VECTOR vXi64 on RV32
     if (!Subtarget.is64Bit())
       setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
 
     // Expand various CCs to best match the RVV ISA, which natively supports UNE
     // but no other unordered comparisons, and supports all ordered comparisons
     // except ONE. Additionally, we expand GT,OGT,GE,OGE for optimization
case ISD::BITREVERSE: {
     unsigned Imm = VT.getSizeInBits() - 1;
     // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
     if (Op.getOpcode() == ISD::BSWAP)
       Imm &= ~0x7U;
     return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0),
                        DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT()));
   }
   case ISD::TRUNCATE: {
-    // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
-    // truncates as a series of "RISCVISD::TRUNCATE_VECTOR" nodes which
-    // truncate by one power of two at a time.
     SDLoc DL(Op);
     EVT VT = Op.getValueType();
-    // Only custom-lower non-mask truncates
-    if (!VT.isVector() || VT.getVectorElementType() == MVT::i1)
+    // Only custom-lower vector truncates
+    if (!VT.isVector())
       return Op;
 
+    // Truncates to mask types are handled differently
+    if (VT.getVectorElementType() == MVT::i1)
+      return lowerVectorMaskTrunc(Op, DAG);
+
+    // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
+    // truncates as a series of "RISCVISD::TRUNCATE_VECTOR" nodes which
+    // truncate by one power of two at a time.
     EVT DstEltVT = VT.getVectorElementType();
 
     SDValue Src = Op.getOperand(0);
     EVT SrcVT = Src.getValueType();
     EVT SrcEltVT = SrcVT.getVectorElementType();
 
     assert(DstEltVT.bitsLT(SrcEltVT) &&
            isPowerOf2_64(DstEltVT.getSizeInBits()) &&
            isPowerOf2_64(SrcEltVT.getSizeInBits()) &&
            "Unexpected vector truncate lowering");
 
     SDValue Result = Src;
     LLVMContext &Context = *DAG.getContext();
     const ElementCount Count = SrcVT.getVectorElementCount();
     do {
       SrcEltVT = EVT::getIntegerVT(Context, SrcEltVT.getSizeInBits() / 2);
       EVT ResultVT = EVT::getVectorVT(Context, SrcEltVT, Count);
       Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR, DL, ResultVT, Result);
     } while (SrcEltVT != DstEltVT);
 
     return Result;
   }
+  case ISD::ANY_EXTEND:
+  case ISD::ZERO_EXTEND:
+    return lowerVectorMaskExt(Op, DAG, /*ExtVal*/ 1);
+  case ISD::SIGN_EXTEND:
+    return lowerVectorMaskExt(Op, DAG, /*ExtVal*/ -1);
   case ISD::SPLAT_VECTOR:
     return lowerSPLATVECTOR(Op, DAG);
   case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT);
     // We define our scalable vector types for lmul=1 to use a 64 bit known
     // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
if (isNullConstant(Hi))
     return Lo;
 
   Hi = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Hi);
   Hi = DAG.getNode(ISD::SHL, DL, VecVT, Hi, ThirtyTwoV);
 
   return DAG.getNode(ISD::OR, DL, VecVT, Lo, Hi);
 }
 
+// Custom-lower extensions from mask vectors by using a vselect either with 1
+// for zero/any-extension or -1 for sign-extension:
+//   (vXiN = (s|z)ext vXi1:vmask) -> (vXiN = vselect vmask, (-1 or 1), 0)
+// Note that any-extension is lowered identically to zero-extension.
+SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
+                                                int64_t ExtTrueVal) const {
+  SDLoc DL(Op);
+  EVT VecVT = Op.getValueType();
+  SDValue Src = Op.getOperand(0);
+  // Only custom-lower extensions from mask types
+  if (!Src.getValueType().isVector() ||
+      Src.getValueType().getVectorElementType() != MVT::i1)
+    return Op;
+
+  // Be careful not to introduce illegal scalar types at this stage, and be
+  // careful also about splatting constants as on RV32, vXi64 SPLAT_VECTOR is
+  // illegal and must be expanded. Since we know that the constants are
+  // sign-extended 32-bit values, we use SPLAT_VECTOR_I64 directly.
+  bool IsRV32E64 =
+      !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64;
+  SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
+  SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, Subtarget.getXLenVT());
+
+  if (!IsRV32E64) {
+    SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero);
+    SplatTrueVal = DAG.getSplatVector(VecVT, DL, SplatTrueVal);
+  } else {
+    SplatZero = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatZero);
+    SplatTrueVal =
+        DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatTrueVal);
+  }
+
+  return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero);
+}
+
+// Custom-lower truncations from vectors to mask vectors by using a mask and a
+// setcc operation:
+//   (vXi1 = trunc vXiN vec) -> (vXi1 = setcc (and vec, 1), 0, ne)
+SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT MaskVT = Op.getValueType();
+  // Only expect to custom-lower truncations to mask types
+  assert(MaskVT.isVector() && MaskVT.getVectorElementType() == MVT::i1 &&
+         "Unexpected type for vector mask lowering");
+  SDValue Src = Op.getOperand(0);
+  EVT VecVT = Src.getValueType();
+
+  // Be careful not to introduce illegal scalar types at this stage, and be
+  // careful also about splatting constants as on RV32, vXi64 SPLAT_VECTOR is
+  // illegal and must be expanded. Since we know that the constants are
+  // sign-extended 32-bit values, we use SPLAT_VECTOR_I64 directly.
+  bool IsRV32E64 =
+      !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64;
+  SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT());
+  SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
+
+  if (!IsRV32E64) {
+    SplatOne = DAG.getSplatVector(VecVT, DL, SplatOne);
+    SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero);
+  } else {
+    SplatOne = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatOne);
+    SplatZero = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatZero);
+  }
+
+  SDValue Trunc = DAG.getNode(ISD::AND, DL, VecVT, Src, SplatOne);
+
+  return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE);
+}
+
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc DL(Op);
 
   if (Subtarget.hasStdExtV()) {
     // Some RVV intrinsics may claim that they want an integer operand to be
     // extended.

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @sext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @zext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i8_nxv1i1(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: trunc_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i8> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i8> @sext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @zext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i8_nxv2i1(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: trunc_nxv2i8_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i8> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i8> @sext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @zext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i8_nxv4i1(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: trunc_nxv4i8_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i8> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i8> @sext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @zext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i8_nxv8i1(<vscale x 8 x i8> %v) {
+; CHECK-LABEL: trunc_nxv8i8_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i8> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+
+define <vscale x 16 x i8> @sext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: sext_nxv16i1_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @zext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: zext_nxv16i1_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i1> @trunc_nxv16i8_nxv16i1(<vscale x 16 x i8> %v) {
+; CHECK-LABEL: trunc_nxv16i8_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 16 x i8> %v to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %r
+}
+
+define <vscale x 32 x i8> @sext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: sext_nxv32i1_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 32 x i1> %v to <vscale x 32 x i8>
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @zext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: zext_nxv32i1_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 32 x i1> %v to <vscale x 32 x i8>
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i1> @trunc_nxv32i8_nxv32i1(<vscale x 32 x i8> %v) {
+; CHECK-LABEL: trunc_nxv32i8_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 32 x i8> %v to <vscale x 32 x i1>
+  ret <vscale x 32 x i1> %r
+}
+
+define <vscale x 64 x i8> @sext_nxv64i1_nxv64i8(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: sext_nxv64i1_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 64 x i1> %v to <vscale x 64 x i8>
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @zext_nxv64i1_nxv64i8(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: zext_nxv64i1_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 64 x i1> %v to <vscale x 64 x i8>
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i1> @trunc_nxv64i8_nxv64i1(<vscale x 64 x i8> %v) {
+; CHECK-LABEL: trunc_nxv64i8_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 64 x i8> %v to <vscale x 64 x i1>
+  ret <vscale x 64 x i1> %r
+}
+
+define <vscale x 1 x i16> @sext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @zext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i16_nxv1i1(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: trunc_nxv1i16_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i16> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i16> @sext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @zext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i16_nxv2i1(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: trunc_nxv2i16_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i16> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i16> @sext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @zext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i16_nxv4i1(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: trunc_nxv4i16_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i16> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i16> @sext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @zext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i16_nxv8i1(<vscale x 8 x i16> %v) {
+; CHECK-LABEL: trunc_nxv8i16_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i16> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+
+define <vscale x 16 x i16> @sext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: sext_nxv16i1_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @zext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: zext_nxv16i1_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i1> @trunc_nxv16i16_nxv16i1(<vscale x 16 x i16> %v) {
+; CHECK-LABEL: trunc_nxv16i16_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 16 x i16> %v to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %r
+}
+
+define <vscale x 32 x i16> @sext_nxv32i1_nxv32i16(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: sext_nxv32i1_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 32 x i1> %v to <vscale x 32 x i16>
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @zext_nxv32i1_nxv32i16(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: zext_nxv32i1_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 32 x i1> %v to <vscale x 32 x i16>
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i1> @trunc_nxv32i16_nxv32i1(<vscale x 32 x i16> %v) {
+; CHECK-LABEL: trunc_nxv32i16_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 32 x i16> %v to <vscale x 32 x i1>
+  ret <vscale x 32 x i1> %r
+}
+
+define <vscale x 1 x i32> @sext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @zext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i32_nxv1i1(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: trunc_nxv1i32_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i32> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i32> @sext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @zext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i32_nxv2i1(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: trunc_nxv2i32_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i32> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i32> @sext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @zext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i32_nxv4i1(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: trunc_nxv4i32_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i32> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i32> @sext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @zext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i32_nxv8i1(<vscale x 8 x i32> %v) {
+; CHECK-LABEL: trunc_nxv8i32_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i32> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+
+define <vscale x 16 x i32> @sext_nxv16i1_nxv16i32(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: sext_nxv16i1_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @zext_nxv16i1_nxv16i32(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: zext_nxv16i1_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i1> @trunc_nxv16i32_nxv16i1(<vscale x 16 x i32> %v) {
+; CHECK-LABEL: trunc_nxv16i32_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 16 x i32> %v to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %r
+}
+
+define <vscale x 1 x i64> @sext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i64>
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @zext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i64>
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i64_nxv1i1(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: trunc_nxv1i64_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i64> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i64> @sext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @zext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i64_nxv2i1(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: trunc_nxv2i64_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i64> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i64> @sext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i64>
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @zext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i64>
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i64_nxv4i1(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: trunc_nxv4i64_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i64> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i64> @sext_nxv8i1_nxv8i64(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i64>
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @zext_nxv8i1_nxv8i64(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i64>
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i64_nxv8i1(<vscale x 8 x i64> %v) {
+; CHECK-LABEL: trunc_nxv8i64_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i64> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @sext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @zext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i8>
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i8_nxv1i1(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: trunc_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i8> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i8> @sext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @zext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i8_nxv2i1(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: trunc_nxv2i8_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i8> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i8> @sext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @zext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i8_nxv4i1(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: trunc_nxv4i8_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i8> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i8> @sext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @zext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i8_nxv8i1(<vscale x 8 x i8> %v) {
+; CHECK-LABEL: trunc_nxv8i8_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i8> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+
+define <vscale x 16 x i8> @sext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: sext_nxv16i1_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @zext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: zext_nxv16i1_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i1> @trunc_nxv16i8_nxv16i1(<vscale x 16 x i8> %v) {
+; CHECK-LABEL: trunc_nxv16i8_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 16 x i8> %v to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %r
+}
+
+define <vscale x 32 x i8> @sext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: sext_nxv32i1_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 32 x i1> %v to <vscale x 32 x i8>
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @zext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: zext_nxv32i1_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 32 x i1> %v to <vscale x 32 x i8>
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i1> @trunc_nxv32i8_nxv32i1(<vscale x 32 x i8> %v) {
+; CHECK-LABEL: trunc_nxv32i8_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 32 x i8> %v to <vscale x 32 x i1>
+  ret <vscale x 32 x i1> %r
+}
+
+define <vscale x 64 x i8> @sext_nxv64i1_nxv64i8(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: sext_nxv64i1_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 64 x i1> %v to <vscale x 64 x i8>
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @zext_nxv64i1_nxv64i8(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: zext_nxv64i1_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 64 x i1> %v to <vscale x 64 x i8>
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i1> @trunc_nxv64i8_nxv64i1(<vscale x 64 x i8> %v) {
+; CHECK-LABEL: trunc_nxv64i8_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 64 x i8> %v to <vscale x 64 x i1>
+  ret <vscale x 64 x i1> %r
+}
+
+define <vscale x 1 x i16> @sext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @zext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i16>
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i16_nxv1i1(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: trunc_nxv1i16_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i16> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i16> @sext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @zext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i16_nxv2i1(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: trunc_nxv2i16_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i16> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i16> @sext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @zext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i16_nxv4i1(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: trunc_nxv4i16_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i16> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i16> @sext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @zext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i16_nxv8i1(<vscale x 8 x i16> %v) {
+; CHECK-LABEL: trunc_nxv8i16_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i16> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+
+define <vscale x 16 x i16> @sext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: sext_nxv16i1_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @zext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: zext_nxv16i1_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i1> @trunc_nxv16i16_nxv16i1(<vscale x 16 x i16> %v) {
+; CHECK-LABEL: trunc_nxv16i16_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 16 x i16> %v to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %r
+}
+
+define <vscale x 32 x i16> @sext_nxv32i1_nxv32i16(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: sext_nxv32i1_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 32 x i1> %v to <vscale x 32 x i16>
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @zext_nxv32i1_nxv32i16(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: zext_nxv32i1_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 32 x i1> %v to <vscale x 32 x i16>
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i1> @trunc_nxv32i16_nxv32i1(<vscale x 32 x i16> %v) {
+; CHECK-LABEL: trunc_nxv32i16_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 32 x i16> %v to <vscale x 32 x i1>
+  ret <vscale x 32 x i1> %r
+}
+
+define <vscale x 1 x i32> @sext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @zext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i32_nxv1i1(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: trunc_nxv1i32_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i32> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i32> @sext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @zext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i32_nxv2i1(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: trunc_nxv2i32_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i32> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i32> @sext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @zext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i32_nxv4i1(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: trunc_nxv4i32_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i32> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i32> @sext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @zext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i32_nxv8i1(<vscale x 8 x i32> %v) {
+; CHECK-LABEL: trunc_nxv8i32_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i32> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+
+define <vscale x 16 x i32> @sext_nxv16i1_nxv16i32(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: sext_nxv16i1_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @zext_nxv16i1_nxv16i32(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: zext_nxv16i1_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i1> @trunc_nxv16i32_nxv16i1(<vscale x 16 x i32> %v) {
+; CHECK-LABEL: trunc_nxv16i32_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 16 x i32> %v to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %r
+}
+
+define <vscale x 1 x i64> @sext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: sext_nxv1i1_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i64>
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @zext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: zext_nxv1i1_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v16, v25, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i64>
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i1> @trunc_nxv1i64_nxv1i1(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: trunc_nxv1i64_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vand.vi v25, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 1 x i64> %v to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %r
+}
+
+define <vscale x 2 x i64> @sext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: sext_nxv2i1_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @zext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: zext_nxv2i1_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v16, v26, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i1> @trunc_nxv2i64_nxv2i1(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: trunc_nxv2i64_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vand.vi v26, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 2 x i64> %v to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %r
+}
+
+define <vscale x 4 x i64> @sext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: sext_nxv4i1_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i64>
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @zext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: zext_nxv4i1_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v16, v28, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i64>
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i1> @trunc_nxv4i64_nxv4i1(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: trunc_nxv4i64_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vand.vi v28, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 4 x i64> %v to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 8 x i64> @sext_nxv8i1_nxv8i64(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: sext_nxv8i1_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i64>
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @zext_nxv8i1_nxv8i64(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: zext_nxv8i1_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT:    ret
+  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i64>
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i1> @trunc_nxv8i64_nxv8i1(<vscale x 8 x i64> %v) {
+; CHECK-LABEL: trunc_nxv8i64_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vand.vi v8, v16, 1
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %r = trunc <vscale x 8 x i64> %v to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %r
+}
+