[RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.

[frasercrmck]

LGTM

[craig.topper]

Rebase

[craig.topper]

Rebase

[craig.topper]

Remove Zba changes that accidentally got merged in the previous rebase

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
 
 let Predicates = [HasStdExtZbp] in {
 def SHFLI   : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
 def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
-def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>;
-def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>;
+def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
+def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def SLOW   : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>;
 def SROW   : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {

llvm/test/CodeGen/RISCV/rv64Zbb.ll

 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 33
 ; RV64I-NEXT:    addi a1, a1, -2
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: slliuw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slliu.w a0, a0, 1
+; RV64IB-NEXT:    slli.uw a0, a0, 1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: slliuw:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slliu.w a0, a0, 1
+; RV64IBB-NEXT:    slli.uw a0, a0, 1
 ; RV64IBB-NEXT:    ret
   %conv1 = shl i64 %a, 1
   %shl = and i64 %conv1, 8589934590
   ret i64 %shl
 }
 
 define i64 @adduw(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: adduw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: adduw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addu.w a0, a0, a1
+; RV64IB-NEXT:    add.uw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: adduw:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addu.w a0, a0, a1
+; RV64IBB-NEXT:    add.uw a0, a0, a1
 ; RV64IBB-NEXT:    ret
   %and = and i64 %b, 4294967295
   %add = add i64 %and, %a
   ret i64 %add
 }

llvm/test/MC/RISCV/rv64zbb-invalid.s

 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s
 
 # Too few operands
-slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-slliu.w t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
-slliu.w t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 # Too few operands
-addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 sloiw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv64zbb-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip base extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbb -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
+# CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
-slliu.w t0, t1, 0
-# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
+slli.uw t0, t1, 0
+# CHECK-ASM-AND-OBJ: add.uw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
-addu.w t0, t1, t2
+add.uw t0, t1, t2
 # CHECK-ASM-AND-OBJ: slow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
 slow t0, t1, t2
 # CHECK-ASM-AND-OBJ: srow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
 srow t0, t1, t2
 # CHECK-ASM-AND-OBJ: sloiw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]