[RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen.

[craig.topper]

Summary

The default behavior for any_extend of a constant is to zero extend.
This occurs inside of getNode rather than allowing type legalization
to promote the constant which would sign extend. By using sign extend
with getNode the constant will be sign extended. This gives a better
chance for isel to find a simm5 immediate since all xlen bits are
examined there.

For instructions that use a uimm5 immediate, this change only affects
constants >= 128 for i8 or >= 32768 for i16. Constants that large
already wouldn't have been eligible for uimm5 and would need to use a
scalar register.

If the instruction isn't able to use simm5 or the immediate is
too large, we'll need to materialize the immediate in a register.
As far as I know constants with all 1s in the upper bits should
materialize as well or better than all 0s.

Longer term we should probably have a SEW aware PatFrag to ignore
the bits above SEW before checking simm5.

I updated about half the test cases in some tests to use a negative
constant to get coverage for this.

[rogfer01]

For instructions that use a uimm5 immediate, this change only affects
constants >= 128 for i8 or >= 32768 for i16. Constants that large
already wouldn't have been eligible for uimm5 and would need to use a
scalar register.

Just to make sure I understand this case, this is relevant for negative numbers which at this point of the backend just look like like very large constants (up to XLenVT).

Other than that, LGTM. Thanks @craig.topper

[craig.topper]

In D93487#2461366, @rogfer01 wrote:

For instructions that use a uimm5 immediate, this change only affects
constants >= 128 for i8 or >= 32768 for i16. Constants that large
already wouldn't have been eligible for uimm5 and would need to use a
scalar register.

Just to make sure I understand this case, this is relevant for negative numbers which at this point of the backend just look like like very large constants (up to XLenVT).

Other than that, LGTM. Thanks @craig.topper

That was me thinking through making sure this wouldn't break shifts and other instructions that use uimm5. If for some reason an SEW=8 shift had 128 as a constant, previously it would have stayed 128 when we extended it to xlenvt. Now it becomes 0xffffffffffffff80. But neither 128 or 0xffffffffffffff80 would be matched by uimm5 so this shouldn't break those instructions.

[evandro]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
             RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) {
       if (II->ExtendedOperand) {
         assert(II->ExtendedOperand < Op.getNumOperands());
         SmallVector<SDValue, 8> Operands(Op->op_begin(), Op->op_end());
         SDValue &ScalarOp = Operands[II->ExtendedOperand];
         EVT OpVT = ScalarOp.getValueType();
         if (OpVT == MVT::i8 || OpVT == MVT::i16 ||
             (OpVT == MVT::i32 && Subtarget.is64Bit())) {
-          ScalarOp =
-              DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), ScalarOp);
+          // If the operand is a constant, sign extend to increase our chances
+          // of being able to use a .vi instruction. ANY_EXTEND would become a
+          // a zero extend and the simm5 check in isel would fail.
+          // FIXME: Should we ignore the upper bits in isel instead?
+          unsigned ExtOpc = isa<ConstantSDNode>(ScalarOp) ? ISD::SIGN_EXTEND
+                                                          : ISD::ANY_EXTEND;
+          ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp);
           return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
                              Operands);
         }
       }
     }
   }
 
   switch (IntNo) {
if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
         // The operands start from the second argument in INTRINSIC_W_CHAIN.
         unsigned ExtendOp = II->ExtendedOperand + 1;
         assert(ExtendOp < Op.getNumOperands());
         SmallVector<SDValue, 8> Operands(Op->op_begin(), Op->op_end());
         SDValue &ScalarOp = Operands[ExtendOp];
         EVT OpVT = ScalarOp.getValueType();
         if (OpVT == MVT::i8 || OpVT == MVT::i16 ||
             (OpVT == MVT::i32 && Subtarget.is64Bit())) {
-          ScalarOp =
-              DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), ScalarOp);
-          return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(), Operands);
+          // If the operand is a constant, sign extend to increase our chances
+          // of being able to use a .vi instruction. ANY_EXTEND would become a
+          // a zero extend and the simm5 check in isel would fail.
+          // FIXME: Should we ignore the upper bits in isel instead?
+          unsigned ExtOpc = isa<ConstantSDNode>(ScalarOp) ? ISD::SIGN_EXTEND
+                                                          : ISD::ANY_EXTEND;
+          ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp);
+          return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(),
+                             Operands);
         }
       }
     }
   }
 
   return SDValue();
 }
 

llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll

; CHECK:       vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vadc_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8(
     <vscale x 1 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 1 x i1> %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadc_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 9,
     <vscale x 2 x i1> %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadc_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8(
     <vscale x 4 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 4 x i1> %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadc_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 9,
     <vscale x 8 x i1> %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadc_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 16 x i8> @llvm.riscv.vadc.nxv16i8.i8(
     <vscale x 16 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 16 x i1> %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadc_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 32 x i8> @llvm.riscv.vadc.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 9,
     <vscale x 32 x i1> %1,
     i32 %2)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadc_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 64 x i8> @llvm.riscv.vadc.nxv64i8.i8(
     <vscale x 64 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 64 x i1> %1,
     i32 %2)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadc_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 1 x i16> @llvm.riscv.vadc.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 9,
     <vscale x 1 x i1> %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadc_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 2 x i16> @llvm.riscv.vadc.nxv2i16.i16(
     <vscale x 2 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 2 x i1> %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadc_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 4 x i16> @llvm.riscv.vadc.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 9,
     <vscale x 4 x i1> %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadc_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 8 x i16> @llvm.riscv.vadc.nxv8i16.i16(
     <vscale x 8 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 8 x i1> %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadc_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 16 x i16> @llvm.riscv.vadc.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 9,
     <vscale x 16 x i1> %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadc_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 32 x i16> @llvm.riscv.vadc.nxv32i16.i16(
     <vscale x 32 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 32 x i1> %1,
     i32 %2)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadc_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 1 x i32> @llvm.riscv.vadc.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 9,
     <vscale x 1 x i1> %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadc_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 2 x i32> @llvm.riscv.vadc.nxv2i32.i32(
     <vscale x 2 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 2 x i1> %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadc_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 4 x i32> @llvm.riscv.vadc.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 9,
     <vscale x 4 x i1> %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadc_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 8 x i32> @llvm.riscv.vadc.nxv8i32.i32(
     <vscale x 8 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 8 x i1> %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadc_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
 entry:

llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll

; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadc_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8(
     <vscale x 2 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 2 x i1> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadc_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     <vscale x 4 x i1> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadc_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8(
     <vscale x 8 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 8 x i1> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadc_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 16 x i8> @llvm.riscv.vadc.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     <vscale x 16 x i1> %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadc_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 32 x i8> @llvm.riscv.vadc.nxv32i8.i8(
     <vscale x 32 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 32 x i1> %1,
     i64 %2)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadc_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 64 x i8> @llvm.riscv.vadc.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     i8 9,
     <vscale x 64 x i1> %1,
     i64 %2)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadc_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 1 x i16> @llvm.riscv.vadc.nxv1i16.i16(
     <vscale x 1 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 1 x i1> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadc_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 2 x i16> @llvm.riscv.vadc.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     <vscale x 2 x i1> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadc_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 4 x i16> @llvm.riscv.vadc.nxv4i16.i16(
     <vscale x 4 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 4 x i1> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadc_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 8 x i16> @llvm.riscv.vadc.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     <vscale x 8 x i1> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadc_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 16 x i16> @llvm.riscv.vadc.nxv16i16.i16(
     <vscale x 16 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 16 x i1> %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadc_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 32 x i16> @llvm.riscv.vadc.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     <vscale x 32 x i1> %1,
     i64 %2)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadc_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 1 x i32> @llvm.riscv.vadc.nxv1i32.i32(
     <vscale x 1 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 1 x i1> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadc_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 2 x i32> @llvm.riscv.vadc.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     <vscale x 2 x i1> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadc_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 4 x i32> @llvm.riscv.vadc.nxv4i32.i32(
     <vscale x 4 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 4 x i1> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadc_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 8 x i32> @llvm.riscv.vadc.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     <vscale x 8 x i1> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadc_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i32_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 16 x i32> @llvm.riscv.vadc.nxv16i32.i32(
     <vscale x 16 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 16 x i1> %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vadc_vim_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i64_nxv1i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 1 x i64> @llvm.riscv.vadc.nxv1i64.i64(
     <vscale x 1 x i64> %0,
     i64 9,
     <vscale x 1 x i1> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 2 x i64> @intrinsic_vadc_vim_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i64_nxv2i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 2 x i64> @llvm.riscv.vadc.nxv2i64.i64(
     <vscale x 2 x i64> %0,
-    i64 9,
+    i64 -9,
     <vscale x 2 x i1> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
 }
 
 define <vscale x 4 x i64> @intrinsic_vadc_vim_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i64_nxv4i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
 ; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 4 x i64> @llvm.riscv.vadc.nxv4i64.i64(
     <vscale x 4 x i64> %0,
     i64 9,
     <vscale x 4 x i1> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
 }
 
 define <vscale x 8 x i64> @intrinsic_vadc_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i64_nxv8i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 8 x i64> @llvm.riscv.vadc.nxv8i64.i64(
     <vscale x 8 x i64> %0,
-    i64 9,
+    i64 -9,
     <vscale x 8 x i1> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
 }

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 32 x i1> %2,
     i32 %3)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
     <vscale x 64 x i8> %0,
-    i8 9,
+    i8 -9,
     i32 %1)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 64 x i1> %2,
     i32 %3)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 32 x i1> %2,
     i32 %3)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
 ; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i32> %a
 }

llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll

; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i8(
     <vscale x 2 x i8> %0,
-    i8 9,
+    i8 -9,
     i32 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i8(
     <vscale x 8 x i8> %0,
-    i8 9,
+    i8 -9,
     i32 %1)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i1.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 32 x i1> @intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i1.i8(
     <vscale x 32 x i8> %0,
-    i8 9,
+    i8 -9,
     i32 %1)
 
   ret <vscale x 32 x i1> %a
 }
 
 define <vscale x 64 x i1> @intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 64 x i1> @llvm.riscv.vmadc.nxv64i1.i8(
     <vscale x 64 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 64 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i1.i16(
     <vscale x 1 x i16> %0,
-    i16 9,
+    i16 -9,
     i32 %1)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i16(
     <vscale x 4 x i16> %0,
-    i16 9,
+    i16 -9,
     i32 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i1.i16(
     <vscale x 16 x i16> %0,
-    i16 9,
+    i16 -9,
     i32 %1)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 32 x i1> @intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i1.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 32 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i1.i32(
     <vscale x 1 x i32> %0,
-    i32 9,
+    i32 -9,
     i32 %1)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i32(
     <vscale x 4 x i32> %0,
-    i32 9,
+    i32 -9,
     i32 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i1.i32(
     <vscale x 16 x i32> %0,
-    i32 9,
+    i32 -9,
     i32 %1)
 
   ret <vscale x 16 x i1> %a
 }

llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll

; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i8(
     <vscale x 2 x i8> %0,
-    i8 9,
+    i8 -9,
     i64 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i8(
     <vscale x 8 x i8> %0,
-    i8 9,
+    i8 -9,
     i64 %1)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i1.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 32 x i1> @intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i1.i8(
     <vscale x 32 x i8> %0,
-    i8 9,
+    i8 -9,
     i64 %1)
 
   ret <vscale x 32 x i1> %a
 }
 
 define <vscale x 64 x i1> @intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 64 x i1> @llvm.riscv.vmadc.nxv64i1.i8(
     <vscale x 64 x i8> %0,
     i8 9,
     i64 %1)
 
   ret <vscale x 64 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i1.i16(
     <vscale x 1 x i16> %0,
-    i16 9,
+    i16 -9,
     i64 %1)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i16(
     <vscale x 4 x i16> %0,
-    i16 9,
+    i16 -9,
     i64 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i1.i16(
     <vscale x 16 x i16> %0,
-    i16 9,
+    i16 -9,
     i64 %1)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 32 x i1> @intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i1.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     i64 %1)
 
   ret <vscale x 32 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i1.i32(
     <vscale x 1 x i32> %0,
-    i32 9,
+    i32 -9,
     i64 %1)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i32(
     <vscale x 4 x i32> %0,
-    i32 9,
+    i32 -9,
     i64 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     i64 %1)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i1.i32(
     <vscale x 16 x i32> %0,
-    i32 9,
+    i32 -9,
     i64 %1)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc_vi_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i1.i64(
     <vscale x 1 x i64> %0,
     i64 9,
     i64 %1)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc_vi_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i1.i64(
     <vscale x 2 x i64> %0,
-    i64 9,
+    i64 -9,
     i64 %1)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc_vi_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
 ; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i1.i64(
     <vscale x 4 x i64> %0,
     i64 9,
     i64 %1)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc_vi_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i64_i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+; CHECK:       vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i1.i64(
     <vscale x 8 x i64> %0,
-    i64 9,
+    i64 -9,
     i64 %1)
 
   ret <vscale x 8 x i1> %a
 }

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll

; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i1.i8(
     <vscale x 2 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 2 x i1> %1,
     i32 %2)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i1.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     <vscale x 4 x i1> %1,
     i32 %2)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i1.i8(
     <vscale x 8 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 8 x i1> %1,
     i32 %2)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i1.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     <vscale x 16 x i1> %1,
     i32 %2)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i1.i8(
     <vscale x 32 x i8> %0,
-    i8 9,
+    i8 -9,
     <vscale x 32 x i1> %1,
     i32 %2)
 
   ret <vscale x 32 x i1> %a
 }
 
 define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i1.i8(
     <vscale x 64 x i8> %0,
     i8 9,
     <vscale x 64 x i1> %1,
     i32 %2)
 
   ret <vscale x 64 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i1.i16(
     <vscale x 1 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 1 x i1> %1,
     i32 %2)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i1.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     <vscale x 2 x i1> %1,
     i32 %2)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i1.i16(
     <vscale x 4 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 4 x i1> %1,
     i32 %2)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i1.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     <vscale x 8 x i1> %1,
     i32 %2)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i1.i16(
     <vscale x 16 x i16> %0,
-    i16 9,
+    i16 -9,
     <vscale x 16 x i1> %1,
     i32 %2)
 
   ret <vscale x 16 x i1> %a
 }
 
 define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i1.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     <vscale x 32 x i1> %1,
     i32 %2)
 
   ret <vscale x 32 x i1> %a
 }
 
 define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i1.i32(
     <vscale x 1 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 1 x i1> %1,
     i32 %2)
 
   ret <vscale x 1 x i1> %a
 }
 
 define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i1.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     <vscale x 2 x i1> %1,
     i32 %2)
 
   ret <vscale x 2 x i1> %a
 }
 
 define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i1.i32(
     <vscale x 4 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 4 x i1> %1,
     i32 %2)
 
   ret <vscale x 4 x i1> %a
 }
 
 define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
 ; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
   %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i1.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     <vscale x 8 x i1> %1,
     i32 %2)
 
   ret <vscale x 8 x i1> %a
 }
 
 define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+; CHECK:       vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0
   %a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i1.i32(
     <vscale x 16 x i32> %0,
-    i32 9,
+    i32 -9,
     <vscale x 16 x i1> %1,
     i32 %2)
 
   ret <vscale x 16 x i1> %a
 }

llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll

; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 1 x i8> @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 2 x i8> @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 4 x i8> @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 8 x i8> @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 16 x i8> @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 32 x i8> @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 32 x i1> %2,
     i32 %3)
 
   ret <vscale x 32 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     i8 9,
     i32 %1)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 64 x i8> @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8> %1,
-    i8 9,
+    i8 -9,
     <vscale x 64 x i1> %2,
     i32 %3)
 
   ret <vscale x 64 x i8> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 1 x i16> @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 2 x i16> @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 4 x i16> @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 8 x i16> @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 16 x i16> @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     i16 9,
     i32 %1)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 32 x i16> @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16> %1,
-    i16 9,
+    i16 -9,
     <vscale x 32 x i1> %2,
     i32 %3)
 
   ret <vscale x 32 x i16> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 1 x i32> @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 1 x i1> %2,
     i32 %3)
 
   ret <vscale x 1 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 2 x i32> @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 2 x i1> %2,
     i32 %3)
 
   ret <vscale x 2 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 4 x i32> @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 4 x i1> %2,
     i32 %3)
 
   ret <vscale x 4 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 8 x i32> @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 8 x i1> %2,
     i32 %3)
 
   ret <vscale x 8 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
 ; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
   %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     i32 9,
     i32 %1)
 
   ret <vscale x 16 x i32> %a
 }
 
 define <vscale x 16 x i32> @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+; CHECK:       vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t
   %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32> %1,
-    i32 9,
+    i32 -9,
     <vscale x 16 x i1> %2,
     i32 %3)
 
   ret <vscale x 16 x i32> %a
 }