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Differential D92008

[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
ClosedPublic

Authored by craig.topper on Nov 23 2020, 11:56 PM.

Details

Reviewers
asb
lenary
luismarques
frasercrmck
HsiangKai
Commits
rGa1ae3c6ac913: [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to…
Summary

If SETUNE isn't legal, UO can use the NOT of the SETO expansion.

Removes some complex isel patterns. Most of the test changes are
from using XORI instead of SEQZ.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 23 2020, 11:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 23 2020, 11:56 PM
Herald added subscribers: NickHung, evandro, apazos and 23 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 23 2020, 11:56 PM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 23 2020, 11:56 PM
Harbormaster completed remote builds in B79898: Diff 307255.Nov 24 2020, 12:35 AM
asb accepted this revision.Dec 10 2020, 5:09 AM

It's great to be able to drop those ugly patterns - nice cleanup. Thanks.

This revision is now accepted and ready to land.Dec 10 2020, 5:09 AM
This revision was landed with ongoing or failed builds.Dec 10 2020, 9:16 AM
Closed by commit rGa1ae3c6ac913: [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGa1ae3c6ac913: [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to….

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
13 lines
Target/
RISCV/
2 lines
17 lines
17 lines
test/
CodeGen/
RISCV/
12 lines
8 lines
4 lines
8 lines
12 lines
8 lines
4 lines
8 lines

Diff 307255

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

//===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===// //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 1,700 Lines • ▼ Show 20 Lines if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
std::swap(LHS, RHS); std::swap(LHS, RHS);
return true; return true;
} }
ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
unsigned Opc = 0; unsigned Opc = 0;
switch (CCCode) { switch (CCCode) {
default: llvm_unreachable("Don't know how to expand this condition!"); default: llvm_unreachable("Don't know how to expand this condition!");
case ISD::SETUO:
if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT)) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-        if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT)) {
-          CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR;
-          break;
-        }
-        assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
-            && "If SETUE is expanded, SETOEQ or SETUNE must be legal!");
-        NeedInvert = true;
-        LLVM_FALLTHROUGH;
+      if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT)) {
+        CC1 = ISD::SETUNE;

8 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT))…
CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR;
break;
}
assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
&& "If SETUE is expanded, SETOEQ or SETUNE must be legal!");
NeedInvert = true;
LLVM_FALLTHROUGH;
case ISD::SETO: case ISD::SETO:
assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
&& "If SETO is expanded, SETOEQ must be legal!"); && "If SETO is expanded, SETOEQ must be legal!");
CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break; CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
case ISD::SETUO:
assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
&& "If SETUO is expanded, SETUNE must be legal!");
CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
case ISD::SETOEQ: case ISD::SETOEQ:
case ISD::SETOGT: case ISD::SETOGT:
case ISD::SETOGE: case ISD::SETOGE:
case ISD::SETOLT: case ISD::SETOLT:
case ISD::SETOLE: case ISD::SETOLE:
case ISD::SETONE: case ISD::SETONE:
case ISD::SETUEQ: case ISD::SETUEQ:
case ISD::SETUNE: case ISD::SETUNE:
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 LinesRISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtZbt()) { if (Subtarget.hasStdExtZbt()) {
setOperationAction(ISD::FSHL, XLenVT, Legal); setOperationAction(ISD::FSHL, XLenVT, Legal);
setOperationAction(ISD::FSHR, XLenVT, Legal); setOperationAction(ISD::FSHR, XLenVT, Legal);
} }
ISD::CondCode FPCCToExtend[] = { ISD::CondCode FPCCToExtend[] = {
ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
ISD::SETGE, ISD::SETNE}; ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO};
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      ISD::SETGE,  ISD::SETNE, ISD::SETO, ISD::SETUO};
+      ISD::SETGE,  ISD::SETNE,  ISD::SETO,   ISD::SETUO};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ISD::SETGE, ISD::SETNE, ISD::SETO, ISD…
ISD::NodeType FPOpToExtend[] = { ISD::NodeType FPOpToExtend[] = {
ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
ISD::FP_TO_FP16}; ISD::FP_TO_FP16};
if (Subtarget.hasStdExtF()) { if (Subtarget.hasStdExtF()) {
setOperationAction(ISD::FMINNUM, MVT::f32, Legal); setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
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llvm/lib/Target/RISCV/RISCVInstrInfoD.td

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def : PatFpr64Fpr64<seteq, FEQ_D>; def : PatFpr64Fpr64<seteq, FEQ_D>;
def : PatFpr64Fpr64<setoeq, FEQ_D>; def : PatFpr64Fpr64<setoeq, FEQ_D>;
def : PatFpr64Fpr64<setlt, FLT_D>; def : PatFpr64Fpr64<setlt, FLT_D>;
def : PatFpr64Fpr64<setolt, FLT_D>; def : PatFpr64Fpr64<setolt, FLT_D>;
def : PatFpr64Fpr64<setle, FLE_D>; def : PatFpr64Fpr64<setle, FLE_D>;
def : PatFpr64Fpr64<setole, FLE_D>; def : PatFpr64Fpr64<setole, FLE_D>;
// Define pattern expansions for setcc operations which aren't directly
// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
// Legalizer.
def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
(AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
(FEQ_D FPR64:$rs2, FPR64:$rs2))>;
def : Pat<(seto FPR64:$rs1, FPR64:$rs1),
(FEQ_D $rs1, $rs1)>;
def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
(SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
(FEQ_D FPR64:$rs2, FPR64:$rs2)),
1)>;
def : Pat<(setuo FPR64:$rs1, FPR64:$rs1),
(SLTIU (FEQ_D $rs1, $rs1), 1)>;
def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>; def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
/// Loads /// Loads
defm : LdPat<load, FLD>; defm : LdPat<load, FLD>;
/// Stores /// Stores
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llvm/lib/Target/RISCV/RISCVInstrInfoF.td

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def : PatFpr32Fpr32<seteq, FEQ_S>; def : PatFpr32Fpr32<seteq, FEQ_S>;
def : PatFpr32Fpr32<setoeq, FEQ_S>; def : PatFpr32Fpr32<setoeq, FEQ_S>;
def : PatFpr32Fpr32<setlt, FLT_S>; def : PatFpr32Fpr32<setlt, FLT_S>;
def : PatFpr32Fpr32<setolt, FLT_S>; def : PatFpr32Fpr32<setolt, FLT_S>;
def : PatFpr32Fpr32<setle, FLE_S>; def : PatFpr32Fpr32<setle, FLE_S>;
def : PatFpr32Fpr32<setole, FLE_S>; def : PatFpr32Fpr32<setole, FLE_S>;
// Define pattern expansions for setcc operations which aren't directly
// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
// Legalizer.
def : Pat<(seto FPR32:$rs1, FPR32:$rs2),
(AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
(FEQ_S FPR32:$rs2, FPR32:$rs2))>;
def : Pat<(seto FPR32:$rs1, FPR32:$rs1),
(FEQ_S $rs1, $rs1)>;
def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
(SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
(FEQ_S FPR32:$rs2, FPR32:$rs2)),
1)>;
def : Pat<(setuo FPR32:$rs1, FPR32:$rs1),
(SLTIU (FEQ_S $rs1, $rs1), 1)>;
def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
/// Loads /// Loads
defm : LdPat<load, FLW>; defm : LdPat<load, FLW>;
/// Stores /// Stores
Show All 40 Lines

llvm/test/CodeGen/RISCV/double-br-fcmp.ll

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; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: and a1, a2, a1
; RV32IFD-NEXT: seqz a1, a1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: or a0, a0, a1 ; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB9_2 ; RV32IFD-NEXT: bnez a0, .LBB9_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB9_2: # %if.then ; RV32IFD-NEXT: .LBB9_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort
; ;
; RV64IFD-LABEL: br_fcmp_ueq: ; RV64IFD-LABEL: br_fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: feq.d a2, ft1, ft1 ; RV64IFD-NEXT: feq.d a2, ft1, ft1
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: and a1, a2, a1
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB9_2 ; RV64IFD-NEXT: bnez a0, .LBB9_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB9_2: # %if.then ; RV64IFD-NEXT: .LBB9_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort
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; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: addi a1, zero, 1
; RV32IFD-NEXT: bnez a0, .LBB15_2 ; RV32IFD-NEXT: bne a0, a1, .LBB15_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB15_2: # %if.then ; RV32IFD-NEXT: .LBB15_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort
; ;
; RV64IFD-LABEL: br_fcmp_uno: ; RV64IFD-LABEL: br_fcmp_uno:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: addi a1, zero, 1
; RV64IFD-NEXT: bnez a0, .LBB15_2 ; RV64IFD-NEXT: bne a0, a1, .LBB15_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB15_2: # %if.then ; RV64IFD-NEXT: .LBB15_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort
%1 = fcmp uno double %a, %b %1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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llvm/test/CodeGen/RISCV/double-fcmp.ll

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; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: and a1, a2, a1
; RV32IFD-NEXT: seqz a1, a1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: or a0, a0, a1 ; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcmp_ueq: ; RV64IFD-LABEL: fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: feq.d a2, ft1, ft1 ; RV64IFD-NEXT: feq.d a2, ft1, ft1
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: and a1, a2, a1
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ugt(double %a, double %b) nounwind { define i32 @fcmp_ugt(double %a, double %b) nounwind {
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; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcmp_uno: ; RV64IFD-LABEL: fcmp_uno:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, %b %1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_true(double %a, double %b) nounwind { define i32 @fcmp_true(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_true: ; RV32IFD-LABEL: fcmp_true:
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llvm/test/CodeGen/RISCV/double-isnan.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IFD %s ; RUN: < %s | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IFD %s ; RUN: < %s | FileCheck -check-prefix=RV64IFD %s
define zeroext i1 @double_is_nan(double %a) nounwind { define zeroext i1 @double_is_nan(double %a) nounwind {
; RV32IFD-LABEL: double_is_nan: ; RV32IFD-LABEL: double_is_nan:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: double_is_nan: ; RV64IFD-LABEL: double_is_nan:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, 0.000000e+00 %1 = fcmp uno double %a, 0.000000e+00
ret i1 %1 ret i1 %1
} }
define zeroext i1 @double_not_nan(double %a) nounwind { define zeroext i1 @double_not_nan(double %a) nounwind {
; RV32IFD-LABEL: double_not_nan: ; RV32IFD-LABEL: double_not_nan:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
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llvm/test/CodeGen/RISCV/double-select-fcmp.ll

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; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: and a1, a2, a1
; RV32IFD-NEXT: seqz a1, a1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: or a0, a0, a1 ; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB8_2 ; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft1, ft0 ; RV32IFD-NEXT: fmv.d ft1, ft0
; RV32IFD-NEXT: .LBB8_2: ; RV32IFD-NEXT: .LBB8_2:
; RV32IFD-NEXT: fsd ft1, 8(sp) ; RV32IFD-NEXT: fsd ft1, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: select_fcmp_ueq: ; RV64IFD-LABEL: select_fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft1 ; RV64IFD-NEXT: feq.d a0, ft0, ft1
; RV64IFD-NEXT: feq.d a1, ft1, ft1 ; RV64IFD-NEXT: feq.d a1, ft1, ft1
; RV64IFD-NEXT: feq.d a2, ft0, ft0 ; RV64IFD-NEXT: feq.d a2, ft0, ft0
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: and a1, a2, a1
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB8_2 ; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1 ; RV64IFD-NEXT: fmv.d ft0, ft1
; RV64IFD-NEXT: .LBB8_2: ; RV64IFD-NEXT: .LBB8_2:
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
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; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB14_2 ; RV32IFD-NEXT: bnez a0, .LBB14_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft0, ft1 ; RV32IFD-NEXT: fmv.d ft0, ft1
; RV32IFD-NEXT: .LBB14_2: ; RV32IFD-NEXT: .LBB14_2:
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: select_fcmp_uno: ; RV64IFD-LABEL: select_fcmp_uno:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB14_2 ; RV64IFD-NEXT: bnez a0, .LBB14_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1 ; RV64IFD-NEXT: fmv.d ft0, ft1
; RV64IFD-NEXT: .LBB14_2: ; RV64IFD-NEXT: .LBB14_2:
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, %b %1 = fcmp uno double %a, %b
%2 = select i1 %1, double %a, double %b %2 = select i1 %1, double %a, double %b
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llvm/test/CodeGen/RISCV/float-br-fcmp.ll

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; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: feq.s a2, ft1, ft1 ; RV32IF-NEXT: feq.s a2, ft1, ft1
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: or a0, a0, a1 ; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB9_2 ; RV32IF-NEXT: bnez a0, .LBB9_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB9_2: # %if.then ; RV32IF-NEXT: .LBB9_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort
; ;
; RV64IF-LABEL: br_fcmp_ueq: ; RV64IF-LABEL: br_fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: feq.s a2, ft1, ft1 ; RV64IF-NEXT: feq.s a2, ft1, ft1
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: and a1, a2, a1
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: or a0, a0, a1 ; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB9_2 ; RV64IF-NEXT: bnez a0, .LBB9_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB9_2: # %if.then ; RV64IF-NEXT: .LBB9_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort
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; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: addi a1, zero, 1
; RV32IF-NEXT: bnez a0, .LBB15_2 ; RV32IF-NEXT: bne a0, a1, .LBB15_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB15_2: # %if.then ; RV32IF-NEXT: .LBB15_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort
; ;
; RV64IF-LABEL: br_fcmp_uno: ; RV64IF-LABEL: br_fcmp_uno:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: addi a1, zero, 1
; RV64IF-NEXT: bnez a0, .LBB15_2 ; RV64IF-NEXT: bne a0, a1, .LBB15_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB15_2: # %if.then ; RV64IF-NEXT: .LBB15_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort
%1 = fcmp uno float %a, %b %1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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llvm/test/CodeGen/RISCV/float-fcmp.ll

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; RV32IF-LABEL: fcmp_ueq: ; RV32IF-LABEL: fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: feq.s a2, ft1, ft1 ; RV32IF-NEXT: feq.s a2, ft1, ft1
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: or a0, a0, a1 ; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcmp_ueq: ; RV64IF-LABEL: fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: feq.s a2, ft1, ft1 ; RV64IF-NEXT: feq.s a2, ft1, ft1
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: and a1, a2, a1
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: or a0, a0, a1 ; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ugt(float %a, float %b) nounwind { define i32 @fcmp_ugt(float %a, float %b) nounwind {
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define i32 @fcmp_uno(float %a, float %b) nounwind { define i32 @fcmp_uno(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_uno: ; RV32IF-LABEL: fcmp_uno:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcmp_uno: ; RV64IF-LABEL: fcmp_uno:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp uno float %a, %b %1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_true(float %a, float %b) nounwind { define i32 @fcmp_true(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_true: ; RV32IF-LABEL: fcmp_true:
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llvm/test/CodeGen/RISCV/float-isnan.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IF %s ; RUN: < %s | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IF %s ; RUN: < %s | FileCheck -check-prefix=RV64IF %s
define zeroext i1 @float_is_nan(float %a) nounwind { define zeroext i1 @float_is_nan(float %a) nounwind {
; RV32IF-LABEL: float_is_nan: ; RV32IF-LABEL: float_is_nan:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0 ; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: float_is_nan: ; RV64IF-LABEL: float_is_nan:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0 ; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp uno float %a, 0.000000e+00 %1 = fcmp uno float %a, 0.000000e+00
ret i1 %1 ret i1 %1
} }
define zeroext i1 @float_not_nan(float %a) nounwind { define zeroext i1 @float_not_nan(float %a) nounwind {
; RV32IF-LABEL: float_not_nan: ; RV32IF-LABEL: float_not_nan:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
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llvm/test/CodeGen/RISCV/float-select-fcmp.ll

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; RV32IF-LABEL: select_fcmp_ueq: ; RV32IF-LABEL: select_fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: feq.s a1, ft1, ft1 ; RV32IF-NEXT: feq.s a1, ft1, ft1
; RV32IF-NEXT: feq.s a2, ft0, ft0 ; RV32IF-NEXT: feq.s a2, ft0, ft0
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: or a0, a0, a1 ; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB8_2 ; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1 ; RV32IF-NEXT: fmv.s ft0, ft1
; RV32IF-NEXT: .LBB8_2: ; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: select_fcmp_ueq: ; RV64IF-LABEL: select_fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft1 ; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: feq.s a1, ft1, ft1 ; RV64IF-NEXT: feq.s a1, ft1, ft1
; RV64IF-NEXT: feq.s a2, ft0, ft0 ; RV64IF-NEXT: feq.s a2, ft0, ft0
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: and a1, a2, a1
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: or a0, a0, a1 ; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB8_2 ; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1 ; RV64IF-NEXT: fmv.s ft0, ft1
; RV64IF-NEXT: .LBB8_2: ; RV64IF-NEXT: .LBB8_2:
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
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; TODO: sltiu+bne could be optimized ; TODO: sltiu+bne could be optimized
; RV32IF-LABEL: select_fcmp_uno: ; RV32IF-LABEL: select_fcmp_uno:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB14_2 ; RV32IF-NEXT: bnez a0, .LBB14_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1 ; RV32IF-NEXT: fmv.s ft0, ft1
; RV32IF-NEXT: .LBB14_2: ; RV32IF-NEXT: .LBB14_2:
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: select_fcmp_uno: ; RV64IF-LABEL: select_fcmp_uno:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB14_2 ; RV64IF-NEXT: bnez a0, .LBB14_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1 ; RV64IF-NEXT: fmv.s ft0, ft1
; RV64IF-NEXT: .LBB14_2: ; RV64IF-NEXT: .LBB14_2:
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp uno float %a, %b %1 = fcmp uno float %a, %b
%2 = select i1 %1, float %a, float %b %2 = select i1 %1, float %a, float %b
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