[RISCV] Do not grow the stack a second time when we need to realign the stack

[rogfer01]

Summary

This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change.

This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout.

My understanding is that we don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this (see https://github.com/llvm/llvm-project/blob/539381da26096df54ccf862088c8242498a7dcae/llvm/lib/CodeGen/PrologEpilogInserter.cpp#L1085 ) with the right size accounting the extra alignment as kept in MaxAlign (see https://github.com/llvm/llvm-project/blob/539381da26096df54ccf862088c8242498a7dcae/llvm/lib/CodeGen/PrologEpilogInserter.cpp#L1079 ).

[lenary]

I thought we were over-allocating stack frame sizes, but I hadn't had time to investigate this properly, thanks for the thorough investigation Roger!

(There's a comment about some of the same issues in one of the other backends, but I cannot find it, I can find my incorrect fix though: D65959, since abandoned).

[luismarques]

LGTM. Thanks for the detailed description, with the links.

[asb]

Thanks Roger, this looks good to me and doesn't seem to break anything in the GCC torture suite at least.

[HsiangKai]

LGTM.

[rogfer01]

ChangeLog:

• Rebase patch prior committing

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

bool RISCVFrameLowering::hasBP(const MachineFunction &MF) const {
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
   return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
 }
 
 // Determines the size of the frame and maximum call frame size.
 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
-  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
 
   // Get the number of bytes to allocate from the FrameInfo.
   uint64_t FrameSize = MFI.getStackSize();
 
   // Get the alignment.
   Align StackAlign = getStackAlign();
-  if (RI->needsStackRealignment(MF)) {
-    Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
-    FrameSize += (MaxStackAlign.value() - StackAlign.value());
-    StackAlign = MaxStackAlign;
-  }
 
   // Set Max Call Frame Size
   uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign);
   MFI.setMaxCallFrameSize(MaxCallSize);
 
   // Make sure the frame is aligned.
   FrameSize = alignTo(FrameSize, StackAlign);
 

llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 
 declare void @callee(i8*, i32*)
 
 define void @caller(i32 %n) {
 ; RV32I-LABEL: caller:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -128
-; RV32I-NEXT:    .cfi_def_cfa_offset 128
-; RV32I-NEXT:    sw ra, 124(sp)
-; RV32I-NEXT:    sw s0, 120(sp)
-; RV32I-NEXT:    sw s1, 116(sp)
+; RV32I-NEXT:    addi sp, sp, -64
+; RV32I-NEXT:    .cfi_def_cfa_offset 64
+; RV32I-NEXT:    sw ra, 60(sp)
+; RV32I-NEXT:    sw s0, 56(sp)
+; RV32I-NEXT:    sw s1, 52(sp)
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    .cfi_offset s0, -8
 ; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    addi s0, sp, 128
+; RV32I-NEXT:    addi s0, sp, 64
 ; RV32I-NEXT:    .cfi_def_cfa s0, 0
 ; RV32I-NEXT:    andi sp, sp, -64
 ; RV32I-NEXT:    mv s1, sp
 ; RV32I-NEXT:    addi a0, a0, 15
 ; RV32I-NEXT:    andi a0, a0, -16
 ; RV32I-NEXT:    sub a0, sp, a0
 ; RV32I-NEXT:    mv sp, a0
-; RV32I-NEXT:    addi a1, s1, 64
+; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -128
-; RV32I-NEXT:    lw s1, 116(sp)
-; RV32I-NEXT:    lw s0, 120(sp)
-; RV32I-NEXT:    lw ra, 124(sp)
-; RV32I-NEXT:    addi sp, sp, 128
+; RV32I-NEXT:    addi sp, s0, -64
+; RV32I-NEXT:    lw s1, 52(sp)
+; RV32I-NEXT:    lw s0, 56(sp)
+; RV32I-NEXT:    lw ra, 60(sp)
+; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -128
-; RV64I-NEXT:    .cfi_def_cfa_offset 128
-; RV64I-NEXT:    sd ra, 120(sp)
-; RV64I-NEXT:    sd s0, 112(sp)
-; RV64I-NEXT:    sd s1, 104(sp)
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    .cfi_def_cfa_offset 64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    sd s1, 40(sp)
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    .cfi_offset s0, -16
 ; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    addi s0, sp, 128
+; RV64I-NEXT:    addi s0, sp, 64
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -64
 ; RV64I-NEXT:    mv s1, sp
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    addi a0, a0, 15
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 33
 ; RV64I-NEXT:    addi a1, a1, -16
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    sub a0, sp, a0
 ; RV64I-NEXT:    mv sp, a0
-; RV64I-NEXT:    addi a1, s1, 64
+; RV64I-NEXT:    mv a1, s1
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -128
-; RV64I-NEXT:    ld s1, 104(sp)
-; RV64I-NEXT:    ld s0, 112(sp)
-; RV64I-NEXT:    ld ra, 120(sp)
-; RV64I-NEXT:    addi sp, sp, 128
+; RV64I-NEXT:    addi sp, s0, -64
+; RV64I-NEXT:    ld s1, 40(sp)
+; RV64I-NEXT:    ld s0, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
   %1 = alloca i8, i32 %n
   %2 = alloca i32, align 64
   call void @callee(i8* %1, i32 *%2)
   ret void
 }

llvm/test/CodeGen/RISCV/stack-realignment.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 
 declare void @callee(i8*)
 
 define void @caller32() nounwind {
 ; RV32I-LABEL: caller32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -64
-; RV32I-NEXT:    sw ra, 60(sp)
-; RV32I-NEXT:    sw s0, 56(sp)
-; RV32I-NEXT:    addi s0, sp, 64
+; RV32I-NEXT:    addi sp, sp, -32
+; RV32I-NEXT:    sw ra, 28(sp)
+; RV32I-NEXT:    sw s0, 24(sp)
+; RV32I-NEXT:    addi s0, sp, 32
 ; RV32I-NEXT:    andi sp, sp, -32
-; RV32I-NEXT:    addi a0, sp, 32
+; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -64
-; RV32I-NEXT:    lw s0, 56(sp)
-; RV32I-NEXT:    lw ra, 60(sp)
-; RV32I-NEXT:    addi sp, sp, 64
+; RV32I-NEXT:    addi sp, s0, -32
+; RV32I-NEXT:    lw s0, 24(sp)
+; RV32I-NEXT:    lw ra, 28(sp)
+; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
-; RV64I-NEXT:    sd s0, 48(sp)
-; RV64I-NEXT:    addi s0, sp, 64
+; RV64I-NEXT:    addi sp, sp, -32
+; RV64I-NEXT:    sd ra, 24(sp)
+; RV64I-NEXT:    sd s0, 16(sp)
+; RV64I-NEXT:    addi s0, sp, 32
 ; RV64I-NEXT:    andi sp, sp, -32
-; RV64I-NEXT:    addi a0, sp, 32
+; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -64
-; RV64I-NEXT:    ld s0, 48(sp)
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    addi sp, s0, -32
+; RV64I-NEXT:    ld s0, 16(sp)
+; RV64I-NEXT:    ld ra, 24(sp)
+; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 32
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign32() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign32:
; RV64I-NEXT:    ret
   %1 = alloca i8, align 32
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller64() nounwind {
 ; RV32I-LABEL: caller64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -128
-; RV32I-NEXT:    sw ra, 124(sp)
-; RV32I-NEXT:    sw s0, 120(sp)
-; RV32I-NEXT:    addi s0, sp, 128
+; RV32I-NEXT:    addi sp, sp, -64
+; RV32I-NEXT:    sw ra, 60(sp)
+; RV32I-NEXT:    sw s0, 56(sp)
+; RV32I-NEXT:    addi s0, sp, 64
 ; RV32I-NEXT:    andi sp, sp, -64
-; RV32I-NEXT:    addi a0, sp, 64
+; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -128
-; RV32I-NEXT:    lw s0, 120(sp)
-; RV32I-NEXT:    lw ra, 124(sp)
-; RV32I-NEXT:    addi sp, sp, 128
+; RV32I-NEXT:    addi sp, s0, -64
+; RV32I-NEXT:    lw s0, 56(sp)
+; RV32I-NEXT:    lw ra, 60(sp)
+; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -128
-; RV64I-NEXT:    sd ra, 120(sp)
-; RV64I-NEXT:    sd s0, 112(sp)
-; RV64I-NEXT:    addi s0, sp, 128
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s0, 48(sp)
+; RV64I-NEXT:    addi s0, sp, 64
 ; RV64I-NEXT:    andi sp, sp, -64
-; RV64I-NEXT:    addi a0, sp, 64
+; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -128
-; RV64I-NEXT:    ld s0, 112(sp)
-; RV64I-NEXT:    ld ra, 120(sp)
-; RV64I-NEXT:    addi sp, sp, 128
+; RV64I-NEXT:    addi sp, s0, -64
+; RV64I-NEXT:    ld s0, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 64
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign64() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign64:
; RV64I-NEXT:    ret
   %1 = alloca i8, align 64
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller128() nounwind {
 ; RV32I-LABEL: caller128:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -256
-; RV32I-NEXT:    sw ra, 252(sp)
-; RV32I-NEXT:    sw s0, 248(sp)
-; RV32I-NEXT:    addi s0, sp, 256
+; RV32I-NEXT:    addi sp, sp, -128
+; RV32I-NEXT:    sw ra, 124(sp)
+; RV32I-NEXT:    sw s0, 120(sp)
+; RV32I-NEXT:    addi s0, sp, 128
 ; RV32I-NEXT:    andi sp, sp, -128
-; RV32I-NEXT:    addi a0, sp, 128
+; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -256
-; RV32I-NEXT:    lw s0, 248(sp)
-; RV32I-NEXT:    lw ra, 252(sp)
-; RV32I-NEXT:    addi sp, sp, 256
+; RV32I-NEXT:    addi sp, s0, -128
+; RV32I-NEXT:    lw s0, 120(sp)
+; RV32I-NEXT:    lw ra, 124(sp)
+; RV32I-NEXT:    addi sp, sp, 128
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller128:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -256
-; RV64I-NEXT:    sd ra, 248(sp)
-; RV64I-NEXT:    sd s0, 240(sp)
-; RV64I-NEXT:    addi s0, sp, 256
+; RV64I-NEXT:    addi sp, sp, -128
+; RV64I-NEXT:    sd ra, 120(sp)
+; RV64I-NEXT:    sd s0, 112(sp)
+; RV64I-NEXT:    addi s0, sp, 128
 ; RV64I-NEXT:    andi sp, sp, -128
-; RV64I-NEXT:    addi a0, sp, 128
+; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -256
-; RV64I-NEXT:    ld s0, 240(sp)
-; RV64I-NEXT:    ld ra, 248(sp)
-; RV64I-NEXT:    addi sp, sp, 256
+; RV64I-NEXT:    addi sp, s0, -128
+; RV64I-NEXT:    ld s0, 112(sp)
+; RV64I-NEXT:    ld ra, 120(sp)
+; RV64I-NEXT:    addi sp, sp, 128
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 128
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign128() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign128:
; RV64I-NEXT:    ret
   %1 = alloca i8, align 128
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller256() nounwind {
 ; RV32I-LABEL: caller256:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -512
-; RV32I-NEXT:    sw ra, 508(sp)
-; RV32I-NEXT:    sw s0, 504(sp)
-; RV32I-NEXT:    addi s0, sp, 512
+; RV32I-NEXT:    addi sp, sp, -256
+; RV32I-NEXT:    sw ra, 252(sp)
+; RV32I-NEXT:    sw s0, 248(sp)
+; RV32I-NEXT:    addi s0, sp, 256
 ; RV32I-NEXT:    andi sp, sp, -256
-; RV32I-NEXT:    addi a0, sp, 256
+; RV32I-NEXT:    mv a0, sp
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -512
-; RV32I-NEXT:    lw s0, 504(sp)
-; RV32I-NEXT:    lw ra, 508(sp)
-; RV32I-NEXT:    addi sp, sp, 512
+; RV32I-NEXT:    addi sp, s0, -256
+; RV32I-NEXT:    lw s0, 248(sp)
+; RV32I-NEXT:    lw ra, 252(sp)
+; RV32I-NEXT:    addi sp, sp, 256
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller256:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -512
-; RV64I-NEXT:    sd ra, 504(sp)
-; RV64I-NEXT:    sd s0, 496(sp)
-; RV64I-NEXT:    addi s0, sp, 512
+; RV64I-NEXT:    addi sp, sp, -256
+; RV64I-NEXT:    sd ra, 248(sp)
+; RV64I-NEXT:    sd s0, 240(sp)
+; RV64I-NEXT:    addi s0, sp, 256
 ; RV64I-NEXT:    andi sp, sp, -256
-; RV64I-NEXT:    addi a0, sp, 256
+; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -512
-; RV64I-NEXT:    ld s0, 496(sp)
-; RV64I-NEXT:    ld ra, 504(sp)
-; RV64I-NEXT:    addi sp, sp, 512
+; RV64I-NEXT:    addi sp, s0, -256
+; RV64I-NEXT:    ld s0, 240(sp)
+; RV64I-NEXT:    ld ra, 248(sp)
+; RV64I-NEXT:    addi sp, sp, 256
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 256
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign256() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign256:
; RV64I-NEXT:    ret
   %1 = alloca i8, align 256
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller512() nounwind {
 ; RV32I-LABEL: caller512:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -1536
-; RV32I-NEXT:    sw ra, 1532(sp)
-; RV32I-NEXT:    sw s0, 1528(sp)
-; RV32I-NEXT:    addi s0, sp, 1536
+; RV32I-NEXT:    addi sp, sp, -1024
+; RV32I-NEXT:    sw ra, 1020(sp)
+; RV32I-NEXT:    sw s0, 1016(sp)
+; RV32I-NEXT:    addi s0, sp, 1024
 ; RV32I-NEXT:    andi sp, sp, -512
-; RV32I-NEXT:    addi a0, sp, 1024
+; RV32I-NEXT:    addi a0, sp, 512
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -1536
-; RV32I-NEXT:    lw s0, 1528(sp)
-; RV32I-NEXT:    lw ra, 1532(sp)
-; RV32I-NEXT:    addi sp, sp, 1536
+; RV32I-NEXT:    addi sp, s0, -1024
+; RV32I-NEXT:    lw s0, 1016(sp)
+; RV32I-NEXT:    lw ra, 1020(sp)
+; RV32I-NEXT:    addi sp, sp, 1024
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller512:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -1536
-; RV64I-NEXT:    sd ra, 1528(sp)
-; RV64I-NEXT:    sd s0, 1520(sp)
-; RV64I-NEXT:    addi s0, sp, 1536
+; RV64I-NEXT:    addi sp, sp, -1024
+; RV64I-NEXT:    sd ra, 1016(sp)
+; RV64I-NEXT:    sd s0, 1008(sp)
+; RV64I-NEXT:    addi s0, sp, 1024
 ; RV64I-NEXT:    andi sp, sp, -512
-; RV64I-NEXT:    addi a0, sp, 1024
+; RV64I-NEXT:    addi a0, sp, 512
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -1536
-; RV64I-NEXT:    ld s0, 1520(sp)
-; RV64I-NEXT:    ld ra, 1528(sp)
-; RV64I-NEXT:    addi sp, sp, 1536
+; RV64I-NEXT:    addi sp, s0, -1024
+; RV64I-NEXT:    ld s0, 1008(sp)
+; RV64I-NEXT:    ld ra, 1016(sp)
+; RV64I-NEXT:    addi sp, sp, 1024
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 512
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign512() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign512:

 
 define void @caller1024() nounwind {
 ; RV32I-LABEL: caller1024:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp)
 ; RV32I-NEXT:    sw s0, 2024(sp)
 ; RV32I-NEXT:    addi s0, sp, 2032
-; RV32I-NEXT:    addi sp, sp, -1040
+; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    andi sp, sp, -1024
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -2048
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    mv a0, a0
+; RV32I-NEXT:    addi a0, sp, 1024
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
-; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    addi sp, sp, 1040
+; RV32I-NEXT:    addi sp, s0, -2048
+; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller1024:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    sd ra, 2024(sp)
 ; RV64I-NEXT:    sd s0, 2016(sp)
 ; RV64I-NEXT:    addi s0, sp, 2032
-; RV64I-NEXT:    addi sp, sp, -1040
+; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    andi sp, sp, -1024
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, -2048
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    mv a0, a0
+; RV64I-NEXT:    addi a0, sp, 1024
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, -1024
-; RV64I-NEXT:    sub sp, s0, a0
-; RV64I-NEXT:    addi sp, sp, 1040
+; RV64I-NEXT:    addi sp, s0, -2048
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ld s0, 2016(sp)
 ; RV64I-NEXT:    ld ra, 2024(sp)
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(i8* %1)
   ret void
 }

 define void @caller2048() nounwind {
 ; RV32I-LABEL: caller2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp)
 ; RV32I-NEXT:    sw s0, 2024(sp)
 ; RV32I-NEXT:    addi s0, sp, 2032
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -2048
 ; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    sd ra, 2024(sp)
 ; RV64I-NEXT:    sd s0, 2016(sp)
 ; RV64I-NEXT:    addi s0, sp, 2032
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -2048
 ; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addiw a0, a0, -2048
+; RV64I-NEXT:    lui a0, 1
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ld s0, 2016(sp)
 ; RV64I-NEXT:    ld ra, 2024(sp)
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(i8* %1)
   ret void

 
 define void @caller4096() nounwind {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp)
 ; RV32I-NEXT:    sw s0, 2024(sp)
 ; RV32I-NEXT:    addi s0, sp, 2032
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
-; RV32I-NEXT:    lui a0, 2
+; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    sd ra, 2024(sp)
 ; RV64I-NEXT:    sd s0, 2016(sp)
 ; RV64I-NEXT:    addi s0, sp, 2032
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    srli a0, sp, 12
 ; RV64I-NEXT:    slli sp, a0, 12
-; RV64I-NEXT:    lui a0, 2
+; RV64I-NEXT:    lui a0, 1
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    sub sp, s0, a0
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ld s0, 2016(sp)
 ; RV64I-NEXT:    ld ra, 2024(sp)
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 4096
   call void @callee(i8* %1)