[RISCV] Implement targetHandlesStackFrameRounding to prevent stack over-allocation

[lenary]

Summary

TargetFrameLowering contains a callback for telling LLVM that a target
will do its own stack frame size rounding. This defaults to false.

In the RISC-V backend, we have been doing our own stack frame size rounding,
without overriding this callback. This has been leading to over-allocation,
which this patch aims to mitigate. In almost all cases of aligned objects on the
stack, stack usage has decreased.

[asb]

This causes failures on the GCC torture suite:

$ cat output_rv64imafdc_lp64_O0/runfail 
920501-8
991216-1
991216-2
complex-7
multi-ix
pr27073
pr64979
struct-ret-1
va-arg-10
va-arg-12
va-arg-15
va-arg-16
va-arg-17
va-arg-18
va-arg-19
va-arg-1
va-arg-22
va-arg-23
va-arg-24
va-arg-2
va-arg-5
va-arg-6
va-arg-9

$ cat output_rv32imafdc_ilp32_O0/runfail
920501-8
991216-1
991216-2
multi-ix
pr23324
pr27073
pr44942
pr64979
stdarg-4
va-arg-10
va-arg-15
va-arg-19
va-arg-22
va-arg-24
va-arg-2
va-arg-6
va-arg-9

Fewer failures at higher optimisation levels.

llvm/lib/Target/RISCV/RISCVFrameLowering.h

public:
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
 
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                            RegScavenger *RS) const override;
 
   bool hasFP(const MachineFunction &MF) const override;
 
+  bool targetHandlesStackFrameRounding() const override { return true; }
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override;
 
 protected:
   const RISCVSubtarget &STI;
 
 private:
   void determineFrameLayout(MachineFunction &MF) const;
   void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
                  int64_t Val, MachineInstr::MIFlag Flag) const;
 };
 }
 #endif

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll

; RV32I-WITHFP-NEXT:    ret
   ret i32 %10
 }
 
 define void @caller_aligned_stack() nounwind {
 ; The double should be 8-byte aligned on the stack, but the two-element array
 ; should only be 4-byte aligned
 ; RV32I-FPELIM-LABEL: caller_aligned_stack:
 ; RV32I-FPELIM:       # %bb.0:
-; RV32I-FPELIM-NEXT:    addi sp, sp, -64
-; RV32I-FPELIM-NEXT:    sw ra, 60(sp)
+; RV32I-FPELIM-NEXT:    addi sp, sp, -32
+; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 18
 ; RV32I-FPELIM-NEXT:    sw a0, 24(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 17
 ; RV32I-FPELIM-NEXT:    sw a0, 20(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 16
 ; RV32I-FPELIM-NEXT:    sw a0, 16(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 262236
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 655
 ; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 377487
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1475
 ; RV32I-FPELIM-NEXT:    sw a0, 8(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 15
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 262153
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 491
-; RV32I-FPELIM-NEXT:    sw a0, 44(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 545260
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -1967
-; RV32I-FPELIM-NEXT:    sw a0, 40(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 964690
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -328
-; RV32I-FPELIM-NEXT:    sw a0, 36(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 335544
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1311
-; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 688509
 ; RV32I-FPELIM-NEXT:    addi a5, a0, -2048
-; RV32I-FPELIM-NEXT:    addi a2, sp, 32
+; RV32I-FPELIM-NEXT:    mv a2, sp
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 11
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 14
 ; RV32I-FPELIM-NEXT:    call callee_aligned_stack
-; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
-; RV32I-FPELIM-NEXT:    addi sp, sp, 64
+; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
+; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_aligned_stack:
 ; RV32I-WITHFP:       # %bb.0:
-; RV32I-WITHFP-NEXT:    addi sp, sp, -64
-; RV32I-WITHFP-NEXT:    sw ra, 60(sp)
-; RV32I-WITHFP-NEXT:    sw s0, 56(sp)
-; RV32I-WITHFP-NEXT:    addi s0, sp, 64
+; RV32I-WITHFP-NEXT:    addi sp, sp, -32
+; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
+; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
+; RV32I-WITHFP-NEXT:    addi s0, sp, 32
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 18
 ; RV32I-WITHFP-NEXT:    sw a0, 24(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 17
 ; RV32I-WITHFP-NEXT:    sw a0, 20(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 16
 ; RV32I-WITHFP-NEXT:    sw a0, 16(sp)
 ; RV32I-WITHFP-NEXT:    lui a0, 262236
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 655

 ; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 11
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 14
 ; RV32I-WITHFP-NEXT:    call callee_aligned_stack
-; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
-; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
-; RV32I-WITHFP-NEXT:    addi sp, sp, 64
+; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
+; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
+; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
     i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
     [2 x i32] [i32 17, i32 18])
   ret void
 }
 

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

; RV32I-WITHFP-NEXT:    ret
   %1 = icmp eq i128 %h, %j_bitcast
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-FPELIM-LABEL: caller_large_scalars_exhausted_regs:
 ; RV32I-FPELIM:       # %bb.0:
-; RV32I-FPELIM-NEXT:    addi sp, sp, -64
-; RV32I-FPELIM-NEXT:    sw ra, 60(sp)
-; RV32I-FPELIM-NEXT:    addi a0, sp, 16
+; RV32I-FPELIM-NEXT:    addi sp, sp, -48
+; RV32I-FPELIM-NEXT:    sw ra, 44(sp)
+; RV32I-FPELIM-NEXT:    mv a0, sp
 ; RV32I-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 9
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 524272
-; RV32I-FPELIM-NEXT:    sw a0, 28(sp)
-; RV32I-FPELIM-NEXT:    sw zero, 24(sp)
-; RV32I-FPELIM-NEXT:    sw zero, 20(sp)
-; RV32I-FPELIM-NEXT:    sw zero, 16(sp)
-; RV32I-FPELIM-NEXT:    sw zero, 52(sp)
-; RV32I-FPELIM-NEXT:    sw zero, 48(sp)
-; RV32I-FPELIM-NEXT:    sw zero, 44(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
+; RV32I-FPELIM-NEXT:    sw zero, 8(sp)
+; RV32I-FPELIM-NEXT:    sw zero, 4(sp)
+; RV32I-FPELIM-NEXT:    sw zero, 0(sp)
+; RV32I-FPELIM-NEXT:    sw zero, 36(sp)
+; RV32I-FPELIM-NEXT:    sw zero, 32(sp)
+; RV32I-FPELIM-NEXT:    sw zero, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 8
-; RV32I-FPELIM-NEXT:    sw a0, 40(sp)
-; RV32I-FPELIM-NEXT:    addi a7, sp, 40
+; RV32I-FPELIM-NEXT:    sw a0, 24(sp)
+; RV32I-FPELIM-NEXT:    addi a7, sp, 24
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a2, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 5
 ; RV32I-FPELIM-NEXT:    addi a5, zero, 6
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 7
 ; RV32I-FPELIM-NEXT:    call callee_large_scalars_exhausted_regs
-; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
-; RV32I-FPELIM-NEXT:    addi sp, sp, 64
+; RV32I-FPELIM-NEXT:    lw ra, 44(sp)
+; RV32I-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
 ; RV32I-WITHFP:       # %bb.0:
-; RV32I-WITHFP-NEXT:    addi sp, sp, -64
-; RV32I-WITHFP-NEXT:    sw ra, 60(sp)
-; RV32I-WITHFP-NEXT:    sw s0, 56(sp)
-; RV32I-WITHFP-NEXT:    addi s0, sp, 64
+; RV32I-WITHFP-NEXT:    addi sp, sp, -48
+; RV32I-WITHFP-NEXT:    sw ra, 44(sp)
+; RV32I-WITHFP-NEXT:    sw s0, 40(sp)
+; RV32I-WITHFP-NEXT:    addi s0, sp, 48
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -48
 ; RV32I-WITHFP-NEXT:    sw a0, 4(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 9
 ; RV32I-WITHFP-NEXT:    sw a0, 0(sp)
 ; RV32I-WITHFP-NEXT:    lui a0, 524272
 ; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -40(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -44(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -48(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -12(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -16(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 8
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
 ; RV32I-WITHFP-NEXT:    addi a7, s0, -24
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a2, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 5
 ; RV32I-WITHFP-NEXT:    addi a5, zero, 6
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 7
 ; RV32I-WITHFP-NEXT:    call callee_large_scalars_exhausted_regs
-; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
-; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
-; RV32I-WITHFP-NEXT:    addi sp, sp, 64
+; RV32I-WITHFP-NEXT:    lw s0, 40(sp)
+; RV32I-WITHFP-NEXT:    lw ra, 44(sp)
+; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_large_scalars_exhausted_regs(
       i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
       fp128 0xL00000000000000007FFF000000000000)
   ret i32 %1
 }
 
 ; Ensure that libcalls generated in the middle-end obey the calling convention
; RV32I-WITHFP-NEXT:    ret
   ret i32 %9
 }
 
 define void @caller_aligned_stack() nounwind {
 ; The i64 should be 8-byte aligned on the stack, but the two-element array
 ; should only be 4-byte aligned
 ; RV32I-FPELIM-LABEL: caller_aligned_stack:
 ; RV32I-FPELIM:       # %bb.0:
-; RV32I-FPELIM-NEXT:    addi sp, sp, -64
-; RV32I-FPELIM-NEXT:    sw ra, 60(sp)
+; RV32I-FPELIM-NEXT:    addi sp, sp, -32
+; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 19
 ; RV32I-FPELIM-NEXT:    sw a0, 24(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 18
 ; RV32I-FPELIM-NEXT:    sw a0, 20(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 17
 ; RV32I-FPELIM-NEXT:    sw a0, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 16
 ; RV32I-FPELIM-NEXT:    sw a0, 8(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 15
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 262153
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 491
-; RV32I-FPELIM-NEXT:    sw a0, 44(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 545260
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -1967
-; RV32I-FPELIM-NEXT:    sw a0, 40(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 8(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 964690
 ; RV32I-FPELIM-NEXT:    addi a0, a0, -328
-; RV32I-FPELIM-NEXT:    sw a0, 36(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 335544
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1311
-; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
+; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, 688509
 ; RV32I-FPELIM-NEXT:    addi a5, a0, -2048
-; RV32I-FPELIM-NEXT:    addi a2, sp, 32
+; RV32I-FPELIM-NEXT:    mv a2, sp
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 11
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 14
 ; RV32I-FPELIM-NEXT:    call callee_aligned_stack
-; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
-; RV32I-FPELIM-NEXT:    addi sp, sp, 64
+; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
+; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_aligned_stack:
 ; RV32I-WITHFP:       # %bb.0:
-; RV32I-WITHFP-NEXT:    addi sp, sp, -64
-; RV32I-WITHFP-NEXT:    sw ra, 60(sp)
-; RV32I-WITHFP-NEXT:    sw s0, 56(sp)
-; RV32I-WITHFP-NEXT:    addi s0, sp, 64
+; RV32I-WITHFP-NEXT:    addi sp, sp, -32
+; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
+; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
+; RV32I-WITHFP-NEXT:    addi s0, sp, 32
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 19
 ; RV32I-WITHFP-NEXT:    sw a0, 24(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 18
 ; RV32I-WITHFP-NEXT:    sw a0, 20(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 17
 ; RV32I-WITHFP-NEXT:    sw a0, 16(sp)
 ; RV32I-WITHFP-NEXT:    sw zero, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 16

 ; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 11
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 14
 ; RV32I-WITHFP-NEXT:    call callee_aligned_stack
-; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
-; RV32I-WITHFP-NEXT:    lw ra, 60(sp)
-; RV32I-WITHFP-NEXT:    addi sp, sp, 64
+; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
+; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
+; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
     i64 20000000000, i32 14, i32 15, i64 16, i32 17,
     [2 x i32] [i32 18, i32 19])
   ret void
 }
 

llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll

; RV64I-NEXT:    ret
   %7 = add i32 %6, %f
   %8 = add i32 %7, %h
   ret i32 %8
 }
 
 define i32 @caller_many_scalars() nounwind {
 ; RV64I-LABEL: caller_many_scalars:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    sd ra, 24(sp)
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a0, zero, 8
 ; RV64I-NEXT:    sd a0, 8(sp)
 ; RV64I-NEXT:    sd zero, 0(sp)
 ; RV64I-NEXT:    addi a0, zero, 1
 ; RV64I-NEXT:    addi a1, zero, 2
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    addi a5, zero, 5
 ; RV64I-NEXT:    addi a6, zero, 6
 ; RV64I-NEXT:    addi a7, zero, 7
 ; RV64I-NEXT:    call callee_many_scalars
-; RV64I-NEXT:    ld ra, 24(sp)
-; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8)
   ret i32 %1
 }
 
 ; Check that i256 is passed indirectly.
 
 define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
; RV64I-NEXT:    ret
   %1 = icmp eq i256 %h, %j
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV64I-LABEL: caller_large_scalars_exhausted_regs:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -96
-; RV64I-NEXT:    sd ra, 88(sp)
-; RV64I-NEXT:    addi a0, sp, 16
+; RV64I-NEXT:    addi sp, sp, -80
+; RV64I-NEXT:    sd ra, 72(sp)
+; RV64I-NEXT:    mv a0, sp
 ; RV64I-NEXT:    sd a0, 8(sp)
 ; RV64I-NEXT:    addi a0, zero, 9
 ; RV64I-NEXT:    sd a0, 0(sp)
 ; RV64I-NEXT:    addi a0, zero, 10
-; RV64I-NEXT:    sd a0, 16(sp)
-; RV64I-NEXT:    sd zero, 40(sp)
-; RV64I-NEXT:    sd zero, 32(sp)
+; RV64I-NEXT:    sd a0, 0(sp)
 ; RV64I-NEXT:    sd zero, 24(sp)
-; RV64I-NEXT:    sd zero, 72(sp)
-; RV64I-NEXT:    sd zero, 64(sp)
+; RV64I-NEXT:    sd zero, 16(sp)
+; RV64I-NEXT:    sd zero, 8(sp)
 ; RV64I-NEXT:    sd zero, 56(sp)
+; RV64I-NEXT:    sd zero, 48(sp)
+; RV64I-NEXT:    sd zero, 40(sp)
 ; RV64I-NEXT:    addi a0, zero, 8
-; RV64I-NEXT:    sd a0, 48(sp)
-; RV64I-NEXT:    addi a7, sp, 48
+; RV64I-NEXT:    sd a0, 32(sp)
+; RV64I-NEXT:    addi a7, sp, 32
 ; RV64I-NEXT:    addi a0, zero, 1
 ; RV64I-NEXT:    addi a1, zero, 2
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    addi a5, zero, 6
 ; RV64I-NEXT:    addi a6, zero, 7
 ; RV64I-NEXT:    call callee_large_scalars_exhausted_regs
-; RV64I-NEXT:    ld ra, 88(sp)
-; RV64I-NEXT:    addi sp, sp, 96
+; RV64I-NEXT:    ld ra, 72(sp)
+; RV64I-NEXT:    addi sp, sp, 80
 ; RV64I-NEXT:    ret
   %1 = call i64 @callee_large_scalars_exhausted_regs(
       i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9,
       i256 10)
   ret i64 %1
 }
 
 ; Ensure that libcalls generated in the middle-end obey the calling convention
; RV64I-NEXT:    ret
   ret i64 %7
 }
 
 define void @caller_aligned_stack() nounwind {
 ; The i128 should be 16-byte aligned on the stack, but the two-element array
 ; should only be 8-byte aligned
 ; RV64I-LABEL: caller_aligned_stack:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a0, zero, 12
 ; RV64I-NEXT:    sd a0, 48(sp)
 ; RV64I-NEXT:    addi a0, zero, 11
 ; RV64I-NEXT:    sd a0, 40(sp)
 ; RV64I-NEXT:    addi a0, zero, 10
 ; RV64I-NEXT:    sd a0, 32(sp)
 ; RV64I-NEXT:    addi a0, zero, 9
 ; RV64I-NEXT:    sd a0, 16(sp)
 ; RV64I-NEXT:    addi a0, zero, 8
 ; RV64I-NEXT:    sd a0, 0(sp)
 ; RV64I-NEXT:    sd zero, 24(sp)
 ; RV64I-NEXT:    addi a0, zero, 1
 ; RV64I-NEXT:    addi a1, zero, 2
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    addi a5, zero, 6
 ; RV64I-NEXT:    mv a6, zero
 ; RV64I-NEXT:    addi a7, zero, 7
 ; RV64I-NEXT:    call callee_aligned_stack
-; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i64 @callee_aligned_stack(i64 1, i64 2, i64 3, i64 4, i64 5,
     i128 6, i64 7, i64 8, i128 9, i64 10, [2 x i64] [i64 11, i64 12])
   ret void
 }
 
 ; Check return of 2x xlen scalars
 

llvm/test/CodeGen/RISCV/calling-conv-lp64.ll

 ; RV64I-FPELIM-NEXT:    mv a7, zero
 ; RV64I-FPELIM-NEXT:    call callee_float_on_stack
 ; RV64I-FPELIM-NEXT:    ld ra, 8(sp)
 ; RV64I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV64I-FPELIM-NEXT:    ret
 ;
 ; RV64I-WITHFP-LABEL: caller_float_on_stack:
 ; RV64I-WITHFP:       # %bb.0:
-; RV64I-WITHFP-NEXT:    addi sp, sp, -32
-; RV64I-WITHFP-NEXT:    sd ra, 24(sp)
-; RV64I-WITHFP-NEXT:    sd s0, 16(sp)
-; RV64I-WITHFP-NEXT:    addi s0, sp, 32
+; RV64I-WITHFP-NEXT:    addi sp, sp, -16
+; RV64I-WITHFP-NEXT:    sd ra, 8(sp)
+; RV64I-WITHFP-NEXT:    sd s0, 0(sp)
+; RV64I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV64I-WITHFP-NEXT:    lui a0, 264704
 ; RV64I-WITHFP-NEXT:    sd a0, 0(sp)
 ; RV64I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV64I-WITHFP-NEXT:    mv a1, zero
 ; RV64I-WITHFP-NEXT:    addi a2, zero, 2
 ; RV64I-WITHFP-NEXT:    mv a3, zero
 ; RV64I-WITHFP-NEXT:    addi a4, zero, 3
 ; RV64I-WITHFP-NEXT:    mv a5, zero
 ; RV64I-WITHFP-NEXT:    addi a6, zero, 4
 ; RV64I-WITHFP-NEXT:    mv a7, zero
 ; RV64I-WITHFP-NEXT:    call callee_float_on_stack
-; RV64I-WITHFP-NEXT:    ld s0, 16(sp)
-; RV64I-WITHFP-NEXT:    ld ra, 24(sp)
-; RV64I-WITHFP-NEXT:    addi sp, sp, 32
+; RV64I-WITHFP-NEXT:    ld s0, 0(sp)
+; RV64I-WITHFP-NEXT:    ld ra, 8(sp)
+; RV64I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV64I-WITHFP-NEXT:    ret
   %1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
   ret i64 %1
 }
 
 define float @callee_tiny_scalar_ret() nounwind {
 ; RV64I-FPELIM-LABEL: callee_tiny_scalar_ret:
 ; RV64I-FPELIM:       # %bb.0:

llvm/test/CodeGen/RISCV/double-calling-conv.ll

 ; RV32IFD-NEXT:    ret
   %1 = fadd double %e, %f
   ret double %1
 }
 
 define double @caller_double_stack() nounwind {
 ; RV32IFD-LABEL: caller_double_stack:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    addi sp, sp, -32
-; RV32IFD-NEXT:    sw ra, 28(sp)
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    sw ra, 12(sp)
 ; RV32IFD-NEXT:    lui a0, 262510
 ; RV32IFD-NEXT:    addi a0, a0, 327
 ; RV32IFD-NEXT:    sw a0, 4(sp)
 ; RV32IFD-NEXT:    lui a0, 262574
 ; RV32IFD-NEXT:    addi a0, a0, 327
 ; RV32IFD-NEXT:    sw a0, 12(sp)
 ; RV32IFD-NEXT:    lui a0, 713032
 ; RV32IFD-NEXT:    addi a0, a0, -1311
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    addi a0, zero, 1
 ; RV32IFD-NEXT:    mv a1, zero
 ; RV32IFD-NEXT:    addi a2, zero, 2
 ; RV32IFD-NEXT:    mv a3, zero
 ; RV32IFD-NEXT:    addi a4, zero, 3
 ; RV32IFD-NEXT:    mv a5, zero
 ; RV32IFD-NEXT:    addi a6, zero, 4
 ; RV32IFD-NEXT:    mv a7, zero
 ; RV32IFD-NEXT:    call callee_double_stack
-; RV32IFD-NEXT:    lw ra, 28(sp)
-; RV32IFD-NEXT:    addi sp, sp, 32
+; RV32IFD-NEXT:    lw ra, 12(sp)
+; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
   %1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
   ret double %1
 }

llvm/test/CodeGen/RISCV/stack-realignment.ll

; RV64I-NEXT:    ret
   %1 = alloca i8, align 256
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller512() nounwind {
 ; RV32I-LABEL: caller512:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -1536
-; RV32I-NEXT:    sw ra, 1532(sp)
-; RV32I-NEXT:    sw s0, 1528(sp)
-; RV32I-NEXT:    addi s0, sp, 1536
+; RV32I-NEXT:    addi sp, sp, -1024
+; RV32I-NEXT:    sw ra, 1020(sp)
+; RV32I-NEXT:    sw s0, 1016(sp)
+; RV32I-NEXT:    addi s0, sp, 1024
 ; RV32I-NEXT:    andi sp, sp, -512
-; RV32I-NEXT:    addi a0, sp, 1024
+; RV32I-NEXT:    addi a0, sp, 512
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    addi sp, s0, -1536
-; RV32I-NEXT:    lw s0, 1528(sp)
-; RV32I-NEXT:    lw ra, 1532(sp)
-; RV32I-NEXT:    addi sp, sp, 1536
+; RV32I-NEXT:    addi sp, s0, -1024
+; RV32I-NEXT:    lw s0, 1016(sp)
+; RV32I-NEXT:    lw ra, 1020(sp)
+; RV32I-NEXT:    addi sp, sp, 1024
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller512:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -1536
-; RV64I-NEXT:    sd ra, 1528(sp)
-; RV64I-NEXT:    sd s0, 1520(sp)
-; RV64I-NEXT:    addi s0, sp, 1536
+; RV64I-NEXT:    addi sp, sp, -1024
+; RV64I-NEXT:    sd ra, 1016(sp)
+; RV64I-NEXT:    sd s0, 1008(sp)
+; RV64I-NEXT:    addi s0, sp, 1024
 ; RV64I-NEXT:    andi sp, sp, -512
-; RV64I-NEXT:    addi a0, sp, 1024
+; RV64I-NEXT:    addi a0, sp, 512
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    addi sp, s0, -1536
-; RV64I-NEXT:    ld s0, 1520(sp)
-; RV64I-NEXT:    ld ra, 1528(sp)
-; RV64I-NEXT:    addi sp, sp, 1536
+; RV64I-NEXT:    addi sp, s0, -1024
+; RV64I-NEXT:    ld s0, 1008(sp)
+; RV64I-NEXT:    ld ra, 1016(sp)
+; RV64I-NEXT:    addi sp, sp, 1024
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 512
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign512() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign512:
; RV64I-NEXT:    ret
   %1 = alloca i8, align 512
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller1024() nounwind {
 ; RV32I-LABEL: caller1024:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -2048
+; RV32I-NEXT:    sw ra, 2044(sp)
+; RV32I-NEXT:    sw s0, 2040(sp)
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
-; RV32I-NEXT:    sub sp, sp, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1028
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    sw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1032
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    sw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
+; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -1024
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -2048
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    mv a0, a0
+; RV32I-NEXT:    addi a0, sp, 1024
 ; RV32I-NEXT:    call callee
+; RV32I-NEXT:    addi sp, s0, -2048
+; RV32I-NEXT:    lw s0, 2040(sp)
+; RV32I-NEXT:    lw ra, 2044(sp)
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
-; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1032
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1028
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
+; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller1024:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -2048
+; RV64I-NEXT:    sd ra, 2040(sp)
+; RV64I-NEXT:    sd s0, 2032(sp)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
-; RV64I-NEXT:    sub sp, sp, a0
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1032
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    sd ra, 0(a0)
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1040
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    sd s0, 0(a0)
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addi a0, a0, -2048
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -1024
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -2048
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    mv a0, a0
+; RV64I-NEXT:    addi a0, sp, 1024
 ; RV64I-NEXT:    call callee
+; RV64I-NEXT:    addi sp, s0, -2048
+; RV64I-NEXT:    ld s0, 2032(sp)
+; RV64I-NEXT:    ld ra, 2040(sp)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
-; RV64I-NEXT:    sub sp, s0, a0
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1040
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    ld s0, 0(a0)
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1032
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    ld ra, 0(a0)
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addi a0, a0, -2048
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign1024() nounwind "no-realign-stack" {
; RV64I-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller2048() nounwind {
 ; RV32I-LABEL: caller2048:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 2044
+; RV32I-NEXT:    addi a0, a0, -4
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw ra, 0(a0)
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 2040
+; RV32I-NEXT:    addi a0, a0, -8
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -2048
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    mv a0, a0
+; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 2040
+; RV32I-NEXT:    addi a0, a0, -8
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw s0, 0(a0)
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 2044
+; RV32I-NEXT:    addi a0, a0, -4
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2040
+; RV64I-NEXT:    addi a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2032
+; RV64I-NEXT:    addi a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
-; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -2048
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    mv a0, a0
+; RV64I-NEXT:    addi a0, a0, -2048
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2032
+; RV64I-NEXT:    addi a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2040
+; RV64I-NEXT:    addi a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
-; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign2048() nounwind "no-realign-stack" {
; RV64I-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller4096() nounwind {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, sp, a0
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -4
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -8
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
-; RV32I-NEXT:    lui a0, 2
+; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -8
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw s0, 0(a0)
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -4
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw ra, 0(a0)
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, sp, a0
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addi a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addi a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    srli a0, sp, 12
 ; RV64I-NEXT:    slli sp, a0, 12
-; RV64I-NEXT:    lui a0, 2
+; RV64I-NEXT:    lui a0, 1
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, s0, a0
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addi a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addi a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 4096
   call void @callee(i8* %1)
   ret void
 }
 

llvm/test/CodeGen/RISCV/vararg.ll

 
 declare i32 @va5_aligned_stack_callee(i32, ...)
 
 define void @va5_aligned_stack_caller() nounwind {
 ; The double should be 8-byte aligned on the stack, but the two-element array
 ; should only be 4-byte aligned
 ; ILP32-ILP32F-FPELIM-LABEL: va5_aligned_stack_caller:
 ; ILP32-ILP32F-FPELIM:       # %bb.0:
-; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, -64
-; ILP32-ILP32F-FPELIM-NEXT:    sw ra, 60(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, -32
+; ILP32-ILP32F-FPELIM-NEXT:    sw ra, 28(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, zero, 17
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 24(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, zero, 16
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 20(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, zero, 15
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 16(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 262236
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, 655
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 12(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 377487
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, 1475
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 8(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, zero, 14
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 0(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 262153
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, 491
-; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 44(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 12(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 545260
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, -1967
-; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 40(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 8(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 964690
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, -328
-; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 36(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 4(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 335544
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, 1311
-; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 32(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 0(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a0, 688509
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a6, a0, -2048
-; ILP32-ILP32F-FPELIM-NEXT:    addi a2, sp, 32
+; ILP32-ILP32F-FPELIM-NEXT:    mv a2, sp
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, zero, 1
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a1, zero, 11
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a3, zero, 12
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a4, zero, 13
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a7, zero, 4
 ; ILP32-ILP32F-FPELIM-NEXT:    call va5_aligned_stack_callee
-; ILP32-ILP32F-FPELIM-NEXT:    lw ra, 60(sp)
-; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, 64
+; ILP32-ILP32F-FPELIM-NEXT:    lw ra, 28(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, 32
 ; ILP32-ILP32F-FPELIM-NEXT:    ret
 ;
 ; ILP32-ILP32F-WITHFP-LABEL: va5_aligned_stack_caller:
 ; ILP32-ILP32F-WITHFP:       # %bb.0:
-; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, -64
-; ILP32-ILP32F-WITHFP-NEXT:    sw ra, 60(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    sw s0, 56(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    addi s0, sp, 64
+; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, -32
+; ILP32-ILP32F-WITHFP-NEXT:    sw ra, 28(sp)
+; ILP32-ILP32F-WITHFP-NEXT:    sw s0, 24(sp)
+; ILP32-ILP32F-WITHFP-NEXT:    addi s0, sp, 32
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, zero, 17
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a0, 24(sp)
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, zero, 16
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a0, 20(sp)
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, zero, 15
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a0, 16(sp)
 ; ILP32-ILP32F-WITHFP-NEXT:    lui a0, 262236
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, a0, 655

 ; ILP32-ILP32F-WITHFP-NEXT:    addi a6, a0, -2048
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a2, s0, -32
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, zero, 1
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a1, zero, 11
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a3, zero, 12
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a4, zero, 13
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a7, zero, 4
 ; ILP32-ILP32F-WITHFP-NEXT:    call va5_aligned_stack_callee
-; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 56(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 60(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 64
+; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 24(sp)
+; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 28(sp)
+; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 32
 ; ILP32-ILP32F-WITHFP-NEXT:    ret
 ;
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va5_aligned_stack_caller:
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM:       # %bb.0:
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, -64
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw ra, 60(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, -32
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw ra, 28(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 262236
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, 655
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 377487
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, 1475
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 8(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, zero, 17
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 24(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, zero, 16
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 20(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, zero, 15
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 16(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, zero, 14
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 262153
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, 491
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 44(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 545260
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, -1967
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 40(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 8(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 964690
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, -328
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 36(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 335544
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, 1311
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 32(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a0, 0(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a0, 688509
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a6, a0, -2048
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a2, sp, 32
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    mv a2, sp
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, zero, 11
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a4, zero, 13
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a7, zero, 4
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    call va5_aligned_stack_callee
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 60(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 64
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 28(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -48
-; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 40(sp)
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -16
+; LP64-LP64F-LP64D-FPELIM-NEXT:    sd ra, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, zero, 17
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 24(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, zero, 16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 16(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, zero, 15
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 2049
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, -1147

 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a2, a0, 1311
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a3, a1, -1967
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, zero, 1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a1, zero, 11
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a4, zero, 12
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a5, zero, 13
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a7, zero, 14
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    call va5_aligned_stack_callee
-; LP64-LP64F-LP64D-FPELIM-NEXT:    ld ra, 40(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, 48
+; LP64-LP64F-LP64D-FPELIM-NEXT:    ld ra, 8(sp)
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, 16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-WITHFP-LABEL: va5_aligned_stack_caller:
 ; LP64-LP64F-LP64D-WITHFP:       # %bb.0:
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, -48
-; LP64-LP64F-LP64D-WITHFP-NEXT:    sd ra, 40(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    sd s0, 32(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addi s0, sp, 48
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, -16
+; LP64-LP64F-LP64D-WITHFP-NEXT:    sd ra, 8(sp)
+; LP64-LP64F-LP64D-WITHFP-NEXT:    sd s0, 0(sp)
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addi s0, sp, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, zero, 17
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, 24(sp)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, zero, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, 16(sp)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, zero, 15
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, 8(sp)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a0, 2049
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, -1147

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a2, a0, 1311
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a3, a1, -1967
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, zero, 1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, zero, 11
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a4, zero, 12
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a5, zero, 13
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a7, zero, 14
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call va5_aligned_stack_callee
-; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 32(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 40(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 48
+; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 0(sp)
+; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 8(sp)
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
   %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
     i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
   ret void
 }
 
 ; A function with no fixed arguments is not valid C, but can be