[RISCV] Handle stack rounding only in RISCVFrameLowering.

[HsiangKai]

Summary

Implement targetHandlesStackFrameRounding() and return true. Handle stack rounding only in RISCVFrameLowering to avoid double-counting alignment; one in PEI::calculateFrameObjectOffsets() and another in determineFrameLayout() in RISCVFrameLowering.cpp.

[HsiangKai]

@lenary, is it reasonable to implement targetHandlesStackFrameRounding() and handle the alignment in RISCVFrameLowering.cpp?

[lenary]

@HsiangKai Can you coordinate with @rogfer01 about this patch vs https://reviews.llvm.org/D89237 ? Roger hit this when looking at the emergency spill slot work.

[craig.topper]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

246

"out going" -> outgoing

llvm/lib/Target/RISCV/RISCVFrameLowering.h

68

No need to write the function name in the doxygen comment.

[HsiangKai]

D89237 is a better way to go.

llvm/lib/Target/RISCV/RISCVFrameLowering.h

public:
   // Get the first stack adjustment amount for SplitSPAdjust.
   // Return 0 if we don't want to to split the SP adjustment in prologue and
   // epilogue.
   uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const;
 
   bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
   bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
 
+  /// targetHandlesStackFrameRounding - Returns true if the target is
+  /// responsible for rounding up the stack frame (probably at emitPrologue
+  /// time).
+  bool targetHandlesStackFrameRounding() const override { return true; }
+
 protected:
   const RISCVSubtarget &STI;
 
 private:
   void determineFrameLayout(MachineFunction &MF) const;
   void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                  const DebugLoc &DL, Register DestReg, Register SrcReg,
                  int64_t Val, MachineInstr::MIFlag Flag) const;
 };
 }
 #endif

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 // Determines the size of the frame and maximum call frame size.
 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
 
   // Get the number of bytes to allocate from the FrameInfo.
   uint64_t FrameSize = MFI.getStackSize();
 
+  // targetHandlesStackFrameRounding() will return true and handle the alignment
+  // here.
+  // MaxCallFrameSize is defined through ADJCALLSTACKDOWN.
+  // Reserve frame space for out going arguments of caller.
+  if (MFI.adjustsStack() && hasReservedCallFrame(MF))
+    FrameSize += MFI.getMaxCallFrameSize();
+
   // Get the alignment.
   Align StackAlign = getStackAlign();
   if (RI->needsStackRealignment(MF)) {
     Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
     FrameSize += (MaxStackAlign.value() - StackAlign.value());
     StackAlign = MaxStackAlign;
   }
 

llvm/test/CodeGen/RISCV/stack-realignment.ll

; RV64I-NEXT:    ret
   %1 = alloca i8, align 256
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller512() nounwind {
 ; RV32I-LABEL: caller512:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -1536
-; RV32I-NEXT:    sw ra, 1532(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s0, 1528(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    addi s0, sp, 1536
+; RV32I-NEXT:    addi sp, sp, -1024
+; RV32I-NEXT:    sw ra, 1020(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s0, 1016(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    addi s0, sp, 1024
 ; RV32I-NEXT:    andi sp, sp, -512
-; RV32I-NEXT:    addi a0, sp, 1024
+; RV32I-NEXT:    addi a0, sp, 512
 ; RV32I-NEXT:    call callee@plt
-; RV32I-NEXT:    addi sp, s0, -1536
-; RV32I-NEXT:    lw s0, 1528(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw ra, 1532(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    addi sp, sp, 1536
+; RV32I-NEXT:    addi sp, s0, -1024
+; RV32I-NEXT:    lw s0, 1016(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw ra, 1020(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 1024
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller512:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -1536
-; RV64I-NEXT:    sd ra, 1528(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s0, 1520(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    addi s0, sp, 1536
+; RV64I-NEXT:    addi sp, sp, -1024
+; RV64I-NEXT:    sd ra, 1016(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 1008(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    addi s0, sp, 1024
 ; RV64I-NEXT:    andi sp, sp, -512
-; RV64I-NEXT:    addi a0, sp, 1024
+; RV64I-NEXT:    addi a0, sp, 512
 ; RV64I-NEXT:    call callee@plt
-; RV64I-NEXT:    addi sp, s0, -1536
-; RV64I-NEXT:    ld s0, 1520(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld ra, 1528(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 1536
+; RV64I-NEXT:    addi sp, s0, -1024
+; RV64I-NEXT:    ld s0, 1008(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld ra, 1016(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 1024
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 512
   call void @callee(i8* %1)
   ret void
 }
 
 define void @caller_no_realign512() nounwind "no-realign-stack" {
 ; RV32I-LABEL: caller_no_realign512:

 
 define void @caller1024() nounwind {
 ; RV32I-LABEL: caller1024:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    addi s0, sp, 2032
-; RV32I-NEXT:    addi sp, sp, -1040
+; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    andi sp, sp, -1024
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -2048
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    mv a0, a0
+; RV32I-NEXT:    addi a0, sp, 1024
 ; RV32I-NEXT:    call callee@plt
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
-; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    addi sp, sp, 1040
+; RV32I-NEXT:    addi sp, s0, -2048
+; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller1024:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    addi s0, sp, 2032
-; RV64I-NEXT:    addi sp, sp, -1040
+; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    andi sp, sp, -1024
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, -2048
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    mv a0, a0
+; RV64I-NEXT:    addi a0, sp, 1024
 ; RV64I-NEXT:    call callee@plt
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, -1024
-; RV64I-NEXT:    sub sp, s0, a0
-; RV64I-NEXT:    addi sp, sp, 1040
+; RV64I-NEXT:    addi sp, s0, -2048
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 1024
   call void @callee(i8* %1)
   ret void
 }

 define void @caller2048() nounwind {
 ; RV32I-LABEL: caller2048:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    addi s0, sp, 2032
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -2048
 ; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    addi a0, a0, -2048
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee@plt
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    addi s0, sp, 2032
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -2048
 ; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee@plt
-; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addiw a0, a0, -2048
+; RV64I-NEXT:    lui a0, 1
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 2048
   call void @callee(i8* %1)
   ret void

 
 define void @caller4096() nounwind {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -2032
 ; RV32I-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    addi s0, sp, 2032
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
-; RV32I-NEXT:    lui a0, 2
+; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee@plt
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    lui a0, 3
+; RV32I-NEXT:    lui a0, 2
 ; RV32I-NEXT:    addi a0, a0, -2032
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 2032
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -2032
 ; RV64I-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    addi s0, sp, 2032
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    srli a0, sp, 12
 ; RV64I-NEXT:    slli sp, a0, 12
-; RV64I-NEXT:    lui a0, 2
+; RV64I-NEXT:    lui a0, 1
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee@plt
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    sub sp, s0, a0
-; RV64I-NEXT:    lui a0, 3
+; RV64I-NEXT:    lui a0, 2
 ; RV64I-NEXT:    addiw a0, a0, -2032
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 2032
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 4096
   call void @callee(i8* %1)