[RISCV] Implement Hooks to avoid chaining SELECT

[lenary]

Summary

This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V
will lower SELECTs into control flow, which is not a great idea.

The hook hasMultipleConditionRegisters() turns off the following
DAGCombiner folds:

select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y))
select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y)

The second hook setJumpIsExpensive controls a flag that has a similar purpose
and is used in CodeGenPrepare and the SelectionDAGBuilder.

Both of these have the effect of ensuring more logic is done before fewer jumps.

Note: with the B extension, we may be able to lower select into a conditional
move instruction, so at some point these hooks will need to be guarded based on
enabled extensions.

[lenary]

@luismarques pointed out there's an easier implementation of this: to use
setHasMultipleConditionRegisters, instead of overriding
shouldNormalizeToSelectSequence. This is correct as RISC-V branches can use
any register they want.

[luismarques]

It might be a good idea to add more targetted tests for this. See llvm/test/CodeGen/PowerPC/no-pref-jumps.ll and some of the tests added in 940ab934d42.

[lenary]

• Update tests due to changes in D79267

[lenary]

• Update tests for last time

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   // Function alignments.
   const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);
+
+  // Jumps are expensive, compared to logic
+  setJumpIsExpensive();
+
+  // We can use any register for comparisons
+  setHasMultipleConditionRegisters();
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                             EVT VT) const {
   if (!VT.isVector())
     return getPointerTy(DL);
   return VT.changeVectorElementTypeToInteger();
 }

llvm/test/CodeGen/RISCV/double-previous-failure.ll

 ; RV32IFD-NEXT:    lui a1, 262144
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    call test
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a1, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT:    flt.d a0, ft0, ft1
-; RV32IFD-NEXT:    bnez a0, .LBB1_3
-; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT:    flt.d a0, ft1, ft0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    beqz a0, .LBB1_3
-; RV32IFD-NEXT:  # %bb.2: # %if.end
+; RV32IFD-NEXT:    fld ft2, %lo(.LCPI1_1)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, ft1
+; RV32IFD-NEXT:    not a0, a0
+; RV32IFD-NEXT:    flt.d a1, ft2, ft0
+; RV32IFD-NEXT:    xori a1, a1, 1
+; RV32IFD-NEXT:    and a0, a0, a1
+; RV32IFD-NEXT:    bnez a0, .LBB1_2
+; RV32IFD-NEXT:  # %bb.1: # %if.then
+; RV32IFD-NEXT:    call abort
+; RV32IFD-NEXT:  .LBB1_2: # %if.end
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    call exit
-; RV32IFD-NEXT:  .LBB1_3: # %if.then
-; RV32IFD-NEXT:    call abort
 entry:
   %call = call double @test(double 2.000000e+00)
   %cmp = fcmp olt double %call, 2.400000e-01
   %cmp2 = fcmp ogt double %call, 2.600000e-01
   %or.cond = or i1 %cmp, %cmp2
   br i1 %or.cond, label %if.then, label %if.end
 
 if.then:

llvm/test/CodeGen/RISCV/select-and.ll

 declare signext i32 @both() nounwind
 declare signext i32 @neither() nounwind
 
 define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
 ; RV32I-LABEL: if_of_and:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    beqz a0, .LBB1_3
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.then
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    addi a1, zero, 1
+; RV32I-NEXT:    bne a0, a1, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    call both
-; RV32I-NEXT:    j .LBB1_4
-; RV32I-NEXT:  .LBB1_3: # %if.else
+; RV32I-NEXT:    j .LBB1_3
+; RV32I-NEXT:  .LBB1_2: # %if.else
 ; RV32I-NEXT:    call neither
-; RV32I-NEXT:  .LBB1_4: # %if.end
+; RV32I-NEXT:  .LBB1_3: # %if.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: if_of_and:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    beqz a0, .LBB1_3
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    beqz a1, .LBB1_3
-; RV64I-NEXT:  # %bb.2: # %if.then
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    bne a0, a1, .LBB1_2
+; RV64I-NEXT:  # %bb.1: # %if.then
 ; RV64I-NEXT:    call both
-; RV64I-NEXT:    j .LBB1_4
-; RV64I-NEXT:  .LBB1_3: # %if.else
+; RV64I-NEXT:    j .LBB1_3
+; RV64I-NEXT:  .LBB1_2: # %if.else
 ; RV64I-NEXT:    call neither
-; RV64I-NEXT:  .LBB1_4: # %if.end
+; RV64I-NEXT:  .LBB1_3: # %if.end
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = and i1 %a, %b
   br i1 %1, label %if.then, label %if.else
 
 if.then:
   %2 = tail call i32 @both()

llvm/test/CodeGen/RISCV/select-or.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ;; There are a few different ways to lower (select (or A, B), X, Y). This test
 ;; ensures that we do so with as few branches as possible.
 
 define signext i32 @select_of_or(i32 zeroext %a, i32 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
 ; RV32I-LABEL: select_of_or:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a4, a2
-; RV32I-NEXT:    bnez a1, .LBB0_3
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    or a1, a0, a1
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    bnez a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    bnez a0, .LBB0_4
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
-; RV32I-NEXT:    mv a4, a3
-; RV32I-NEXT:    beqz a0, .LBB0_2
-; RV32I-NEXT:  .LBB0_4:
-; RV32I-NEXT:    mv a2, a4
-; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: select_of_or:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a4, a2
-; RV64I-NEXT:    bnez a1, .LBB0_3
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    or a1, a0, a1
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    bnez a1, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    bnez a0, .LBB0_4
+; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB0_3:
-; RV64I-NEXT:    mv a4, a3
-; RV64I-NEXT:    beqz a0, .LBB0_2
-; RV64I-NEXT:  .LBB0_4:
-; RV64I-NEXT:    mv a2, a4
-; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
   %1 = icmp eq i32 %a, 0
   %2 = icmp eq i32 %b, 0
   %3 = or i1 %1, %2
   %4 = select i1 %3, i32 %c, i32 %d
   ret i32 %4
 }
 
 declare signext i32 @either() nounwind
 declare signext i32 @neither() nounwind
 
 define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
 ; RV32I-LABEL: if_of_or:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    bnez a0, .LBB1_3
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    bnez a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.else
-; RV32I-NEXT:    call neither
-; RV32I-NEXT:    j .LBB1_4
-; RV32I-NEXT:  .LBB1_3: # %if.then
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    addi a1, zero, 1
+; RV32I-NEXT:    bne a0, a1, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    call either
-; RV32I-NEXT:  .LBB1_4: # %if.end
+; RV32I-NEXT:    j .LBB1_3
+; RV32I-NEXT:  .LBB1_2: # %if.else
+; RV32I-NEXT:    call neither
+; RV32I-NEXT:  .LBB1_3: # %if.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: if_of_or:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    bnez a0, .LBB1_3
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    bnez a1, .LBB1_3
-; RV64I-NEXT:  # %bb.2: # %if.else
-; RV64I-NEXT:    call neither
-; RV64I-NEXT:    j .LBB1_4
-; RV64I-NEXT:  .LBB1_3: # %if.then
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    bne a0, a1, .LBB1_2
+; RV64I-NEXT:  # %bb.1: # %if.then
 ; RV64I-NEXT:    call either
-; RV64I-NEXT:  .LBB1_4: # %if.end
+; RV64I-NEXT:    j .LBB1_3
+; RV64I-NEXT:  .LBB1_2: # %if.else
+; RV64I-NEXT:    call neither
+; RV64I-NEXT:  .LBB1_3: # %if.end
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = or i1 %a, %b
   br i1 %1, label %if.then, label %if.else
 
 if.then:
   %2 = tail call i32 @either()

llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
 ; TODO: lbu and lhu should be selected to avoid the unnecessary masking.
 
 @bytes = global [5 x i8] zeroinitializer, align 1
 
 define i32 @test_zext_i8() nounwind {
 ; RV32I-LABEL: test_zext_i8:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(bytes)
 ; RV32I-NEXT:    lbu a1, %lo(bytes)(a0)
-; RV32I-NEXT:    addi a2, zero, 136
-; RV32I-NEXT:    bne a1, a2, .LBB0_3
-; RV32I-NEXT:  # %bb.1: # %entry
 ; RV32I-NEXT:    addi a0, a0, %lo(bytes)
 ; RV32I-NEXT:    lbu a0, 1(a0)
-; RV32I-NEXT:    addi a1, zero, 7
-; RV32I-NEXT:    bne a0, a1, .LBB0_3
-; RV32I-NEXT:  # %bb.2: # %if.end
+; RV32I-NEXT:    xori a1, a1, 136
+; RV32I-NEXT:    xori a0, a0, 7
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3: # %if.then
+; RV32I-NEXT:  .LBB0_2: # %if.then
 ; RV32I-NEXT:    addi a0, zero, 1
 ; RV32I-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 0), align 1
   %cmp = icmp eq i8 %0, -120
   %1 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 1), align 1
   %cmp3 = icmp eq i8 %1, 7
   %or.cond = and i1 %cmp, %cmp3
   br i1 %or.cond, label %if.end, label %if.then
 
 if.then:
   ret i32 1
 
 if.end:
   ret i32 0
 }
 
 @shorts = global [5 x i16] zeroinitializer, align 2
 
 define i32 @test_zext_i16() nounwind {
 ; RV32I-LABEL: test_zext_i16:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(shorts)
 ; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -120
-; RV32I-NEXT:    bne a1, a2, .LBB1_3
-; RV32I-NEXT:  # %bb.1: # %entry
 ; RV32I-NEXT:    addi a0, a0, %lo(shorts)
 ; RV32I-NEXT:    lhu a0, 2(a0)
-; RV32I-NEXT:    addi a1, zero, 7
-; RV32I-NEXT:    bne a0, a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.end
+; RV32I-NEXT:    lui a2, 16
+; RV32I-NEXT:    addi a2, a2, -120
+; RV32I-NEXT:    xor a1, a1, a2
+; RV32I-NEXT:    xori a0, a0, 7
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB1_3: # %if.then
+; RV32I-NEXT:  .LBB1_2: # %if.then
 ; RV32I-NEXT:    addi a0, zero, 1
 ; RV32I-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 0), align 2
   %cmp = icmp eq i16 %0, -120
   %1 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 1), align 2
   %cmp3 = icmp eq i16 %1, 7
   %or.cond = and i1 %cmp, %cmp3
   br i1 %or.cond, label %if.end, label %if.then
 
 if.then:
   ret i32 1
 
 if.end:
   ret i32 0
 }