[ELF] Delete the RelExpr member R_HINT. NFC

[MaskRay]

Summary

R_HINT is ignored like R_NONE. There are no strong reasons to keep
R_HINT. The largest RelExpr member R_RISCV_PC_INDIRECT is 60 now.

[grimar]

I think this is fine, but would like to hear what others think.

lld/ELF/Arch/RISCV.cpp

232

This place deserves a comment then.

lld/ELF/Relocations.cpp

1262

if (expr == R_NONE) ?

[MaskRay]

Simplify

lld/ELF/Arch/RISCV.cpp

232

@jrtc27 will add it on D71820. Ignoring R_RISCV_ALIGN deserves a warning/error.

(For more interesting problems, see D70157 how this can be risky in a few constructs (I'd say in 99% cases they are probably fine))

lld/ELF/Arch/ARM.cpp

case R_ARM_NONE:
     return R_NONE;
   case R_ARM_TLS_LE32:
     return R_TLS;
   case R_ARM_V4BX:
     // V4BX is just a marker to indicate there's a "bx rN" instruction at the
     // given address. It can be used to implement a special linker mode which
     // rewrites ARMv4T inputs to ARMv4. Since we support only ARMv4 input and
     // not ARMv4 output, we can just ignore it.
-    return R_HINT;
+    return R_NONE;
   default:
     return R_ABS;
   }
 }
 
 RelType ARM::getDynRel(RelType type) const {
   if ((type == R_ARM_ABS32) || (type == R_ARM_TARGET1 && !config->target1Rel))
     return R_ARM_ABS32;

lld/ELF/Arch/RISCV.cpp

case R_RISCV_TLS_GOT_HI20:
     return R_GOT_PC;
   case R_RISCV_TPREL_HI20:
   case R_RISCV_TPREL_LO12_I:
   case R_RISCV_TPREL_LO12_S:
     return R_TLS;
   case R_RISCV_RELAX:
   case R_RISCV_ALIGN:
   case R_RISCV_TPREL_ADD:
-    return R_HINT;
+    return R_NONE;
   default:
     return R_ABS;
   }
 }
 
 // Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
 static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
   return (v & ((1ULL << (begin + 1)) - 1)) >> end;

lld/ELF/Relocations.h

enum RelExpr {
   R_GOT,
   R_GOT_OFF,
   R_GOT_PC,
   R_GOTONLY_PC,
   R_GOTPLTONLY_PC,
   R_GOTPLT,
   R_GOTPLTREL,
   R_GOTREL,
-  R_HINT,
   R_NEG_TLS,
   R_NONE,
   R_PC,
   R_PLT,
   R_PLT_PC,
   R_RELAX_GOT_PC,
   R_RELAX_GOT_PC_NOPIC,
   R_RELAX_TLS_GD_TO_IE,

lld/ELF/Relocations.cpp

static void scanReloc(InputSectionBase &sec, OffsetGetter &getOffset, RelTy *&i,
   // Error if the target symbol is undefined. Symbol index 0 may be used by
   // marker relocations, e.g. R_*_NONE and R_ARM_V4BX. Don't error on them.
   if (symIndex != 0 && maybeReportUndefined(sym, sec, rel.r_offset))
     return;
 
   const uint8_t *relocatedAddr = sec.data().begin() + rel.r_offset;
   RelExpr expr = target->getRelExpr(type, sym, relocatedAddr);
 
-  // Ignore "hint" relocations because they are only markers for relaxation.
-  if (oneof<R_HINT, R_NONE>(expr))
+  // Ignore R_*_NONE and other marker relocations.
+  if (expr == R_NONE)
     return;
 
   // We can separate the small code model relocations into 2 categories:
   // 1) Those that access the compiler generated .toc sections.
   // 2) Those that access the linker allocated got entries.
   // lld allocates got entries to symbols on demand. Since we don't try to sort
   // the got entries in any way, we don't have to track which objects have
   // got-based small code model relocs. The .toc sections get placed after the