[RISCV] Sign-extend 32-bit integer inline assembly operands on RV64I

[jrtc27]

Summary

GCC forces its in-register representation of 32-bit integers to be
sign-extended (ignoring whether it was a signed type in the source),
which gets exposed to inline assembly, commonly due to comparisons
against other sign-extended registers written to in the assembly, such
as in FreeBSD's atomic.h.

Since i32 is not legal for RV64I, we end up with a zero extension
(presumably because isZExtFree returns true and is preferred) for i32
loads consumed by inline assembly, deviating from GCC's exposed
behaviour. 64-bit MIPS (for which GCC also has the same in-register
representation of 32-bit integers) does not suffer from this bug because
it has a GPR32 register class and can use a normal non-extending load
(which is by default the sign-extending variant).

[jrtc27]

So, I'm not sure whether this is actually something we want to make work or not. You can already end up with both inconsistencies between compilers and inconsistencies within a compiler for how 16-bit values get represented when passed as register operands, and the fact that we're going against the grain and making i32 an illegal type just makes that also apply to i32; it's nothing new, just more widespread. I wrote a bunch of stuff exploring how this is all already broken for i16 over on the corresponding FreeBSD revision that found this issue (https://reviews.freebsd.org/D22084#482766), but trying to support this sounds like opening a can of worms, and it seems likely that we will still end up with subtle differences, ones which might rear their heads only once there is sufficient inlining (and perhaps due to LTO), removing the sanitisation applied by the calling convention. Moreover, only guaranteeing GCC compatibility (and self-consistency) for i32 and iPTR (whatever that may be) across architectures seems a bit arbitrary. Yes, i32 is a bit special due to C's integer promotion rules, but it feels like a slippery slope towards standardising on i16 and i8 too. Yes, I went and wrote this patch, but having further explored the issue and thought about it, my inclination is that we should just tell people to not do this, and put in the explicit sign-extending or zero-extending casts they want in order to get an XLEN-sized value. Especially since there is not likely to be much RISC-V inline assembly out there at the moment that relies on this. What do others think? Perhaps Clang could gain more than the current warn_asm_mismatched_size_modifier (which is currently about whether the register you're getting due to your modifiers matches what your input is, e.g. if the input gets promoted to an i32 on AArch64 you should be using a W register with %w0 rather than %0; it's not warning about the promotion itself).

[bsdjhb]

My only thought is that the RISC-V spec seems to require sign-extending unsigned 32-bit ints when stored in 64-bit registers, so folks may very well assume this behavior in the future when writing inline assembly. The spec doesn't say anything about types other than 32-bits that I found, and the section from the 2.2 user spec (quoted below) is in italics (meaning it's commentary to explain that spec that technically isn't part of the spec itself IIRC which perhaps puts it in a grey area). For FreeBSD it seems a simple cast in the constraint is sufficient to resolve our immediate issue FWIW.

From section 4.2:

The compiler and calling convention maintain an invariant that all 32-bit values are held in a sign-extended format in 64-bit registers. Even 32-bit unsigned integers extend bit 31 into bits 63 through 32. Consequently, conversion between unsigned and signed 32-bit integers is a no-op, as is conversion from a signed 32-bit integer to a signed 64-bit integer. Existing 64-bit wide SLTU and unsigned branch compares still operate correctly on unsigned 32-bit integers under this invariant. Similarly, existing 64-bit wide logical operations on 32-bit sign-extended integers preserve the sign-extension property. A few new instructions (ADD[I]W/SUBW/SxxW) are required for addition and shifts to ensure reasonable performance for 32-bit values.

[lenary]

I think there are a few issues here (having read the freebsd ticket):

1. How do we choose to do something reasonable?
2. How do we tell users there are sharp corners here?

To provide opinionated answers, having had a chat with @luismarques before we saw the comment from @bsdjhb:

1. We need a sensible default here. Because GCC doesn't define any behaviour around inline assembly (and doesn't expect to maintain compatibility between versions), we can choose to do something principled and stick to that. Given the specification wording, I think sign-extending makes sense (given the specification), but if we want to do something different for signed vs unsigned types, this will be much more complex (LLVM IR doesn't have signed/unsigned types). I do think looking at the RISC-V specification and forming a reasonable behaviour based off that (without looking at other implementations) is the correct approach in this case.

2. I absolutely believe we need a warning if the operand type does not match the register size. This is important for users who want to avoid this sharp edge (users who don't care can turn off warnings). It doesn't need to be enabled by default, but warnings are a great way of encouraging developers to improve their code, and also help to point to potential code issues when switching compilers/versions which may have incompatibilities (as inline assembly does have, see comment about GCC in 1.). I would go so far as to say this warning should be cross-target, so other targets can benefit too. I do realise this could be hard to implement.

[jrtc27]

I was not aware of that aside in the spec, which does indeed suggest this specific case should sign-extend, and I guess gives us a reason why this isn't a slippery slope. However, even if this is the case, I still feel code shouldn't be relying on this, simply because it's unclear (and perhaps surprising to those who don't know this particular note from the spec). One might perfectly reasonably assume that both signed and unsigned i32 types (in the original source) are zero-extended, or (probably the default position of people) that the signed type is sign-extended and the unsigned type is zero-extended (which would require passing the extension information through via the asm call instruction's operands).

[bsdjhb]

In D69212#1716991, @jrtc27 wrote:

I was not aware of that aside in the spec, which does indeed suggest this specific case should sign-extend, and I guess gives us a reason why this isn't a slippery slope. However, even if this is the case, I still feel code shouldn't be relying on this, simply because it's unclear (and perhaps surprising to those who don't know this particular note from the spec). One might perfectly reasonably assume that both signed and unsigned i32 types (in the original source) are zero-extended, or (probably the default position of people) that the signed type is sign-extended and the unsigned type is zero-extended (which would require passing the extension information through via the asm call instruction's operands).

FWIW, even though I had ready this part of the spec previously, I didn't really notice it until I went back and re-read it while investigating this specific issue (I was actually hunting for an unsigned variant of lw.r when I found this section instead). I think having a warning makes sense as this behavior is certainly not common across platforms. I also find it odd that this comment is commentary in the spec rather than formal language in the spec as it seems to assert that this behavior is required of the compiler rather than optional. For FreeBSD's atomic.h I'm going to add explicit casts to force sign-extension which I think would also satisfy the proposed warning.

llvm/include/llvm/CodeGen/TargetLowering.h

virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                             SelectionDAG &DAG) const;
 
   // Lower custom output constraints. If invalid, return SDValue().
   virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
                                               SDLoc DL,
                                               const AsmOperandInfo &OpInfo,
                                               SelectionDAG &DAG) const;
 
+  /// Returns how the platform's inline assembly operands of the given type
+  /// should be extended for the given register type (ZERO_EXTEND, SIGN_EXTEND
+  /// or ANY_EXTEND).
+  virtual ISD::NodeType getExtendForInlineAsmOperand(EVT VT) const {
+    return ISD::ANY_EXTEND;
+  }
+
   //===--------------------------------------------------------------------===//
   // Div utility functions
   //
   SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
                     SmallVectorImpl<SDNode *> &Created) const;
   SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
                     SmallVectorImpl<SDNode *> &Created) const;
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case InlineAsm::isInput: {
             for (unsigned i = 0; i != NumRegs; ++i)
               Regs.push_back(RegInfo.createVirtualRegister(RC));
           } else {
             emitInlineAsmError(CS, "inline asm error: This value type register "
                                    "class is not natively supported!");
             return;
           }
 
-          RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
+          EVT ValVT = InOperandVal.getValueType();
+          RegsForValue MatchedRegs(Regs, RegVT, ValVT);
 
           SDLoc dl = getCurSDLoc();
           // Use the produced MatchedRegs object to
           MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag,
-                                    CS.getInstruction());
+                                    CS.getInstruction(),
+                                    TLI.getExtendForInlineAsmOperand(ValVT));
           MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
                                            true, OpInfo.getMatchedOperand(), dl,
                                            DAG, AsmNodeOperands);
           break;
         }
 
         assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
         assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
case InlineAsm::isInput: {
       if (OpInfo.AssignedRegs.Regs.empty()) {
         emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
                                    Twine(OpInfo.ConstraintCode) + "'");
         return;
       }
 
       SDLoc dl = getCurSDLoc();
 
+      EVT ValVT = InOperandVal.getValueType();
+      ISD::NodeType ExtendType = TLI.getExtendForInlineAsmOperand(ValVT);
       OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
-                                        Chain, &Flag, CS.getInstruction());
+                                        Chain, &Flag, CS.getInstruction(),
+                                        ExtendType);
 
       OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
                                                dl, DAG, AsmNodeOperands);
       break;
     }
     case InlineAsm::isClobber:
       // Add the clobbered value to the operand list, so that the register
       // allocator is aware that the physreg got clobbered.

llvm/lib/Target/RISCV/RISCVISelLowering.h

public:
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;
 
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
+  ISD::NodeType getExtendForInlineAsmOperand(EVT VT) const override;
+
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
 
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
 
   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case 'K':
       return;
     default:
       break;
     }
   }
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
+ISD::NodeType
+RISCVTargetLowering::getExtendForInlineAsmOperand(EVT VT) const {
+  // GCC forces 32-bit integers on RV64I to be sign-extended in registers,
+  // whether unsigned or signed, and this is visible to inline assembly, so we
+  // make it look like we do the same.
+  if (Subtarget.is64Bit() && VT == MVT::i32)
+    return ISD::SIGN_EXTEND;
+  return TargetLowering::getExtendForInlineAsmOperand(VT);
+}
+
 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
                                                    Instruction *Inst,
                                                    AtomicOrdering Ord) const {
   if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
     return Builder.CreateFence(Ord);
   if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
     return Builder.CreateFence(AtomicOrdering::Release);
   return nullptr;

llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll

 ; RV64I-NEXT:    addi a0, zero, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved.
-define i32 @explicit_register_x1(i32 %a) nounwind {
+define i32 @explicit_register_x1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv ra, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, ra, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved.
-define i32 @explicit_register_ra(i32 %a) nounwind {
+define i32 @explicit_register_ra(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_ra:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv ra, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, ra, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x2(i32 %a) nounwind {
+define i32 @explicit_register_x2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv sp, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, sp, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv sp, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, sp, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_sp(i32 %a) nounwind {
+define i32 @explicit_register_sp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_sp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv sp, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, sp, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_sp:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv sp, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, sp, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved.
-define i32 @explicit_register_x3(i32 %a) nounwind {
+define i32 @explicit_register_x3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw gp, 12(sp)
 ; RV32I-NEXT:    mv gp, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, gp, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld gp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved.
-define i32 @explicit_register_gp(i32 %a) nounwind {
+define i32 @explicit_register_gp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_gp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw gp, 12(sp)
 ; RV32I-NEXT:    mv gp, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, gp, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld gp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved.
-define i32 @explicit_register_x4(i32 %a) nounwind {
+define i32 @explicit_register_x4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw tp, 12(sp)
 ; RV32I-NEXT:    mv tp, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, tp, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld tp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved.
-define i32 @explicit_register_tp(i32 %a) nounwind {
+define i32 @explicit_register_tp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_tp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw tp, 12(sp)
 ; RV32I-NEXT:    mv tp, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, tp, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ld tp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x5(i32 %a) nounwind {
+define i32 @explicit_register_x5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t0, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t0, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x5:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t0, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t0(i32 %a) nounwind {
+define i32 @explicit_register_t0(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t0, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t0, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_t0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t0, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x6(i32 %a) nounwind {
+define i32 @explicit_register_x6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t1, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t1, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x6:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t1, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t1(i32 %a) nounwind {
+define i32 @explicit_register_t1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t1, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t1, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_t1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t1, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x7(i32 %a) nounwind {
+define i32 @explicit_register_x7(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t2, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t2, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x7:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t2, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t2(i32 %a) nounwind {
+define i32 @explicit_register_t2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t2, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t2, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_t2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t2, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved.
-define i32 @explicit_register_x8(i32 %a) nounwind {
+define i32 @explicit_register_x8(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s0, 12(sp)
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s0, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s0, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved.
-define i32 @explicit_register_s0(i32 %a) nounwind {
+define i32 @explicit_register_s0(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s0, 12(sp)
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s0, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s0, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved.
-define i32 @explicit_register_fp(i32 %a) nounwind {
+define i32 @explicit_register_fp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_fp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s0, 12(sp)
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s0, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s0, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved.
-define i32 @explicit_register_x9(i32 %a) nounwind {
+define i32 @explicit_register_x9(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x9:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s1, 12(sp)
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s1, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved.
-define i32 @explicit_register_s1(i32 %a) nounwind {
+define i32 @explicit_register_s1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s1, 12(sp)
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s1, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x10(i32 %a) nounwind {
+define i32 @explicit_register_x10(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a0, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x10:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a0(i32 %a) nounwind {
+define i32 @explicit_register_a0(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a0, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x11(i32 %a) nounwind {
+define i32 @explicit_register_x11(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a1, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x11:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a1(i32 %a) nounwind {
+define i32 @explicit_register_a1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a1, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x12(i32 %a) nounwind {
+define i32 @explicit_register_x12(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x12:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a2, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x12:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a2(i32 %a) nounwind {
+define i32 @explicit_register_a2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a2, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x13(i32 %a) nounwind {
+define i32 @explicit_register_x13(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x13:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a3, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x13:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a3, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a3(i32 %a) nounwind {
+define i32 @explicit_register_a3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a3, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a3, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x14(i32 %a) nounwind {
+define i32 @explicit_register_x14(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x14:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a4, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x14:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a4, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a4(i32 %a) nounwind {
+define i32 @explicit_register_a4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a4, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a4:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a4, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x15(i32 %a) nounwind {
+define i32 @explicit_register_x15(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x15:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a5, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a5, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x15:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a5, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a5(i32 %a) nounwind {
+define i32 @explicit_register_a5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a5, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a5, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a5:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a5, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x16(i32 %a) nounwind {
+define i32 @explicit_register_x16(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a6, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a6, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a6, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a6(i32 %a) nounwind {
+define i32 @explicit_register_a6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a6, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a6, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a6:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a6, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x17(i32 %a) nounwind {
+define i32 @explicit_register_x17(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x17:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a7, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a7, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x17:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a7, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a7, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_a7(i32 %a) nounwind {
+define i32 @explicit_register_a7(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a7, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a7, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_a7:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a7, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a7, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved.
-define i32 @explicit_register_x18(i32 %a) nounwind {
+define i32 @explicit_register_x18(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x18:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s2, 12(sp)
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s2, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s2, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved.
-define i32 @explicit_register_s2(i32 %a) nounwind {
+define i32 @explicit_register_s2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s2, 12(sp)
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s2, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s2, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved.
-define i32 @explicit_register_x19(i32 %a) nounwind {
+define i32 @explicit_register_x19(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x19:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s3, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s3, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved.
-define i32 @explicit_register_s3(i32 %a) nounwind {
+define i32 @explicit_register_s3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s3, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s3, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved.
-define i32 @explicit_register_x20(i32 %a) nounwind {
+define i32 @explicit_register_x20(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x20:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s4, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved.
-define i32 @explicit_register_s4(i32 %a) nounwind {
+define i32 @explicit_register_s4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s4, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved.
-define i32 @explicit_register_x21(i32 %a) nounwind {
+define i32 @explicit_register_x21(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x21:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s5, 12(sp)
 ; RV32I-NEXT:    mv s5, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s5, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s5, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved.
-define i32 @explicit_register_s5(i32 %a) nounwind {
+define i32 @explicit_register_s5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s5, 12(sp)
 ; RV32I-NEXT:    mv s5, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s5, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s5, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved.
-define i32 @explicit_register_x22(i32 %a) nounwind {
+define i32 @explicit_register_x22(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x22:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s6, 12(sp)
 ; RV32I-NEXT:    mv s6, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s6, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved.
-define i32 @explicit_register_s6(i32 %a) nounwind {
+define i32 @explicit_register_s6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s6, 12(sp)
 ; RV32I-NEXT:    mv s6, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s6, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved.
-define i32 @explicit_register_x23(i32 %a) nounwind {
+define i32 @explicit_register_x23(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x23:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s7, 12(sp)
 ; RV32I-NEXT:    mv s7, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s7, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s7, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved.
-define i32 @explicit_register_s7(i32 %a) nounwind {
+define i32 @explicit_register_s7(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s7, 12(sp)
 ; RV32I-NEXT:    mv s7, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s7, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s7, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved.
-define i32 @explicit_register_x24(i32 %a) nounwind {
+define i32 @explicit_register_x24(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x24:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s8, 12(sp)
 ; RV32I-NEXT:    mv s8, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s8, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s8, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved.
-define i32 @explicit_register_s8(i32 %a) nounwind {
+define i32 @explicit_register_s8(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s8, 12(sp)
 ; RV32I-NEXT:    mv s8, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s8, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s8, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved.
-define i32 @explicit_register_x25(i32 %a) nounwind {
+define i32 @explicit_register_x25(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x25:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s9, 12(sp)
 ; RV32I-NEXT:    mv s9, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s9, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s9, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved.
-define i32 @explicit_register_s9(i32 %a) nounwind {
+define i32 @explicit_register_s9(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s9:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s9, 12(sp)
 ; RV32I-NEXT:    mv s9, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s9, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s9, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved.
-define i32 @explicit_register_x26(i32 %a) nounwind {
+define i32 @explicit_register_x26(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x26:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s10, 12(sp)
 ; RV32I-NEXT:    mv s10, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s10, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s10, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved.
-define i32 @explicit_register_s10(i32 %a) nounwind {
+define i32 @explicit_register_s10(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s10, 12(sp)
 ; RV32I-NEXT:    mv s10, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s10, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s10, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved.
-define i32 @explicit_register_x27(i32 %a) nounwind {
+define i32 @explicit_register_x27(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x27:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s11, 12(sp)
 ; RV32I-NEXT:    mv s11, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s11, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    ld s11, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a)
   ret i32 %1
 }
 
 ; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved.
-define i32 @explicit_register_s11(i32 %a) nounwind {
+define i32 @explicit_register_s11(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw s11, 12(sp)
 ; RV32I-NEXT:    mv s11, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, s11, 0
 ; RV32I-NEXT:    #NO_APP

 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ld s11, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x28(i32 %a) nounwind {
+define i32 @explicit_register_x28(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x28:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t3, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t3, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x28:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t3, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t3(i32 %a) nounwind {
+define i32 @explicit_register_t3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t3, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t3, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_t3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t3, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x29(i32 %a) nounwind {
+define i32 @explicit_register_x29(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x29:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t4, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t4, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x29:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t4, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t4(i32 %a) nounwind {
+define i32 @explicit_register_t4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t4, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t4, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_t4:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t4, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x30(i32 %a) nounwind {
+define i32 @explicit_register_x30(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t5, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t5, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t5, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t5(i32 %a) nounwind {
+define i32 @explicit_register_t5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t5, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t5, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_t5:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t5, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_x31(i32 %a) nounwind {
+define i32 @explicit_register_x31(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t6, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t6, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: explicit_register_x31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv t6, a0
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, t6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a)
   ret i32 %1
 }
 
-define i32 @explicit_register_t6(i32 %a) nounwind {
+define i32 @explicit_register_t6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t6, a0
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, t6, 0
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/inline-asm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 @gi = external global i32
 
-define i32 @constraint_r(i32 %a) nounwind {
+define i32 @constraint_r(i32 signext %a) nounwind {
 ; RV32I-LABEL: constraint_r:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, %hi(gi)
 ; RV32I-NEXT:    lw a1, %lo(gi)(a1)
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: constraint_r:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, %hi(gi)
-; RV64I-NEXT:    lwu a1, %lo(gi)(a1)
+; RV64I-NEXT:    lw a1, %lo(gi)(a1)
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = load i32, i32* @gi
   %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
   ret i32 %2
 }
 
-define i32 @constraint_i(i32 %a) nounwind {
+define i32 @constraint_i(i32 signext %a) nounwind {
 ; RV32I-LABEL: constraint_i:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a0, 113
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: constraint_i:

 ; RV64I-NEXT:    lb s1, 0(a0)
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   tail call void asm sideeffect "sb s0, $0", "*A"(i8* %a)
   tail call void asm sideeffect "lb s1, $0", "*A"(i8* %a)
   ret void
 }
 
-define i32 @modifier_z_zero(i32 %a) nounwind {
+define i32 @modifier_z_zero(i32 signext %a) nounwind {
 ; RV32I-LABEL: modifier_z_zero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    add a0, a0, zero
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: modifier_z_zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    add a0, a0, zero
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 0)
   ret i32 %1
 }
 
-define i32 @modifier_z_nonzero(i32 %a) nounwind {
+define i32 @modifier_z_nonzero(i32 signext %a) nounwind {
 ; RV32I-LABEL: modifier_z_nonzero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 1
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: modifier_z_nonzero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 1)
   ret i32 %1
 }
 
-define i32 @modifier_i_imm(i32 %a) nounwind {
+define i32 @modifier_i_imm(i32 signext %a) nounwind {
 ; RV32I-LABEL: modifier_i_imm:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: modifier_i_imm:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    addi a0, a0, 1
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
   ret i32 %1
 }
 
-define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
+define i32 @modifier_i_reg(i32 signext %a, i32 signext %b) nounwind {
 ; RV32I-LABEL: modifier_i_reg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: modifier_i_reg: