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[Xtensa 4/10] Add basic *td files with Xtensa architecture description.
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Authored by andreisfr on Jul 16 2019, 3:21 PM.

Details

Summary

Add initial Xtensa.td file with target machine description. Add XtensaInstrInfo.td,
currently describe just susbet of Core Instructions like ALU, Processor control,
memory barrier and some move instructions. Add descriptions of the instructions
formats(XtensaInstrInfo.td) and some immediate instruction operands(XtensaOperands.td).
Add General Registers and Special Registers classes.

Diff Detail

Event Timeline

andreisfr created this revision.Jul 16 2019, 3:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2019, 3:21 PM
arsenm added a subscriber: arsenm.Jul 16 2019, 3:24 PM
arsenm added inline comments.
llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
41–46

Usually the register names and corresponding generated enums are capitalized

appcs added a reviewer: appcs.Jul 16 2019, 4:03 PM

Where is the Xtensa instruction set architecture (ISA) document on which this patch is based on?

andreisfr updated this revision to Diff 212684.Jul 31 2019, 3:51 PM

Register names are capitalized.

As for Xtensa instruction set architecture (ISA) document , currently public ISA description mainly available in opensource projects like gcc/qemu/binutils:
https://github.com/gcc-mirror/gcc/tree/master/gcc/config/xtensa
https://github.com/qemu/qemu/blob/master/target/xtensa/translate.c
https://github.com/bminor/binutils-gdb/blob/master/bfd/xtensa-modules.c

I don’t think I saw an RFC for this target? Was there one I missed?

As for Xtensa instruction set architecture (ISA) document , currently public ISA description mainly available in opensource projects like gcc/qemu/binutils:
https://github.com/gcc-mirror/gcc/tree/master/gcc/config/xtensa
https://github.com/qemu/qemu/blob/master/target/xtensa/translate.c
https://github.com/bminor/binutils-gdb/blob/master/bfd/xtensa-modules.c

So the only documentation is the existing implementations?
To me personally that does not sound like there is documentation..

Doing a websearch for "xtensa isa", I do see that documentation does seem to exist: https://github.com/eerimoq/hardware-reference/blob/master/esp32/xtensa%20Instruction%20Set%20Architecture%20(ISA)%20Reference%20Manual.pdf.

It would sure be nice if it was hosted in a more official location, though.

I do not think there is a reason why the Xtensa architecture shouldn't be included in LLVM. As a comparison, there is also the proprietary (Google) Lanai architecture which was added at a time when there was little public information on it and to this time nobody can actually buy Lanai hardware (there is only a simulator). As a comparison, Xtensa has easy to get hardware (in the form of the ESP8266/ESP32) and is already supported in GCC/binutils.

Looking back at the email thread, there were very few responses. I wonder what should be done next?
Tagging Chris just in case: @lattner