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[Xtensa 4/10] Add basic *td files with Xtensa architecture description.
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Authored by andreisfr on Jul 16 2019, 3:21 PM.

Details

Summary

Add initial Xtensa.td file with target machine description. Add XtensaInstrInfo.td,
currently describe just susbet of Core Instructions like ALU, Processor control,
memory barrier and some move instructions. Add descriptions of the instructions
formats(XtensaInstrInfo.td) and some immediate instruction operands(XtensaOperands.td).
Add General Registers and Special Registers classes.

Diff Detail

Event Timeline

andreisfr created this revision.Jul 16 2019, 3:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2019, 3:21 PM
arsenm added a subscriber: arsenm.Jul 16 2019, 3:24 PM
arsenm added inline comments.
llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
41–46

Usually the register names and corresponding generated enums are capitalized

appcs added a reviewer: appcs.Jul 16 2019, 4:03 PM

Where is the Xtensa instruction set architecture (ISA) document on which this patch is based on?

andreisfr updated this revision to Diff 212684.Jul 31 2019, 3:51 PM

Register names are capitalized.

As for Xtensa instruction set architecture (ISA) document , currently public ISA description mainly available in opensource projects like gcc/qemu/binutils:
https://github.com/gcc-mirror/gcc/tree/master/gcc/config/xtensa
https://github.com/qemu/qemu/blob/master/target/xtensa/translate.c
https://github.com/bminor/binutils-gdb/blob/master/bfd/xtensa-modules.c

I don’t think I saw an RFC for this target? Was there one I missed?

As for Xtensa instruction set architecture (ISA) document , currently public ISA description mainly available in opensource projects like gcc/qemu/binutils:
https://github.com/gcc-mirror/gcc/tree/master/gcc/config/xtensa
https://github.com/qemu/qemu/blob/master/target/xtensa/translate.c
https://github.com/bminor/binutils-gdb/blob/master/bfd/xtensa-modules.c

So the only documentation is the existing implementations?
To me personally that does not sound like there is documentation..

Doing a websearch for "xtensa isa", I do see that documentation does seem to exist: https://github.com/eerimoq/hardware-reference/blob/master/esp32/xtensa%20Instruction%20Set%20Architecture%20(ISA)%20Reference%20Manual.pdf.

It would sure be nice if it was hosted in a more official location, though.

I do not think there is a reason why the Xtensa architecture shouldn't be included in LLVM. As a comparison, there is also the proprietary (Google) Lanai architecture which was added at a time when there was little public information on it and to this time nobody can actually buy Lanai hardware (there is only a simulator). As a comparison, Xtensa has easy to get hardware (in the form of the ESP8266/ESP32) and is already supported in GCC/binutils.

Looking back at the email thread, there were very few responses. I wonder what should be done next?
Tagging Chris just in case: @lattner

I do not think there is a reason why the Xtensa architecture shouldn't be included in LLVM. As a comparison, there is also the proprietary (Google) Lanai architecture which was added at a time when there was little public information on it and to this time nobody can actually buy Lanai hardware (there is only a simulator). As a comparison, Xtensa has easy to get hardware (in the form of the ESP8266/ESP32) and is already supported in GCC/binutils.

I'd note that Lanai did publish a set of ISA docs as part of upstreaming the llvm backend.

Having something like that perhaps doesn't need to be a hard-blocker, but I'd love to see a real response from the xtensa folks, since AFAICT it looks as if like there *IS* ISA documentation, just perhaps not -- officially -- publicly available. It would make things much easier to understand if xtensa published what they had. Without that, nobody else can really review or understand the backend.

I'd note that Lanai did publish a set of ISA docs as part of upstreaming the llvm backend.

Having something like that perhaps doesn't need to be a hard-blocker, but I'd love to see a real response from the xtensa folks, since AFAICT it looks as if like there *IS* ISA documentation, just perhaps not -- officially -- publicly available. It would make things much easier to understand if xtensa published what they had. Without that, nobody else can really review or understand the backend.

@jyknight , as I'm understood, Cadence doesn;t want to publish Xtensa ISA. But it seems that documentation from the link that you provided is quite actual, probably it was published when Xtensa was owned by Tensilica. Also, the code can be reviewed by people from companies that use Xtensa IP in their chips.

BTW there is also an ARC backend (from Synopsys), and I have not found any public documentation with ARC ISA, so probably encoding of ARC instructions also could be verified only by Synopsys engineers.

Also we could prepare summary about Xtensa ISA based on public resources like GCC, Binutils, QEMU with quality enough for code review. What do you think?

@jyknight , as I'm understood, Cadence doesn;t want to publish Xtensa ISA. But it seems that documentation from the link that you provided is quite actual, probably it was published when Xtensa was owned by Tensilica. Also, the code can be reviewed by people from companies that use Xtensa IP in their chips.

That seems really silly -- why wouldn't someone want all users of their CPUs to be able to easily access the ISA docs. Oh well.

Anyways, are there some folks who know LLVM and do have access to the official documentation who can help review the patches? (Maybe asking on the mailing list thread would be useful.)

BTW there is also an ARC backend (from Synopsys), and I have not found any public documentation with ARC ISA, so probably encoding of ARC instructions also could be verified only by Synopsys engineers.

Also we could prepare summary about Xtensa ISA based on public resources like GCC, Binutils, QEMU with quality enough for code review. What do you think?

I think a short summary of the general characteristics of the CPU/ISA would be useful. I do not think that it would be a productive use of time to attempt to reverse-engineer/rewrite an entire ISA doc -- having such a reverse-engineered and possibly incorrect or outdated doc might even be worse than not having it. But I do not think lack of public documentation should be a blocker for inclusion, especially if there are folks who do have access to the privately-available documentation who can help review.

@andreisfr @jyknight @ivanbaev Ping? Are there any news concerning these pull requests?

@andreisfr @jyknight @ivanbaev Ping? Are there any news concerning these pull requests?

From my point of view, this is waiting for the submitter to follow up (or someone may take over).

andreisfr added a comment.EditedJan 17 2020, 4:07 AM

@codehippo, @jyknight, @ivanbaev , we still active develop and improve Xtensa backend, for example this is recent version https://github.com/espressif/llvm-project/tree/xtensa_release_9.x currently we maintain mainstream version and we plan to publish one based on release 10. Current review is paused on *.td files with Xtensa ISA description after the question about ISA documentation, we have been tried to find a way how to help reviewers to aprove this code. We interested to integrate Xtensa backend to upstream and make it available to LLVM community, so we are going to prepare Xtensa ISA description based on opensource projects like binutils, gcc etc. It seems to be the only way to continue review process. What do you think?

andreisfr updated this revision to Diff 242205.Feb 3 2020, 3:14 PM

Patch is updated according to latest upstream version. Updated licenses.

@jyknight, @ivanbaev , currently is available Xtensa backend based on latest 9.0.1 release https://github.com/espressif/llvm-project/tree/xtensa_release_9.0.1

@appcs Do you perhaps have access to the ISA documentation so you can review these patches?

andreisfr marked an inline comment as done.Feb 9 2020, 4:54 PM

@andreisfr Has any progress been made on the reverse-engineered Xtensa ISA based on the open-source projects like gcc and binutils?

Not sure how relevant it is, but I found this PDF which seems to be some documentation for the ISA.

https://0x04.net/~mwk/doc/xtensa.pdf

lattner removed a subscriber: lattner.Aug 29 2020, 9:19 PM
brainstorm added a comment.EditedJan 18 2021, 2:26 AM

Hello LLVM,

I own an Xtensa ISA document from 2015 and I can confirm that the 2010 ISA document linked above (https://0x04.net/~mwk/doc/xtensa.pdf as @philip-peterson points out) is sufficient to proceed with this review since the changes between those two documents are not that substantial on a first pass. So please, could you take that 0x04.net as authoritative source for this review?

I'd be happy to help review corner cases as they pop up if need be, @ivanbaev @jyknight.

Please bear with me LLVM maintainers since I've never upstreamed a compiler backend, but is there any other document than https://www.llvm.org/docs/WritingAnLLVMBackend.html which outlines the comformance testing required to get this xtensa work in-tree? I would like to see this backend supported in LLVM after all the effort that @andreisfr and others have put into this.

jscott added a subscriber: jscott.Jan 20 2021, 1:07 PM

@andreisfr I don't seen any major issues being raised with this backend. It would be great if there was a public official ISA document, but I don't think the lack of one is a blocker. Please make a last check of the reviews in phabricato to see if there are any outstanding issues. Then, I would recommend you take a look at the documentation @tonic posted. Specifically the 5 bullet points under the "The basic rules for a back-end to be upstreamed in experimental mode are:" header. If you think you meet those requirements, please re-send the RFC to the list, so we can discuss getting this added.

andreisfr added a comment.EditedJan 24 2021, 5:14 PM

@brainstorm , @tonic , @tstellar , thank you very much for your help!

I support and improve Xtensa backend now, current version of the backend is rebased on release 11.0.0 https://github.com/espressif/llvm-project/tree/xtensa_release_11.0.0 .

@tstellar , so I can just update these 10 patches according to latest changes in LLVM, add myself as code owner in the first patch and send patches again to list (I will recheck outstanding issues)?

@brainstorm , @tonic , @tstellar , thank you very much for your help!

I support and improve Xtensa backend now, current version of the backend is rebased on release 11.0.0 https://github.com/espressif/llvm-project/tree/xtensa_release_11.0.0 .

@tstellar , so I can just update these 10 patches according to latest changes in LLVM, add myself as code owner in the first patch and send patches again to list (I will recheck outstanding issues)?

@andreisfr Yes, that sounds good.

aykevl added a comment.Mar 4 2021, 6:45 AM

@andreisfr any update on this?

It would be great if you could update these patches and send a new RFC to llvm-dev, like you did here: https://lists.llvm.org/pipermail/llvm-dev/2019-March/130796.html

aykevl added a comment.EditedMar 4 2021, 4:31 PM

Also, there is an emulator here: https://github.com/espressif/qemu/wiki
I have successfully used it in the past. Noting it here as it can make backend review/development easier for those who don't have the hardware.

@aykevl , I prepared new version of patches and I will update them in 1 day.

andreisfr updated this revision to Diff 328695.EditedMar 5 2021, 4:44 PM

Patch is updated according to LLVM upstream version and latest Xtensa backend version.

aykevl added a comment.Mar 9 2021, 2:28 PM

@andreisfr awesome! Thanks a lot!

Can you please also write a new RFC and send it to llvm-dev like @tstellar proposed? An RFC is the next step in getting this backend accepted.

If you think you meet those requirements, please re-send the RFC to the list, so we can discuss getting this added.

craig.topper added inline comments.
llvm/lib/Target/Xtensa/Xtensa.td
2

Please limit line length to 80 characters

llvm/lib/Target/Xtensa/XtensaInstrFormats.td
2

Please limit line length to 80 characters

15

I think the prevailing style in LLVM has the open curly brace at the end of the previous line.

32

It might just be me, but I find this lining the XtensaInst up with template parameters hard to read. I think a common style is to put at the start of the line with only a small indentation. For example

class PseudoI<dag oops, dag iops, list<dag> pattern>                                                                                                                                                                                                                                   
  : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {                                                                                                                                                                                                                                        
  let Pattern = pattern;                                                                                                                                                                                                                                                               
}
llvm/lib/Target/Xtensa/XtensaOperands.td
2

This line seems shorter than 80 characters.

andreisfr updated this revision to Diff 335949.Wed, Apr 7, 4:40 PM

Correct instruction descriptions, format descriptions and instruction operands according to common style for *.td files.

andreisfr added inline comments.Wed, Apr 7, 4:47 PM
llvm/lib/Target/Xtensa/Xtensa.td
2

Corrected

llvm/lib/Target/Xtensa/XtensaInstrFormats.td
2

Corrected

15

Corrected for instruction descriptions, format descriptions and instruction operands.

32

@craig.topper , I corrected instruction formats and instruction descriptions, do you think that this code now in common style or it must be corrected bit more?

llvm/lib/Target/Xtensa/XtensaOperands.td
2

Corrected

@craig.topper , thank you very much for comments!

craig.topper added inline comments.Thu, Apr 8, 3:01 PM
llvm/lib/Target/Xtensa/XtensaInstrFormats.td
32

I think this looks better. Unfortunately, we don't have a formatting tool for tablegen and no rules are written down. I think this is good enough.

167

Drop the second blank line?

llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
31

This is overindented relative to the style of the rest of the file.

andreisfr updated this revision to Diff 336425.Fri, Apr 9, 6:09 AM

Corrected indentation, removed blank line

llvm/lib/Target/Xtensa/XtensaInstrFormats.td
167

Corrected

llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
31

Corrected