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andreisfr (Andrei Safronov)
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User Since
Jul 16 2019, 2:20 PM (13 w, 1 d)

Recent Activity

Aug 18 2019

andreisfr added a comment to D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code..

@aykevl, I'm not sure whether we currently could upload patch 1/10, because there are some questions in patch 4/10 about ISA(we currently have just opensource projects and unofficial documents with Xtensa ISA description). You could participate in this discussion to move the Xtensa backend forward.

Aug 18 2019, 9:33 AM · Restricted Project

Jul 31 2019

andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

I sent RFC to LLVM community on 6 March http://lists.llvm.org/pipermail/llvm-dev/2019-March/130796.html

Jul 31 2019, 5:29 PM · Restricted Project
andreisfr added inline comments to D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..
Jul 31 2019, 4:51 PM · Restricted Project
andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

As for Xtensa instruction set architecture (ISA) document , currently public ISA description mainly available in opensource projects like gcc/qemu/binutils:
https://github.com/gcc-mirror/gcc/tree/master/gcc/config/xtensa
https://github.com/qemu/qemu/blob/master/target/xtensa/translate.c
https://github.com/bminor/binutils-gdb/blob/master/bfd/xtensa-modules.c

Jul 31 2019, 4:19 PM · Restricted Project
andreisfr updated the diff for D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions..

Register names are capitalized.

Jul 31 2019, 4:08 PM · Restricted Project
andreisfr updated the diff for D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler..

Register names are capitalized.

Jul 31 2019, 4:07 PM · Restricted Project
andreisfr updated the diff for D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..

Register names are capitalized.

Jul 31 2019, 4:05 PM · Restricted Project
andreisfr updated the diff for D64833: [Xtensa 7/10] Add Xtensa instruction printer..

Register names are capitalized.

Jul 31 2019, 4:00 PM · Restricted Project
andreisfr updated the diff for D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality..

Register names are capitalized.

Jul 31 2019, 3:53 PM · Restricted Project
andreisfr updated the diff for D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

Register names are capitalized.

Jul 31 2019, 3:53 PM · Restricted Project

Jul 17 2019

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Jul 17 2019, 3:12 PM · Restricted Project

Jul 16 2019

andreisfr created D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64833: [Xtensa 7/10] Add Xtensa instruction printer..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64832: [Xtensa 6/10] Add Xtensa basic assembler parser..
Jul 16 2019, 3:24 PM · Restricted Project
andreisfr created D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality..
Jul 16 2019, 3:23 PM · Restricted Project
andreisfr created D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..
Jul 16 2019, 3:21 PM · Restricted Project
andreisfr created D64829: [Xtensa 3/10] Add initial version of the Xtensa backend..
Jul 16 2019, 3:19 PM · Restricted Project
andreisfr created D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Jul 16 2019, 3:18 PM · Restricted Project
andreisfr created D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code..
Jul 16 2019, 3:17 PM · Restricted Project