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andreisfr (Andrei Safronov)
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User Since
Jul 16 2019, 2:20 PM (55 w, 4 d)

Recent Activity

Feb 28 2020

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 28 2020, 4:25 PM · Restricted Project
andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 28 2020, 4:07 PM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Correct relocations test for the Xtensa target

Feb 28 2020, 4:07 PM · Restricted Project

Feb 19 2020

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 19 2020, 3:46 AM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Correction of comments and Xtensa ELF flags test.

Feb 19 2020, 3:21 AM · Restricted Project

Feb 16 2020

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 16 2020, 4:13 PM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Correct Xtensa ELF flag test

Feb 16 2020, 3:55 PM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Change EF_XTENSA_MACH_BASE to EF_XTENSA_MACH_NONE, it seems this is closer to ELF flag naming style used for AMDGPU and MIPS.

Feb 16 2020, 3:10 PM · Restricted Project

Feb 12 2020

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 12 2020, 12:52 PM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Correction of the llvm/test/Object/obj2yaml.test, now Xtensa test uses yaml2obj instead of pre-built binary trivial-object-test.elf-xtensa.

Feb 12 2020, 12:52 PM · Restricted Project
andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 12 2020, 4:32 AM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Correction of the llvm/test/tools/ llvm-readobj/ELF/reloc-types-elf-xtensa.test file (renaming to reloc-types-xtensa.test, and also delete the empty line at the end of file).

Feb 12 2020, 4:14 AM · Restricted Project

Feb 9 2020

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Feb 9 2020, 4:56 PM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Add Xtensa ELF relocations test. Move ELF flags test from "llvm/test/Object/Xtensa/" directory to test/Object/obj2yaml.test.

Feb 9 2020, 4:47 PM · Restricted Project

Feb 3 2020

andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

@jyknight, @ivanbaev , currently is available Xtensa backend based on latest 9.0.1 release https://github.com/espressif/llvm-project/tree/xtensa_release_9.0.1

Feb 3 2020, 3:34 PM · Restricted Project
andreisfr updated the diff for D64832: [Xtensa 6/10] Add Xtensa basic assembler parser..

Patch is updated according to latest upstream version. Updated licenses.

Feb 3 2020, 3:24 PM · Restricted Project
andreisfr updated the diff for D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler..

Patch is updated according to latest upstream version. Updated licenses.

Feb 3 2020, 3:24 PM · Restricted Project
andreisfr updated the diff for D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions..

Patch is updated according to latest upstream version. Updated licenses.

Feb 3 2020, 3:24 PM · Restricted Project
andreisfr updated the diff for D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..

Patch is updated according to latest upstream version.

Feb 3 2020, 3:24 PM · Restricted Project
andreisfr updated the diff for D64833: [Xtensa 7/10] Add Xtensa instruction printer..

Patch is updated according to latest upstream version. Updated licenses.

Feb 3 2020, 3:24 PM · Restricted Project
andreisfr updated the diff for D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality..

Patch is updated according to latest upstream version. Updated licenses, added CFI encoding for Xtensa target

Feb 3 2020, 3:16 PM · Restricted Project
andreisfr updated the diff for D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

Patch is updated according to latest upstream version. Updated licenses.

Feb 3 2020, 3:14 PM · Restricted Project
andreisfr updated the diff for D64829: [Xtensa 3/10] Add initial version of the Xtensa backend..

Patch is updated according to latest upstream version. Updated licenses.

Feb 3 2020, 3:04 PM · Restricted Project
andreisfr updated the diff for D64827: [Xtensa 2/10] Add Xtensa ELF definitions..

Patch is updated according to latest upstream version. The E_XTENSA_MACH_BASE symbol changed to EF_XTENSA_MACH_BASE.

Feb 3 2020, 3:04 PM · Restricted Project
andreisfr updated the diff for D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code..

Patch is updated according to latest upstream version.

Feb 3 2020, 3:04 PM · Restricted Project

Jan 24 2020

andreisfr committed rG04a9081ecc69: [Xtensa] Add Xtensa subtarget features. (authored by andreisfr).
[Xtensa] Add Xtensa subtarget features.
Jan 24 2020, 3:04 AM
andreisfr committed rG28f6b2af48b4: [Xtensa] Add many code improvements of Xtensa backend in single patch (modify… (authored by gerekon).
[Xtensa] Add many code improvements of Xtensa backend in single patch (modify…
Jan 24 2020, 3:04 AM
andreisfr committed rG0db191089d73: [Xtensa] Add FPR and BR register class (authored by andreisfr).
[Xtensa] Add FPR and BR register class
Jan 24 2020, 3:04 AM
andreisfr committed rG67730fbda7ff: [Xtensa] Implement lowering SELECT_CC, SETCC (authored by andreisfr).
[Xtensa] Implement lowering SELECT_CC, SETCC
Jan 24 2020, 3:04 AM
andreisfr committed rGa89dc46e6058: [Xtensa] Implement assembler representation of the Constant Pool (authored by andreisfr).
[Xtensa] Implement assembler representation of the Constant Pool
Jan 24 2020, 3:04 AM
andreisfr committed rG0de87badc447: [Xtensa] Implement emitPrologue/emitEpilogue (authored by andreisfr).
[Xtensa] Implement emitPrologue/emitEpilogue
Jan 24 2020, 3:04 AM
andreisfr committed rG0ceede6be37c: [Xtensa] Add support of the Xtensa function calls (authored by andreisfr).
[Xtensa] Add support of the Xtensa function calls
Jan 24 2020, 3:03 AM
andreisfr committed rG353906216f7a: [Xtensa] Add Constant Pool (authored by andreisfr).
[Xtensa] Add Constant Pool
Jan 24 2020, 3:03 AM
andreisfr committed rG0bdd3c8d0556: [Xtensa] Initial codegen support for simple ALU operations (authored by andreisfr).
[Xtensa] Initial codegen support for simple ALU operations
Jan 24 2020, 3:03 AM
andreisfr committed rG6d74874a523e: [Xtensa] Add Xtensa target ABI support to clang (authored by andreisfr).
[Xtensa] Add Xtensa target ABI support to clang
Jan 24 2020, 3:03 AM
andreisfr committed rG7934cf9cee99: [Xtensa] Add Xtensa target to clang (authored by andreisfr).
[Xtensa] Add Xtensa target to clang
Jan 24 2020, 3:03 AM
andreisfr committed rG8d97fd948aa2: [Xtensa] Add support of the rest part of Xtensa Core Instructions. Add… (authored by andreisfr).
[Xtensa] Add support of the rest part of Xtensa Core Instructions. Add…
Jan 24 2020, 3:03 AM
andreisfr committed rGad738ea51ac2: [Xtensa] Add basic support of Xtensa disassembler. (authored by andreisfr).
[Xtensa] Add basic support of Xtensa disassembler.
Jan 24 2020, 3:03 AM
andreisfr committed rG497fe4e6527b: [Xtensa] Add descriptions of the Xtensa shift/load/store instructions. (authored by andreisfr).
[Xtensa] Add descriptions of the Xtensa shift/load/store instructions.
Jan 24 2020, 3:03 AM
andreisfr committed rGb468b816085b: [Xtensa] Add basic Xtensa instruction printer. Add basic tests of the Xtensa… (authored by andreisfr).
[Xtensa] Add basic Xtensa instruction printer. Add basic tests of the Xtensa…
Jan 24 2020, 3:03 AM
andreisfr committed rGadcda12c0df1: [Xtensa] Add Xtensa basic assembler parser. (authored by andreisfr).
[Xtensa] Add Xtensa basic assembler parser.
Jan 24 2020, 3:03 AM
andreisfr committed rGcdcba48e91a0: [Xtensa] Add Xtensa MCTargetDescr initial functionality. (authored by andreisfr).
[Xtensa] Add Xtensa MCTargetDescr initial functionality.
Jan 24 2020, 3:03 AM
andreisfr committed rGdc199157c6a8: [Xtensa] Add basic *td files with Xtensa architecture description, like Xtensa. (authored by andreisfr).
[Xtensa] Add basic *td files with Xtensa architecture description, like Xtensa.
Jan 24 2020, 3:03 AM
andreisfr committed rG4e8c960f035e: [Xtensa] Add initial version of the Xtensa backend. (authored by andreisfr).
[Xtensa] Add initial version of the Xtensa backend.
Jan 24 2020, 3:03 AM

Jan 17 2020

andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

@codehippo, @jyknight, @ivanbaev , we still active develop and improve Xtensa backend, for example this is recent version https://github.com/espressif/llvm-project/tree/xtensa_release_9.x currently we maintain mainstream version and we plan to publish one based on release 10. Current review is paused on *.td files with Xtensa ISA description after the question about ISA documentation, we have been tried to find a way how to help reviewers to aprove this code. We interested to integrate Xtensa backend to upstream and make it available to LLVM community, so we are going to prepare Xtensa ISA description based on opensource projects like binutils, gcc etc. It seems to be the only way to continue review process. What do you think?

Jan 17 2020, 4:07 AM · Restricted Project

Nov 6 2019

andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

I'd note that Lanai did publish a set of ISA docs as part of upstreaming the llvm backend.

Having something like that perhaps doesn't need to be a hard-blocker, but I'd love to see a real response from the xtensa folks, since AFAICT it looks as if like there *IS* ISA documentation, just perhaps not -- officially -- publicly available. It would make things much easier to understand if xtensa published what they had. Without that, nobody else can really review or understand the backend.

Nov 6 2019, 5:29 PM · Restricted Project

Aug 18 2019

andreisfr added a comment to D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code..

@aykevl, I'm not sure whether we currently could upload patch 1/10, because there are some questions in patch 4/10 about ISA(we currently have just opensource projects and unofficial documents with Xtensa ISA description). You could participate in this discussion to move the Xtensa backend forward.

Aug 18 2019, 9:33 AM · Restricted Project

Jul 31 2019

andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

I sent RFC to LLVM community on 6 March http://lists.llvm.org/pipermail/llvm-dev/2019-March/130796.html

Jul 31 2019, 5:29 PM · Restricted Project
andreisfr added inline comments to D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..
Jul 31 2019, 4:51 PM · Restricted Project
andreisfr added a comment to D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

As for Xtensa instruction set architecture (ISA) document , currently public ISA description mainly available in opensource projects like gcc/qemu/binutils:
https://github.com/gcc-mirror/gcc/tree/master/gcc/config/xtensa
https://github.com/qemu/qemu/blob/master/target/xtensa/translate.c
https://github.com/bminor/binutils-gdb/blob/master/bfd/xtensa-modules.c

Jul 31 2019, 4:19 PM · Restricted Project
andreisfr updated the diff for D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions..

Register names are capitalized.

Jul 31 2019, 4:08 PM · Restricted Project
andreisfr updated the diff for D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler..

Register names are capitalized.

Jul 31 2019, 4:07 PM · Restricted Project
andreisfr updated the diff for D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..

Register names are capitalized.

Jul 31 2019, 4:05 PM · Restricted Project
andreisfr updated the diff for D64833: [Xtensa 7/10] Add Xtensa instruction printer..

Register names are capitalized.

Jul 31 2019, 4:00 PM · Restricted Project
andreisfr updated the diff for D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality..

Register names are capitalized.

Jul 31 2019, 3:53 PM · Restricted Project
andreisfr updated the diff for D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..

Register names are capitalized.

Jul 31 2019, 3:53 PM · Restricted Project

Jul 17 2019

andreisfr added inline comments to D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Jul 17 2019, 3:12 PM · Restricted Project

Jul 16 2019

andreisfr created D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64833: [Xtensa 7/10] Add Xtensa instruction printer..
Jul 16 2019, 3:32 PM · Restricted Project
andreisfr created D64832: [Xtensa 6/10] Add Xtensa basic assembler parser..
Jul 16 2019, 3:24 PM · Restricted Project
andreisfr created D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality..
Jul 16 2019, 3:23 PM · Restricted Project
andreisfr created D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description..
Jul 16 2019, 3:21 PM · Restricted Project
andreisfr created D64829: [Xtensa 3/10] Add initial version of the Xtensa backend..
Jul 16 2019, 3:19 PM · Restricted Project
andreisfr created D64827: [Xtensa 2/10] Add Xtensa ELF definitions..
Jul 16 2019, 3:18 PM · Restricted Project
andreisfr created D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code..
Jul 16 2019, 3:17 PM · Restricted Project