[ARM] Add MVE horizontal accumulation instructions.

[miyuki]

Summary

This is the family of vector instructions that combine all the lanes
in their input vector(s), and output a value in one or two GPRs.

[ostannard]

llvm/lib/Target/ARM/ARMInstrMVE.td

367

There seems to be a lot of repetition here, could some of these classes be combined? For example most bits of t2VMINNM, t2VMINV, t2VMAXNMV and t2VMAX are the same. Could we also use multiclasses to avoid repeating the list of types for each of the MIN and MAX versions of these instructions?

Also, is the a pattern to whether these names end in "V" which I've missed, or could they be made more consistent?

382

What is this comment adding?

487

Again, the t2VMLADAV and t2VMLSDAV classes share most of their bits, and could be merged.

llvm/test/MC/ARM/mve-reductions.s

14

We could avoid repeating all of these check lines by either adding a new check-prefix shared between the two runs, or moving the FP instructions to a separate file. As noted in previous reviews, we should also be checking the error message when the FP instructions are rejected.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrMVE.td

307

As a corollary to what Oliver was saying. The VADDV (or in VADDVs8no_acc) doesn't really take a Rda_src, I believe. At least the structure you would match from llvm would not. There's a perfectly good chance it's possible and I just don't know how to represent that in a pattern. But it seems more natural to make sure that VADDVs*no_acc don't require a Rda_src.

When I looked at this downstream, I just ended up splitting this into two classes.

[simon_tatham]

Remastered patch to apply cleanly against current trunk.

[miyuki]

llvm/lib/Target/ARM/ARMInstrMVE.td

307

But it seems more natural to make sure that VADDVs*no_acc don't require a Rda_src.

This also pertains to VMLADAV, VMLSDAV, etc, right?

[miyuki]

• Fixed naming inconsistencies
• Removed comments about undefined instructions
• Factored out common parts of:
  • VMINV and VMAXV
  • VMINNMV and VMAXNMV
  • VMLADAV and VMLSDAV
  • VMLALDAV, VMLSLDAV (includes VRMLSLDAVH) and VRMLALDAVH
• Fixed inputs and constraints of non-accumulating instructions
• Split the assembler test into integer and floating point parts

[dmgreen]

LGTM, if Oliver is also happy

[ostannard]

llvm/lib/Target/ARM/ARMInstrMVE.td

308

This class is only instantiated once with each value of A, so I think it would be clearer to make these parameters and move the values down to the multiclass below.

457

Again, this is quite hard to follow, I think it would be better to move the operand lists down to the multiclass.

[miyuki]

llvm/lib/Target/ARM/ARMInstrMVE.td

457

But this would mean duplicating everything (i.e., input operands and constraints) 4 times for each case. And 6 times for t2VMLALDAVBase. Wouldn't it be better to create separate subclasses for accumulating and non-accumulating versions?

[miyuki]

• Rebase
• Avoid TableGen logic in instruction operands and constraints

[ostannard]

LGTM

llvm/lib/Target/ARM/ARMInstrFormats.td

 class VFP2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
       : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2]>;
 class VFP2DPInstAlias<string Asm, dag Result, bit EmitPriority = 0>
       : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2,HasDPVFP]>;
 class VFP3InstAlias<string Asm, dag Result, bit EmitPriority = 0>
       : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
 class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
       : InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
+class MVEInstAlias<string Asm, dag Result, bit EmitPriority = 1>
+      : InstAlias<Asm, Result, EmitPriority>, Requires<[HasMVEInt, IsThumb]>;
 
 
 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
           Requires<[HasVFP2]>;
 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
           Requires<[HasNEON]>;
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/ARM/ARMInstrMVE.td

 
 def VABAVs8  : t2VABAV<"s8", 0b0, 0b00>;
 def VABAVs16 : t2VABAV<"s16", 0b0, 0b01>;
 def VABAVs32 : t2VABAV<"s32", 0b0, 0b10>;
 def VABAVu8  : t2VABAV<"u8", 0b1, 0b00>;
 def VABAVu16 : t2VABAV<"u16", 0b1, 0b01>;
 def VABAVu32 : t2VABAV<"u32", 0b1, 0b10>;
 
+class t2VADDV<string suffix, bit A, string acc, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$Rda), (ins tGPREven:$Rda_src, MQPR:$Qm), NoItinerary,
+              !strconcat("vaddv", acc), suffix, "$Rda, $Qm", "$Rda = $Rda_src",
+              pattern> {
+  bits<3> Qm;
+  bits<4> Rda;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b111;
+  let Inst{19-18} = size{1-0};
+  let Inst{17-16} = 0b01;
+  let Inst{15-13} = Rda{3-1};
+  let Inst{12} = 0b0;
+  let Inst{8-6} = 0b100;
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VADDV_A<string suffix, bit U, bits<2> size, list<dag> pattern=[]> {
+  def acc : t2VADDV<suffix, 1, "a", U, size>;
+  def no_acc : t2VADDV<suffix, 0, "", U, size>;
+}
+
+defm VADDVs8  : t2VADDV_A<"s8", 0b0, 0b00>;
+defm VADDVs16 : t2VADDV_A<"s16", 0b0, 0b01>;
+defm VADDVs32 : t2VADDV_A<"s32", 0b0, 0b10>;
+defm VADDVu8  : t2VADDV_A<"u8", 0b1, 0b00>;
+defm VADDVu16 : t2VADDV_A<"u16", 0b1, 0b01>;
+defm VADDVu32 : t2VADDV_A<"u32", 0b1, 0b10>;
+
+class t2VADDLV<string suffix, bit A, string acc, bit U, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), (ins tGPREven:$RdaLo_src,
+              tGPROdd:$RdaHi_src, MQPR:$Qm), NoItinerary, !strconcat("vaddlv", acc),
+              suffix, "$RdaLo, $RdaHi, $Qm", "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
+              pattern> {
+  bits<3> Qm;
+  bits<4> RdaLo;
+  bits<4> RdaHi;
+
+  let Inst{28} = U;
+  let Inst{22-20} = RdaHi{3-1};
+  let Inst{19-18} = 0b10;
+  let Inst{17-16} = 0b01;
+  let Inst{15-13} = RdaLo{3-1};
+  let Inst{12} = 0b0;
+  let Inst{8-6} = 0b100;
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
+  def acc : t2VADDLV<suffix, 1, "a", U>;
+  def no_acc : t2VADDLV<suffix, 0, "", U>;
+}
+
+
+defm VADDLVs32 : t2VADDLV_A<"s32", 0b0>;
+defm VADDLVu32 : t2VADDLV_A<"u32", 0b1>;
+
+class t2VMINNM<string iname, string suffix, bit sz, bit bit_17,
+               list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<3> Qm;
+  bits<4> RdaDest;
+
+  let Inst{28} = sz;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = 0b11;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b110;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+multiclass t2VMINNM_fty<string iname, bit bit_17, list<dag> pattern=[]> {
+  def f32 : t2VMINNM<iname, "f32", 0b0, bit_17>;
+  def f16 : t2VMINNM<iname, "f16", 0b1, bit_17>;
+}
+
+defm VMINNMV : t2VMINNM_fty<"vminnmv", 0b1>;
+defm VMINNMAV : t2VMINNM_fty<"vminnmav", 0b0>;
+
+class t2VMINV<string iname, string suffix, bit U, bits<2> size,
+              bit bit_17, list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm), NoItinerary,
+              iname, suffix, "$RdaSrc, $Qm", "$RdaDest = $RdaSrc", pattern> {
+  bits<3> Qm;
+  bits<4> RdaDest;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = size{1-0};
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b110;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+// Prefixed with MVE to prevent conflict with A57 scheduler.
+def MVE_VMINVs8  : t2VMINV<"vminv", "s8", 0b0, 0b00, 0b1>;
+def MVE_VMINVs16 : t2VMINV<"vminv", "s16", 0b0, 0b01, 0b1>;
+def MVE_VMINVs32 : t2VMINV<"vminv", "s32", 0b0, 0b10, 0b1>;
+def MVE_VMINVu8  : t2VMINV<"vminv", "u8", 0b1, 0b00, 0b1>;
+def MVE_VMINVu16 : t2VMINV<"vminv", "u16", 0b1, 0b01, 0b1>;
+def MVE_VMINVu32 : t2VMINV<"vminv", "u32", 0b1, 0b10, 0b1>;
+
+def MVE_VMINAVs8  : t2VMINV<"vminav", "s8", 0b0, 0b00, 0b0>;
+def MVE_VMINAVs16 : t2VMINV<"vminav", "s16", 0b0, 0b01, 0b0>;
+def MVE_VMINAVs32 : t2VMINV<"vminav", "s32", 0b0, 0b10, 0b0>;
+
+class t2VMAXNMV<string iname, string suffix, bit sz, bit bit_17,
+                list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+
+  let Inst{28} = sz;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = 0b11;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b100;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VMAXNMVf32 : t2VMAXNMV<"vmaxnmv", "f32", 0b0, 0b1>;
+def VMAXNMVf16 : t2VMAXNMV<"vmaxnmv", "f16", 0b1, 0b1>;
+
+def VMAXNMAVf32 : t2VMAXNMV<"vmaxnmav", "f32", 0b0, 0b0>;
+def VMAXNMAVf16 : t2VMAXNMV<"vmaxnmav", "f16", 0b1, 0b0>;
+
+class t2VMAX<string iname, string suffix, bit U, bits<2> size, bit bit_17,
+                list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = size{1-0};
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b100;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+def MVE_VMAXVs8  : t2VMAX<"vmaxv", "s8", 0b0, 0b00, 0b1>;
+def MVE_VMAXVs16 : t2VMAX<"vmaxv", "s16", 0b0, 0b01, 0b1>;
+def MVE_VMAXVs32 : t2VMAX<"vmaxv", "s32", 0b0, 0b10, 0b1>;
+def MVE_VMAXVu8  : t2VMAX<"vmaxv", "u8", 0b1, 0b00, 0b1>;
+def MVE_VMAXVu16 : t2VMAX<"vmaxv", "u16", 0b1, 0b01, 0b1>;
+def MVE_VMAXVu32 : t2VMAX<"vmaxv", "u32", 0b1, 0b10, 0b1>;
+
+def MVE_VMAXAVs8  : t2VMAX<"vmaxav", "s8", 0b0, 0b00, 0b0>;
+def MVE_VMAXAVs16 : t2VMAX<"vmaxav", "s16", 0b0, 0b01, 0b0>;
+def MVE_VMAXAVs32 : t2VMAX<"vmaxav", "s32", 0b0, 0b10, 0b0>;
+
+class t2VMLADAV<string iname, string suffix, bit sz, bit U,
+                bit A, bit X, bit bit_8, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaDest), (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
+              NoItinerary, !strconcat(iname, !if(!eq(A, 1), "a", ""),
+              !if(!eq(X, 1), "x", "")), suffix, "$RdaSrc, $Qn, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b111;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaDest{3-1};
+  let Inst{12} = X; // undefined if 1
+  let Inst{8} = bit_8;
+  let Inst{7-6} = 0b00; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VMLADAV_multi<string iname, string suffix, bit sz, bit U,
+                           bit bit_8, list<dag> pattern=[]> {
+  def acc_noexch : t2VMLADAV<iname, suffix, sz, U, 0b1, 0b0, bit_8, pattern>;
+  def noacc_exch : t2VMLADAV<iname, suffix, sz, U, 0b0, 0b1, bit_8, pattern>;
+  def acc_exch : t2VMLADAV<iname, suffix, sz, U, 0b1, 0b1, bit_8, pattern>;
+  def noacc_noexch : t2VMLADAV<iname, suffix, sz, U, 0b0, 0b0, bit_8, pattern>;
+}
+
+defm VMLADAVs16 : t2VMLADAV_multi<"vmladav", "s16", 0b0, 0b0, 0b0>;
+defm VMLADAVs32 : t2VMLADAV_multi<"vmladav", "s32", 0b1, 0b0, 0b0>;
+defm VMLADAVu16 : t2VMLADAV_multi<"vmladav", "u16", 0b0, 0b1, 0b0>;
+defm VMLADAVu32 : t2VMLADAV_multi<"vmladav", "u32", 0b1, 0b1, 0b0>;
+
+defm VMLADAVs8 : t2VMLADAV_multi<"vmladav", "s8", 0b0, 0b0, 0b1>;
+defm VMLADAVu8 : t2VMLADAV_multi<"vmladav", "u8", 0b0, 0b1, 0b1>;
+
+// vmlav aliases vmladav
+foreach acc = ["acc", "noacc"] in {
+  foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
+    def : MVEInstAlias<!strconcat("vmlav", !if(!eq(acc, "acc"), "a", ""),
+                       "${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
+                       (!cast<Instruction>(!strconcat("VMLADAV", suffix, acc, "_noexch")) tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+  }
+}
+
+class t2VRMLALDAVH<string iname, string suffix, bit U, bit A,
+                   bit X, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), (ins tGPREven:$RdaLoSrc,
+              tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm), NoItinerary, !strconcat(iname,
+              !if(!eq(A, 1), "a", ""), !if(!eq(X, 1), "x", "")), suffix,
+              "$RdaLoSrc, $RdaHiSrc, $Qn, $Qm", "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
+              pattern> {
+  bits<4> RdaLoDest;
+  bits<4> RdaHiDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = U;
+  let Inst{22-20} = RdaHiDest{3-1};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = RdaLoDest{3-1};
+  let Inst{12} = X;
+  let Inst{8-6} = 0b100; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VRMLALDAVH_multi<string iname, string suffix, bit U,
+                              list<dag> pattern=[]> {
+  def acc_noexch : t2VRMLALDAVH<iname, suffix, U, 0b1, 0b0, pattern>;
+  def noacc_exch : t2VRMLALDAVH<iname, suffix, U, 0b0, 0b1, pattern>;
+  def acc_exch : t2VRMLALDAVH<iname, suffix, U, 0b1, 0b1, pattern>;
+  def noacc_noexch : t2VRMLALDAVH<iname, suffix, U, 0b0, 0b0, pattern>;
+}
+
+defm t2VRMLALDAVHs32 : t2VRMLALDAVH_multi<"vrmlaldavh", "s32", 0>;
+defm t2VRMLALDAVHu32 : t2VRMLALDAVH_multi<"vrmlaldavh", "u32", 1>;
+
+// vrmlalvh aliases for vrmlaldavh
+def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHs32noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHs32acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHu32noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHu32acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+
+class t2VMLSDAV<string iname, string suffix, bit sz, bit A,
+                bit X, bit bit_28, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaDest), (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
+              NoItinerary, !strconcat(iname, !if(!eq(A, 1), "a", ""),
+              !if(!eq(X, 1), "x", "")), suffix, "$RdaSrc, $Qn, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{22-20} = 0b111;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaDest{3-1};
+  let Inst{12} = X;
+  let Inst{8-6} = 0b000; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+multiclass t2VMLSDAV_multi<string iname, string suffix, bit sz,
+                           bit bit_28, list<dag> pattern=[]> {
+  def acc_noexch : t2VMLSDAV<iname, suffix, sz, 0b1, 0b0, bit_28, pattern>;
+  def noacc_exch : t2VMLSDAV<iname, suffix, sz, 0b0, 0b1, bit_28, pattern>;
+  def acc_exch : t2VMLSDAV<iname, suffix, sz, 0b1, 0b1, bit_28, pattern>;
+  def noacc_noexch : t2VMLSDAV<iname, suffix, sz, 0b0, 0b0, bit_28, pattern>;
+}
+
+defm t2VMLSDAVs8  : t2VMLSDAV_multi<"vmlsdav", "s8", 0, 0b1>;
+defm t2VMLSDAVs16 : t2VMLSDAV_multi<"vmlsdav", "s16", 0, 0b0>;
+defm t2VMLSDAVs32 : t2VMLSDAV_multi<"vmlsdav", "s32", 1, 0b0>;
+
+class t2VMLALDAV<string iname, string suffix, bit sz, bit U, bit A,
+                   bit X, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), (ins tGPREven:$RdaLoSrc,
+              tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm), NoItinerary, !strconcat(iname,
+              !if(!eq(A, 1), "a", ""), !if(!eq(X, 1), "x", "")), suffix,
+              "$RdaLoSrc, $RdaHiSrc, $Qn, $Qm",
+              "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc", pattern> {
+  bits<4> RdaLoDest;
+  bits<4> RdaHiDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = U;
+  let Inst{22-20} = RdaHiDest{3-1};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaLoDest{3-1};
+  let Inst{12} = X;
+  let Inst{8-6} = 0b000; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VMLALDAV_multi<string iname, string suffix, bit sz,
+                            bit U, list<dag> pattern=[]> {
+  def acc_noexch : t2VMLALDAV<iname, suffix, sz, U, 0b1, 0b0, pattern>;
+  def noacc_exch : t2VMLALDAV<iname, suffix, sz, U, 0b0, 0b1, pattern>;
+  def acc_exch : t2VMLALDAV<iname, suffix, sz, U, 0b1, 0b1, pattern>;
+  def noacc_noexch : t2VMLALDAV<iname, suffix, sz, U, 0b0, 0b0, pattern>;
+}
+
+defm VMLALDAVs16 : t2VMLALDAV_multi<"vmlaldav", "s16", 0, 0>;
+defm VMLALDAVs32 : t2VMLALDAV_multi<"vmlaldav", "s32", 1, 0>;
+defm VMLALDAVu16 : t2VMLALDAV_multi<"vmlaldav", "u16", 0, 1>;
+defm VMLALDAVu32 : t2VMLALDAV_multi<"vmlaldav", "u32", 1, 1>;
+
+// vmlalv aliases vmlaldav
+foreach acc = ["acc", "noacc"] in {
+  foreach suffix = ["s16", "s32", "u16", "u32"] in {
+    def : MVEInstAlias<!strconcat("vmlalv", !if(!eq(acc, "acc"), "a", ""),
+                       "${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
+                       (!cast<Instruction>(!strconcat("VMLALDAV", suffix, acc, "_noexch"))
+                       tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
+                       MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+  }
+}
+
+class t2VMLSLDAV<string iname, string suffix, bit A, bit X,
+                 bit sz, bit bit_28, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), (ins tGPREven:$RdaLoSrc,
+              tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm), NoItinerary, !strconcat(iname,
+              !if(!eq(A, 1), "a", ""), !if(!eq(X, 1), "x", "")), suffix,
+              "$RdaLoSrc, $RdaHiSrc, $Qn, $Qm",
+              "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc", pattern> {
+  bits<4> RdaLoDest;
+  bits<4> RdaHiDest;
+  bits<4> Qm;
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{22-20} = RdaHiDest{3-1};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaLoDest{3-1};
+  let Inst{12} = X;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+multiclass t2VMLSLDAwV_multi<string iname, string suffix, bit sz,
+                             bit bit_28, list<dag> pattern=[]> {
+  def acc_noexch   : t2VMLSLDAV<iname, suffix, 0b1, 0b0, sz, bit_28, pattern>;
+  def noacc_exch   : t2VMLSLDAV<iname, suffix, 0b0, 0b1, sz, bit_28, pattern>;
+  def acc_exch     : t2VMLSLDAV<iname, suffix, 0b1, 0b1, sz, bit_28, pattern>;
+  def noacc_noexch : t2VMLSLDAV<iname, suffix, 0b0, 0b0, sz, bit_28, pattern>;
+}
+
+defm t2VMLSLDAVs16   : t2VMLSLDAwV_multi<"vmlsldav", "s16", 0b0, 0b0>;
+defm t2VMLSLDAVs32   : t2VMLSLDAwV_multi<"vmlsldav", "s32", 0b1, 0b0>;
+defm t2VRMLSLDAVHs32 : t2VMLSLDAwV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
+
 // end of mve_rDest instructions
 
 // start of mve_comp instructions
 
 class MVE_comp<InstrItinClass itin, string iname, string suffix,
                string cstr, list<dag> pattern=[]>
   : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), itin, iname, suffix,
            "$Qd, $Qn, $Qm", vpred_r, cstr, pattern> {

llvm/test/MC/ARM/mve-reductions.s

+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
+# CHECK-NOFP: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
+vaddv.s16 lr, q0
+
+# ERROR: [[@LINE+1]]:11: {{error|note}}: invalid operand for instruction
+vaddv.s16 r1, q0
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vaddvt.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK-NOFP: vaddvt.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK: vaddve.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK-NOFP: vaddve.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+vpte.i8 eq, q0, q0
+vaddvt.s16 r0, q6
+vaddve.s16 r0, q6
+
+# CHECK: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOFP: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+vaddva.s16 lr, q0
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOFP: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOFP: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+vpte.i8 eq, q0, q0
+vaddvat.s16 lr, q0
+vaddvae.s16 lr, q0
+
+# CHECK: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
+# CHECK-NOFP: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
+vaddlv.s32 r0, r9, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vaddlv.s32 r0, r2, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vaddlv.s32 r1, r3, q2
+
+# CHECK: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
+# CHECK-NOFP: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
+vaddlv.u32 r0, r1, q1
+
+# CHECK: vminnmv.f16 lr, q3  @ encoding: [0xee,0xfe,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmv.f16 lr, q3  @ encoding: [0xee,0xfe,0x86,0xef]
+vminnmv.f16 lr, q3
+
+# CHECK: vminnmv.f32 lr, q1  @ encoding: [0xee,0xee,0x82,0xef]
+# CHECK-NOFP-NOT: vminnmv.f32 lr, q1  @ encoding: [0xee,0xee,0x82,0xef]
+vminnmv.f32 lr, q1
+
+# CHECK: vminnmav.f16 lr, q0  @ encoding: [0xec,0xfe,0x80,0xef]
+# CHECK-NOFP-NOT: vminnmav.f16 lr, q0  @ encoding: [0xec,0xfe,0x80,0xef]
+vminnmav.f16 lr, q0
+
+# CHECK: vminnmav.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmav.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+vminnmav.f32 lr, q3
+
+# CHECK: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
+# CHECK-NOFP: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
+vminv.s8 lr, q0
+
+# CHECK: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
+# CHECK-NOFP: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
+vminv.s16 lr, q0
+
+# CHECK: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
+# CHECK-NOFP: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
+vminv.s32 lr, q2
+
+# CHECK: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
+# CHECK-NOFP: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
+vminv.u8 r0, q0
+
+# CHECK: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
+# CHECK-NOFP: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
+vminv.u32 r10, q3
+
+# CHECK: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
+# CHECK-NOFP: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
+vminav.s16 r0, q0
+
+# CHECK: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
+# CHECK-NOFP: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
+vminav.s8 r0, q1
+
+# CHECK: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
+# CHECK-NOFP: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
+vminav.s32 lr, q1
+
+# CHECK: vmaxnmv.f16 lr, q1  @ encoding: [0xee,0xfe,0x02,0xef]
+# CHECK-NOFP-NOT: vmaxnmv.f16 lr, q1  @ encoding: [0xee,0xfe,0x02,0xef]
+vmaxnmv.f16 lr, q1
+
+# CHECK: vmaxnmv.f32 r10, q1  @ encoding: [0xee,0xee,0x02,0xaf]
+# CHECK-NOFP-NOT: vmaxnmv.f32 r10, q1  @ encoding: [0xee,0xee,0x02,0xaf]
+vmaxnmv.f32 r10, q1
+
+# CHECK: vmaxnmav.f16 r0, q6  @ encoding: [0xec,0xfe,0x0c,0x0f]
+# CHECK-NOFP-NOT: vmaxnmav.f16 r0, q6  @ encoding: [0xec,0xfe,0x0c,0x0f]
+vmaxnmav.f16 r0, q6
+
+# CHECK: vmaxnmav.f32 lr, q7  @ encoding: [0xec,0xee,0x0e,0xef]
+# CHECK-NOFP-NOT: vmaxnmav.f32 lr, q7  @ encoding: [0xec,0xee,0x0e,0xef]
+vmaxnmav.f32 lr, q7
+
+# CHECK: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
+# CHECK-NOFP: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
+vmaxv.s8 lr, q4
+
+# CHECK: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
+# CHECK-NOFP: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
+vmaxv.s16 lr, q0
+
+# CHECK: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
+# CHECK-NOFP: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
+vmaxv.s32 r1, q1
+
+# CHECK: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
+# CHECK-NOFP: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
+vmaxv.u8 r0, q4
+
+# CHECK: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
+# CHECK-NOFP: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
+vmaxv.u16 r0, q1
+
+# CHECK: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
+# CHECK-NOFP: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
+vmaxv.u32 r1, q0
+
+# CHECK: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
+# CHECK-NOFP: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
+vmaxav.s8 lr, q6
+
+# CHECK: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
+# CHECK-NOFP: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
+vmaxav.s16 r0, q6
+
+# CHECK: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
+# CHECK-NOFP: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
+vmaxav.s32 r10, q7
+
+# CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOFP: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+vmladav.s16 lr, q0, q7
+
+# CHECK: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
+# CHECK-NOFP: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
+vmladav.s32 lr, q0, q4
+
+# CHECK: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
+# CHECK-NOFP: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
+vmladav.u16 lr, q0, q7
+
+# CHECK: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
+# CHECK-NOFP: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
+vmladav.u32 lr, q0, q0
+
+# CHECK: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
+# CHECK-NOFP: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
+vmladava.s16 lr, q0, q4
+
+# CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
+# CHECK-NOFP: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
+vmladavx.s16 r0, q0, q7
+
+# CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
+# CHECK-NOFP: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
+vmladavax.s16 lr, q0, q7
+
+# CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
+# CHECK-NOFP: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
+vmladav.s8 lr, q3, q0
+
+# CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
+# CHECK-NOFP: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
+vmladav.u8 lr, q1, q7
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+vrmlaldavh.s32 lr, r1, q6, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlaldavh.u32 lr, r1, q5, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlaldavh.u32 lr, r1, q5, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavh.u32 r1, r3, q5, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavh.u32 r2, r4, q5, q2
+
+# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
+# CHECK-NOFP: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
+vrmlaldavhax.s32 lr, r1, q3, q0
+
+# CHECK: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
+# CHECK-NOFP: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
+vrmlsldavh.s32 lr, r11, q6, q5
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOFP: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+vmlsdav.s16 lr, q0, q3
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+vrmlalvh.s32 lr, r1, q6, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlalvh.u32 lr, r1, q5, q2
+
+# CHECK: vrmlalvha.s32 lr, r1, q3, q6  @ encoding: [0x86,0xee,0x2c,0xef]
+# CHECK-NOFP: vrmlalvha.s32 lr, r1, q3, q6  @ encoding: [0x86,0xee,0x2c,0xef]
+vrmlalvha.s32 lr, r1, q3, q6
+
+# CHECK: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
+# CHECK-NOFP: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
+vrmlalvha.u32 lr, r1, q7, q1
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOFP: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+vmlsdav.s16 lr, q0, q3
+
+# CHECK: vmlsdav.s32 lr, q2, q6  @ encoding: [0xf5,0xee,0x0d,0xee]
+# CHECK-NOFP: vmlsdav.s32 lr, q2, q6  @ encoding: [0xf5,0xee,0x0d,0xee]
+vmlsdav.s32 lr, q2, q6
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vmlsdavaxt.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK-NOFP: vmlsdavaxt.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK: vmlsdavaxe.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK-NOFP: vmlsdavaxe.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+vpte.i8 eq, q0, q0
+vmlsdavaxt.s16 lr, q1, q4
+vmlsdavaxe.s16 lr, q1, q4
+
+# CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOFP: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+vmlav.s16 lr, q0, q7
+
+# CHECK: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
+# CHECK-NOFP: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
+vmlaldav.s16 lr, r1, q4, q1
+
+# CHECK: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
+# CHECK-NOFP: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
+vmlaldav.s32 lr, r11, q4, q1
+
+# CHECK: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
+# CHECK-NOFP: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
+vmlalv.s32 r0, r1, q7, q6
+
+# CHECK: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
+# CHECK-NOFP: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
+vmlalv.u16 lr, r11, q5, q4
+
+# ----------------------------------------------------------------------
+# The following tests have to go last because of the NOFP-NOT checks inside the
+# VPT block.
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vminnmavt.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmavt.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK: vminnmave.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmave.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+vpte.i8 eq, q0, q0
+vminnmavt.f32 lr, q3
+vminnmave.f32 lr, q3

llvm/test/MC/Disassembler/ARM/mve-reductions.txt

+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf5,0xee,0x00,0xef]
+
+# CHECK: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf5,0xee,0x20,0xef]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xf5,0xee,0x20,0xef]
+[0xf5,0xee,0x20,0xef]
+
+# CHECK: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xc9,0xee,0x04,0x0f]
+
+# CHECK: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xfe,0x02,0x0f]
+
+# CHECK: vminnmv.f16 lr, q3  @ encoding: [0xee,0xfe,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xfe,0x86,0xef]
+
+# CHECK: vminnmv.f32 lr, q1  @ encoding: [0xee,0xee,0x82,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xee,0x82,0xef]
+
+# CHECK: vminnmav.f16 lr, q0  @ encoding: [0xec,0xfe,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xfe,0x80,0xef]
+
+# CHECK: vminnmav.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xee,0x86,0xef]
+
+# CHECK: vpte.i8 eq, q0, q0    @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vminnmavt.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vminnmave.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xec,0xee,0x86,0xef]
+[0xec,0xee,0x86,0xef]
+
+# CHECK: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xee,0x80,0xef]
+
+# CHECK: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xee,0x80,0xef]
+
+# CHECK: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xee,0x84,0xef]
+
+# CHECK: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xfe,0x80,0x0f]
+
+# CHECK: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xfe,0x86,0xaf]
+
+# CHECK: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe4,0xee,0x80,0x0f]
+
+# CHECK: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe0,0xee,0x82,0x0f]
+
+# CHECK: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe8,0xee,0x82,0xef]
+
+# CHECK: vmaxnmv.f16 lr, q1  @ encoding: [0xee,0xfe,0x02,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xfe,0x02,0xef]
+
+# CHECK: vmaxnmv.f32 r10, q1  @ encoding: [0xee,0xee,0x02,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xee,0x02,0xaf]
+
+# CHECK: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xee,0x08,0xef]
+
+# CHECK: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xee,0x00,0xef]
+
+# CHECK: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xee,0x02,0x1f]
+
+# CHECK: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xfe,0x08,0x0f]
+
+# CHECK: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xfe,0x02,0x0f]
+
+# CHECK: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xfe,0x00,0x1f]
+
+# CHECK: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe0,0xee,0x0c,0xef]
+
+# CHECK: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe4,0xee,0x0c,0x0f]
+
+# CHECK: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe8,0xee,0x0e,0xaf]
+
+# CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x0e,0xee]
+
+# CHECK: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf1,0xee,0x08,0xee]
+
+# CHECK: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xfe,0x0e,0xee]
+
+# CHECK: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf1,0xfe,0x00,0xee]
+
+# CHECK: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x28,0xee]
+
+# CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x0e,0x1e]
+
+# CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x2e,0xfe]
+
+# CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf6,0xee,0x00,0xef]
+
+# CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf2,0xfe,0x0e,0xef]
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xee,0x04,0xef]
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0x04,0xef]
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0x04,0xef]
+
+# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x86,0xee,0x20,0xff]
+
+# CHECK: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xdc,0xfe,0x0b,0xee]
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x07,0xee]
+
+# CHECK: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xfe,0x22,0xef]
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x07,0xee]
+
+# CHECK: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xee,0x02,0xee]
+
+# CHECK: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xd9,0xee,0x02,0xee]
+
+# CHECK: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0x0c,0x0e]
+
+# CHECK: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xda,0xfe,0x08,0xee]
+