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miyukimiyuki
committedJun 14, 2019
[ARM] Add MVE horizontal accumulation instructions
This is the family of vector instructions that combine all the lanes in their input vector(s), and output a value in one or two GPRs. Differential Revision: https://reviews.llvm.org/D62670 llvm-svn: 363403
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llvmorg-21-initllvmorg-9.0.0-rc1
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‎llvm/lib/Target/ARM/ARMInstrFormats.td

+2
Original file line numberDiff line numberDiff line change
@@ -366,6 +366,8 @@ class VFP3InstAlias<string Asm, dag Result, bit EmitPriority = 0>
366366
: InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
367367
class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
368368
: InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
369+
class MVEInstAlias<string Asm, dag Result, bit EmitPriority = 1>
370+
: InstAlias<Asm, Result, EmitPriority>, Requires<[HasMVEInt, IsThumb]>;
369371

370372

371373
class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,

‎llvm/lib/Target/ARM/ARMInstrMVE.td

+316
Original file line numberDiff line numberDiff line change
@@ -266,6 +266,322 @@ def VABAVu8 : t2VABAV<"u8", 0b1, 0b00>;
266266
def VABAVu16 : t2VABAV<"u16", 0b1, 0b01>;
267267
def VABAVu32 : t2VABAV<"u32", 0b1, 0b10>;
268268

269+
class t2VADDV<string iname, string suffix, dag iops, string cstr,
270+
bit A, bit U, bits<2> size, list<dag> pattern=[]>
271+
: MVE_rDest<(outs tGPREven:$Rda), iops, NoItinerary,
272+
iname, suffix, "$Rda, $Qm", cstr, pattern> {
273+
bits<3> Qm;
274+
bits<4> Rda;
275+
276+
let Inst{28} = U;
277+
let Inst{22-20} = 0b111;
278+
let Inst{19-18} = size{1-0};
279+
let Inst{17-16} = 0b01;
280+
let Inst{15-13} = Rda{3-1};
281+
let Inst{12} = 0b0;
282+
let Inst{8-6} = 0b100;
283+
let Inst{5} = A;
284+
let Inst{3-1} = Qm{2-0};
285+
let Inst{0} = 0b0;
286+
}
287+
288+
multiclass t2VADDV_A<string suffix, bit U, bits<2> size, list<dag> pattern=[]> {
289+
def acc : t2VADDV<"vaddva", suffix,
290+
(ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
291+
0b1, U, size, pattern>;
292+
def no_acc : t2VADDV<"vaddv", suffix,
293+
(ins MQPR:$Qm), "",
294+
0b0, U, size, pattern>;
295+
}
296+
297+
defm VADDVs8 : t2VADDV_A<"s8", 0b0, 0b00>;
298+
defm VADDVs16 : t2VADDV_A<"s16", 0b0, 0b01>;
299+
defm VADDVs32 : t2VADDV_A<"s32", 0b0, 0b10>;
300+
defm VADDVu8 : t2VADDV_A<"u8", 0b1, 0b00>;
301+
defm VADDVu16 : t2VADDV_A<"u16", 0b1, 0b01>;
302+
defm VADDVu32 : t2VADDV_A<"u32", 0b1, 0b10>;
303+
304+
class t2VADDLV<string iname, string suffix, dag iops, string cstr,
305+
bit A, bit U, list<dag> pattern=[]>
306+
: MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), iops, NoItinerary, iname,
307+
suffix, "$RdaLo, $RdaHi, $Qm", cstr, pattern> {
308+
bits<3> Qm;
309+
bits<4> RdaLo;
310+
bits<4> RdaHi;
311+
312+
let Inst{28} = U;
313+
let Inst{22-20} = RdaHi{3-1};
314+
let Inst{19-18} = 0b10;
315+
let Inst{17-16} = 0b01;
316+
let Inst{15-13} = RdaLo{3-1};
317+
let Inst{12} = 0b0;
318+
let Inst{8-6} = 0b100;
319+
let Inst{5} = A;
320+
let Inst{3-1} = Qm{2-0};
321+
let Inst{0} = 0b0;
322+
}
323+
324+
multiclass t2VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
325+
def acc : t2VADDLV<"vaddlva", suffix,
326+
(ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, MQPR:$Qm),
327+
"$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
328+
0b1, U, pattern>;
329+
def no_acc : t2VADDLV<"vaddlv", suffix,
330+
(ins MQPR:$Qm), "",
331+
0b0, U, pattern>;
332+
}
333+
334+
335+
defm VADDLVs32 : t2VADDLV_A<"s32", 0b0>;
336+
defm VADDLVu32 : t2VADDLV_A<"u32", 0b1>;
337+
338+
class t2VMINMAXNMV<string iname, string suffix, bit sz, bit bit_17, bit bit_7,
339+
list<dag> pattern=[]>
340+
: MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
341+
NoItinerary, iname, suffix, "$RdaSrc, $Qm",
342+
"$RdaDest = $RdaSrc", pattern> {
343+
bits<3> Qm;
344+
bits<4> RdaDest;
345+
346+
let Inst{28} = sz;
347+
let Inst{22-20} = 0b110;
348+
let Inst{19-18} = 0b11;
349+
let Inst{17} = bit_17;
350+
let Inst{16} = 0b0;
351+
let Inst{15-12} = RdaDest{3-0};
352+
let Inst{8} = 0b1;
353+
let Inst{7} = bit_7;
354+
let Inst{6-5} = 0b00;
355+
let Inst{3-1} = Qm{2-0};
356+
let Inst{0} = 0b0;
357+
358+
let Predicates = [HasMVEFloat];
359+
}
360+
361+
multiclass t2VMINMAXNMV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
362+
def f32 : t2VMINMAXNMV<iname, "f32", 0b0, 0b1, bit_7, pattern>;
363+
def f16 : t2VMINMAXNMV<iname, "f16", 0b1, 0b1, bit_7, pattern>;
364+
}
365+
366+
defm VMINNMV : t2VMINMAXNMV_fty<"vminnmv", 0b1>;
367+
defm VMAXNMV : t2VMINMAXNMV_fty<"vmaxnmv", 0b0>;
368+
369+
multiclass t2VMINMAXNMAV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
370+
def f32 : t2VMINMAXNMV<iname, "f32", 0b0, 0b0, bit_7, pattern>;
371+
def f16 : t2VMINMAXNMV<iname, "f16", 0b1, 0b0, bit_7, pattern>;
372+
}
373+
374+
defm VMINNMAV : t2VMINMAXNMAV_fty<"vminnmav", 0b1>;
375+
defm VMAXNMAV : t2VMINMAXNMAV_fty<"vmaxnmav", 0b0>;
376+
377+
class t2VMINMAXV<string iname, string suffix, bit U, bits<2> size,
378+
bit bit_17, bit bit_7, list<dag> pattern=[]>
379+
: MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm), NoItinerary,
380+
iname, suffix, "$RdaSrc, $Qm", "$RdaDest = $RdaSrc", pattern> {
381+
bits<3> Qm;
382+
bits<4> RdaDest;
383+
384+
let Inst{28} = U;
385+
let Inst{22-20} = 0b110;
386+
let Inst{19-18} = size{1-0};
387+
let Inst{17} = bit_17;
388+
let Inst{16} = 0b0;
389+
let Inst{15-12} = RdaDest{3-0};
390+
let Inst{8} = 0b1;
391+
let Inst{7} = bit_7;
392+
let Inst{6-5} = 0b00;
393+
let Inst{3-1} = Qm{2-0};
394+
let Inst{0} = 0b0;
395+
}
396+
397+
multiclass t2VMINMAXV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
398+
def s8 : t2VMINMAXV<iname, "s8", 0b0, 0b00, 0b1, bit_7>;
399+
def s16 : t2VMINMAXV<iname, "s16", 0b0, 0b01, 0b1, bit_7>;
400+
def s32 : t2VMINMAXV<iname, "s32", 0b0, 0b10, 0b1, bit_7>;
401+
def u8 : t2VMINMAXV<iname, "u8", 0b1, 0b00, 0b1, bit_7>;
402+
def u16 : t2VMINMAXV<iname, "u16", 0b1, 0b01, 0b1, bit_7>;
403+
def u32 : t2VMINMAXV<iname, "u32", 0b1, 0b10, 0b1, bit_7>;
404+
}
405+
406+
// Prefixed with MVE to prevent conflict with A57 scheduler.
407+
defm MVE_VMINV : t2VMINMAXV_ty<"vminv", 0b1>;
408+
defm MVE_VMAXV : t2VMINMAXV_ty<"vmaxv", 0b0>;
409+
410+
multiclass t2VMINMAXAV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
411+
def s8 : t2VMINMAXV<iname, "s8", 0b0, 0b00, 0b0, bit_7>;
412+
def s16 : t2VMINMAXV<iname, "s16", 0b0, 0b01, 0b0, bit_7>;
413+
def s32 : t2VMINMAXV<iname, "s32", 0b0, 0b10, 0b0, bit_7>;
414+
}
415+
416+
defm MVE_VMINAV : t2VMINMAXAV_ty<"vminav", 0b1>;
417+
defm MVE_VMAXAV : t2VMINMAXAV_ty<"vmaxav", 0b0>;
418+
419+
class t2VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
420+
bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
421+
list<dag> pattern=[]>
422+
: MVE_rDest<(outs tGPREven:$RdaDest), iops, NoItinerary, iname, suffix,
423+
"$RdaDest, $Qn, $Qm", cstr, pattern> {
424+
bits<4> RdaDest;
425+
bits<3> Qm;
426+
bits<3> Qn;
427+
428+
let Inst{28} = bit_28;
429+
let Inst{22-20} = 0b111;
430+
let Inst{19-17} = Qn{2-0};
431+
let Inst{16} = sz;
432+
let Inst{15-13} = RdaDest{3-1};
433+
let Inst{12} = X;
434+
let Inst{8} = bit_8;
435+
let Inst{7-6} = 0b00;
436+
let Inst{5} = A;
437+
let Inst{3-1} = Qm{2-0};
438+
let Inst{0} = bit_0;
439+
}
440+
441+
multiclass t2VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
442+
bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
443+
list<dag> pattern=[]> {
444+
def _noexch : t2VMLAMLSDAV<iname, suffix, iops, cstr, sz,
445+
bit_28, A, 0b0, bit_8, bit_0, pattern>;
446+
def _exch : t2VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
447+
bit_28, A, 0b1, bit_8, bit_0, pattern>;
448+
}
449+
450+
multiclass t2VMLAMLSDAV_XA<string iname, string suffix, bit sz, bit bit_28,
451+
bit bit_8, bit bit_0, list<dag> pattern=[]> {
452+
defm _noacc : t2VMLAMLSDAV_X<iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
453+
sz, bit_28, 0b0, bit_8, bit_0, pattern>;
454+
defm _acc : t2VMLAMLSDAV_X<iname # "a", suffix,
455+
(ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
456+
"$RdaDest = $RdaSrc",
457+
sz, bit_28, 0b1, bit_8, bit_0, pattern>;
458+
}
459+
460+
multiclass t2VMLADAV_multi<string suffix, bit sz, bit U, bit bit_8,
461+
list<dag> pattern=[]> {
462+
defm "" : t2VMLAMLSDAV_XA<"vmladav", suffix, sz, U, bit_8, 0b0, pattern>;
463+
}
464+
465+
defm VMLADAVs16 : t2VMLADAV_multi<"s16", 0b0, 0b0, 0b0>;
466+
defm VMLADAVs32 : t2VMLADAV_multi<"s32", 0b1, 0b0, 0b0>;
467+
defm VMLADAVu16 : t2VMLADAV_multi<"u16", 0b0, 0b1, 0b0>;
468+
defm VMLADAVu32 : t2VMLADAV_multi<"u32", 0b1, 0b1, 0b0>;
469+
470+
defm VMLADAVs8 : t2VMLADAV_multi<"s8", 0b0, 0b0, 0b1>;
471+
defm VMLADAVu8 : t2VMLADAV_multi<"u8", 0b0, 0b1, 0b1>;
472+
473+
// vmlav aliases vmladav
474+
foreach acc = ["_acc", "_noacc"] in {
475+
foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
476+
def : MVEInstAlias<!strconcat("vmlav", !if(!eq(acc, "_acc"), "a", ""),
477+
"${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
478+
(!cast<Instruction>(!strconcat("VMLADAV", suffix, acc, "_noexch")) tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
479+
}
480+
}
481+
482+
multiclass t2VMLSDAV_multi<string suffix, bit sz, bit bit_28,
483+
list<dag> pattern=[]> {
484+
defm "" : t2VMLAMLSDAV_XA<"vmlsdav", suffix, sz, bit_28, 0b0, 0b1, pattern>;
485+
}
486+
487+
defm t2VMLSDAVs8 : t2VMLSDAV_multi<"s8", 0, 0b1>;
488+
defm t2VMLSDAVs16 : t2VMLSDAV_multi<"s16", 0, 0b0>;
489+
defm t2VMLSDAVs32 : t2VMLSDAV_multi<"s32", 1, 0b0>;
490+
491+
// Base class for VMLALDAV and VMLSLDAV, VRMLALDAVH, VRMLSLDAVH
492+
class t2VMLALDAVBase<string iname, string suffix, dag iops, string cstr, bit sz,
493+
bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
494+
list<dag> pattern=[]>
495+
: MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), iops, NoItinerary,
496+
iname, suffix, "$RdaLoDest, $RdaHiDest, $Qn, $Qm", cstr, pattern> {
497+
bits<4> RdaLoDest;
498+
bits<4> RdaHiDest;
499+
bits<3> Qm;
500+
bits<3> Qn;
501+
502+
let Inst{28} = bit_28;
503+
let Inst{22-20} = RdaHiDest{3-1};
504+
let Inst{19-17} = Qn{2-0};
505+
let Inst{16} = sz;
506+
let Inst{15-13} = RdaLoDest{3-1};
507+
let Inst{12} = X;
508+
let Inst{8} = bit_8;
509+
let Inst{7-6} = 0b00;
510+
let Inst{5} = A;
511+
let Inst{3-1} = Qm{2-0};
512+
let Inst{0} = bit_0;
513+
}
514+
515+
multiclass t2VMLALDAVBase_X<string iname, string suffix, dag iops, string cstr,
516+
bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
517+
list<dag> pattern=[]> {
518+
def _noexch : t2VMLALDAVBase<iname, suffix, iops, cstr, sz,
519+
bit_28, A, 0b0, bit_8, bit_0, pattern>;
520+
def _exch : t2VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,
521+
bit_28, A, 0b1, bit_8, bit_0, pattern>;
522+
}
523+
524+
multiclass t2VMLALDAVBase_XA<string iname, string suffix, bit sz, bit bit_28,
525+
bit bit_8, bit bit_0, list<dag> pattern=[]> {
526+
defm _noacc : t2VMLALDAVBase_X<iname, suffix,
527+
(ins MQPR:$Qn, MQPR:$Qm), "",
528+
sz, bit_28, 0b0, bit_8, bit_0, pattern>;
529+
defm _acc : t2VMLALDAVBase_X<iname # "a", suffix,
530+
(ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm),
531+
"$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
532+
sz, bit_28, 0b1, bit_8, bit_0, pattern>;
533+
}
534+
535+
multiclass t2VRMLALDAVH_multi<string suffix, bit U, list<dag> pattern=[]> {
536+
defm "" : t2VMLALDAVBase_XA<"vrmlaldavh", suffix, 0b0, U, 0b1, 0b0, pattern>;
537+
}
538+
539+
defm t2VRMLALDAVHs32 : t2VRMLALDAVH_multi<"s32", 0>;
540+
defm t2VRMLALDAVHu32 : t2VRMLALDAVH_multi<"u32", 1>;
541+
542+
// vrmlalvh aliases for vrmlaldavh
543+
def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
544+
(t2VRMLALDAVHs32_noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
545+
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
546+
def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
547+
(t2VRMLALDAVHs32_acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
548+
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
549+
def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
550+
(t2VRMLALDAVHu32_noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
551+
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
552+
def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
553+
(t2VRMLALDAVHu32_acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
554+
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
555+
556+
multiclass t2VMLALDAV_multi<string suffix, bit sz, bit U, list<dag> pattern=[]> {
557+
defm "" : t2VMLALDAVBase_XA<"vmlaldav", suffix, sz, U, 0b0, 0b0, pattern>;
558+
}
559+
560+
defm VMLALDAVs16 : t2VMLALDAV_multi<"s16", 0b0, 0b0>;
561+
defm VMLALDAVs32 : t2VMLALDAV_multi<"s32", 0b1, 0b0>;
562+
defm VMLALDAVu16 : t2VMLALDAV_multi<"u16", 0b0, 0b1>;
563+
defm VMLALDAVu32 : t2VMLALDAV_multi<"u32", 0b1, 0b1>;
564+
565+
// vmlalv aliases vmlaldav
566+
foreach acc = ["_acc", "_noacc"] in {
567+
foreach suffix = ["s16", "s32", "u16", "u32"] in {
568+
def : MVEInstAlias<!strconcat("vmlalv", !if(!eq(acc, "_acc"), "a", ""),
569+
"${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
570+
(!cast<Instruction>(!strconcat("VMLALDAV", suffix, acc, "_noexch"))
571+
tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
572+
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
573+
}
574+
}
575+
576+
multiclass t2VMLSLDAV_multi<string iname, string suffix, bit sz,
577+
bit bit_28, list<dag> pattern=[]> {
578+
defm "" : t2VMLALDAVBase_XA<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
579+
}
580+
581+
defm t2VMLSLDAVs16 : t2VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
582+
defm t2VMLSLDAVs32 : t2VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
583+
defm t2VRMLSLDAVHs32 : t2VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
584+
269585
// end of mve_rDest instructions
270586

271587
// start of mve_comp instructions

‎llvm/test/MC/ARM/mve-reductions-fp.s

+58
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
2+
# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
3+
# RUN: FileCheck --check-prefix=ERROR-NOFP < %t %s
4+
# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s \
5+
# RUN: | FileCheck --check-prefix=CHECK %s
6+
7+
# CHECK: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
8+
# CHECK-NOFP-NOT: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
9+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
10+
vminnmv.f16 lr, q3
11+
12+
# CHECK: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
13+
# CHECK-NOFP-NOT: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
14+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
15+
vminnmv.f32 lr, q1
16+
17+
# CHECK: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
18+
# CHECK-NOFP-NOT: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
19+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
20+
vminnmav.f16 lr, q0
21+
22+
# CHECK: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
23+
# CHECK-NOFP-NOT: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
24+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
25+
vminnmav.f32 lr, q3
26+
27+
# CHECK: vmaxnmv.f16 lr, q1 @ encoding: [0xee,0xfe,0x02,0xef]
28+
# CHECK-NOFP-NOT: vmaxnmv.f16 lr, q1 @ encoding: [0xee,0xfe,0x02,0xef]
29+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
30+
vmaxnmv.f16 lr, q1
31+
32+
# CHECK: vmaxnmv.f32 r10, q1 @ encoding: [0xee,0xee,0x02,0xaf]
33+
# CHECK-NOFP-NOT: vmaxnmv.f32 r10, q1 @ encoding: [0xee,0xee,0x02,0xaf]
34+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
35+
vmaxnmv.f32 r10, q1
36+
37+
# CHECK: vmaxnmav.f16 r0, q6 @ encoding: [0xec,0xfe,0x0c,0x0f]
38+
# CHECK-NOFP-NOT: vmaxnmav.f16 r0, q6 @ encoding: [0xec,0xfe,0x0c,0x0f]
39+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
40+
vmaxnmav.f16 r0, q6
41+
42+
# CHECK: vmaxnmav.f32 lr, q7 @ encoding: [0xec,0xee,0x0e,0xef]
43+
# CHECK-NOFP-NOT: vmaxnmav.f32 lr, q7 @ encoding: [0xec,0xee,0x0e,0xef]
44+
# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
45+
vmaxnmav.f32 lr, q7
46+
47+
# ----------------------------------------------------------------------
48+
# The following tests have to go last because of the NOFP-NOT checks inside the
49+
# VPT block.
50+
51+
# CHECK: vpte.i8 eq, q0, q0
52+
# CHECK: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
53+
# CHECK-NOFP-NOT: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
54+
# CHECK: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
55+
# CHECK-NOFP-NOT: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
56+
vpte.i8 eq, q0, q0
57+
vminnmavt.f32 lr, q3
58+
vminnmave.f32 lr, q3

‎llvm/test/MC/ARM/mve-reductions.s

+182-9
Original file line numberDiff line numberDiff line change
@@ -1,28 +1,201 @@
1-
# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
2-
# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
3-
# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s \
1+
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
42
# RUN: | FileCheck --check-prefix=CHECK %s
3+
# RUN: FileCheck --check-prefix=ERROR < %t %s
4+
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
5+
# RUN: | FileCheck --check-prefix=CHECK %s
6+
# RUN: FileCheck --check-prefix=ERROR < %t %s
57

68
# CHECK: vabav.s8 r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
7-
# CHECK-NOFP: vabav.s8 r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
89
vabav.s8 r0, q1, q3
910

1011
# CHECK: vabav.s16 r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
11-
# CHECK-NOFP: vabav.s16 r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
1212
vabav.s16 r0, q1, q3
1313

1414
# CHECK: vabav.s32 r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
15-
# CHECK-NOFP: vabav.s32 r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
1615
vabav.s32 r0, q1, q3
1716

1817
# CHECK: vabav.u8 r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
19-
# CHECK-NOFP: vabav.u8 r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
2018
vabav.u8 r0, q1, q3
2119

2220
# CHECK: vabav.u16 r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
23-
# CHECK-NOFP: vabav.u16 r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
2421
vabav.u16 r0, q1, q3
2522

2623
# CHECK: vabav.u32 r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
27-
# CHECK-NOFP: vabav.u32 r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
2824
vabav.u32 r0, q1, q3
25+
26+
# CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]
27+
vaddv.s16 lr, q0
28+
29+
# ERROR: [[@LINE+1]]:11: {{error|note}}: invalid operand for instruction
30+
vaddv.s16 r1, q0
31+
32+
# CHECK: vpte.i8 eq, q0, q0
33+
# CHECK: vaddvt.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]
34+
# CHECK: vaddve.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]
35+
vpte.i8 eq, q0, q0
36+
vaddvt.s16 r0, q6
37+
vaddve.s16 r0, q6
38+
39+
# CHECK: vaddva.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
40+
vaddva.s16 lr, q0
41+
42+
# CHECK: vpte.i8 eq, q0, q0
43+
# CHECK: vaddvat.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
44+
# CHECK: vaddvae.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
45+
vpte.i8 eq, q0, q0
46+
vaddvat.s16 lr, q0
47+
vaddvae.s16 lr, q0
48+
49+
# CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]
50+
vaddlv.s32 r0, r9, q2
51+
52+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
53+
vaddlv.s32 r0, r2, q2
54+
55+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
56+
vaddlv.s32 r1, r3, q2
57+
58+
# CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]
59+
vaddlv.u32 r0, r1, q1
60+
61+
# CHECK: vminv.s8 lr, q0 @ encoding: [0xe2,0xee,0x80,0xef]
62+
vminv.s8 lr, q0
63+
64+
# CHECK: vminv.s16 lr, q0 @ encoding: [0xe6,0xee,0x80,0xef]
65+
vminv.s16 lr, q0
66+
67+
# CHECK: vminv.s32 lr, q2 @ encoding: [0xea,0xee,0x84,0xef]
68+
vminv.s32 lr, q2
69+
70+
# CHECK: vminv.u8 r0, q0 @ encoding: [0xe2,0xfe,0x80,0x0f]
71+
vminv.u8 r0, q0
72+
73+
# CHECK: vminv.u32 r10, q3 @ encoding: [0xea,0xfe,0x86,0xaf]
74+
vminv.u32 r10, q3
75+
76+
# CHECK: vminav.s16 r0, q0 @ encoding: [0xe4,0xee,0x80,0x0f]
77+
vminav.s16 r0, q0
78+
79+
# CHECK: vminav.s8 r0, q1 @ encoding: [0xe0,0xee,0x82,0x0f]
80+
vminav.s8 r0, q1
81+
82+
# CHECK: vminav.s32 lr, q1 @ encoding: [0xe8,0xee,0x82,0xef]
83+
vminav.s32 lr, q1
84+
85+
# CHECK: vmaxv.s8 lr, q4 @ encoding: [0xe2,0xee,0x08,0xef]
86+
vmaxv.s8 lr, q4
87+
88+
# CHECK: vmaxv.s16 lr, q0 @ encoding: [0xe6,0xee,0x00,0xef]
89+
vmaxv.s16 lr, q0
90+
91+
# CHECK: vmaxv.s32 r1, q1 @ encoding: [0xea,0xee,0x02,0x1f]
92+
vmaxv.s32 r1, q1
93+
94+
# CHECK: vmaxv.u8 r0, q4 @ encoding: [0xe2,0xfe,0x08,0x0f]
95+
vmaxv.u8 r0, q4
96+
97+
# CHECK: vmaxv.u16 r0, q1 @ encoding: [0xe6,0xfe,0x02,0x0f]
98+
vmaxv.u16 r0, q1
99+
100+
# CHECK: vmaxv.u32 r1, q0 @ encoding: [0xea,0xfe,0x00,0x1f]
101+
vmaxv.u32 r1, q0
102+
103+
# CHECK: vmaxav.s8 lr, q6 @ encoding: [0xe0,0xee,0x0c,0xef]
104+
vmaxav.s8 lr, q6
105+
106+
# CHECK: vmaxav.s16 r0, q6 @ encoding: [0xe4,0xee,0x0c,0x0f]
107+
vmaxav.s16 r0, q6
108+
109+
# CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]
110+
vmaxav.s32 r10, q7
111+
112+
# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
113+
vmladav.s16 lr, q0, q7
114+
115+
# CHECK: vmlav.s32 lr, q0, q4 @ encoding: [0xf1,0xee,0x08,0xee]
116+
vmladav.s32 lr, q0, q4
117+
118+
# CHECK: vmlav.u16 lr, q0, q7 @ encoding: [0xf0,0xfe,0x0e,0xee]
119+
vmladav.u16 lr, q0, q7
120+
121+
# CHECK: vmlav.u32 lr, q0, q0 @ encoding: [0xf1,0xfe,0x00,0xee]
122+
vmladav.u32 lr, q0, q0
123+
124+
# CHECK: vmlava.s16 lr, q0, q4 @ encoding: [0xf0,0xee,0x28,0xee]
125+
vmladava.s16 lr, q0, q4
126+
127+
# CHECK: vmladavx.s16 r0, q0, q7 @ encoding: [0xf0,0xee,0x0e,0x1e]
128+
vmladavx.s16 r0, q0, q7
129+
130+
# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
131+
vmladavax.s16 lr, q0, q7
132+
133+
# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
134+
vmladav.s8 lr, q3, q0
135+
136+
# CHECK: vmlav.u8 lr, q1, q7 @ encoding: [0xf2,0xfe,0x0e,0xef]
137+
vmladav.u8 lr, q1, q7
138+
139+
# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
140+
vrmlaldavh.s32 lr, r1, q6, q2
141+
142+
# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
143+
vrmlaldavh.u32 lr, r1, q5, q2
144+
145+
# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
146+
vrmlaldavh.u32 lr, r1, q5, q2
147+
148+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
149+
vrmlaldavh.u32 r1, r3, q5, q2
150+
151+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
152+
vrmlaldavh.u32 r2, r4, q5, q2
153+
154+
# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]
155+
vrmlaldavhax.s32 lr, r1, q3, q0
156+
157+
# CHECK: vrmlsldavh.s32 lr, r11, q6, q5 @ encoding: [0xdc,0xfe,0x0b,0xee]
158+
vrmlsldavh.s32 lr, r11, q6, q5
159+
160+
# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
161+
vmlsdav.s16 lr, q0, q3
162+
163+
# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
164+
vrmlalvh.s32 lr, r1, q6, q2
165+
166+
# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
167+
vrmlalvh.u32 lr, r1, q5, q2
168+
169+
# CHECK: vrmlalvha.s32 lr, r1, q3, q6 @ encoding: [0x86,0xee,0x2c,0xef]
170+
vrmlalvha.s32 lr, r1, q3, q6
171+
172+
# CHECK: vrmlalvha.u32 lr, r1, q7, q1 @ encoding: [0x8e,0xfe,0x22,0xef]
173+
vrmlalvha.u32 lr, r1, q7, q1
174+
175+
# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
176+
vmlsdav.s16 lr, q0, q3
177+
178+
# CHECK: vmlsdav.s32 lr, q2, q6 @ encoding: [0xf5,0xee,0x0d,0xee]
179+
vmlsdav.s32 lr, q2, q6
180+
181+
# CHECK: vpte.i8 eq, q0, q0
182+
# CHECK: vmlsdavaxt.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]
183+
# CHECK: vmlsdavaxe.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]
184+
vpte.i8 eq, q0, q0
185+
vmlsdavaxt.s16 lr, q1, q4
186+
vmlsdavaxe.s16 lr, q1, q4
187+
188+
# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
189+
vmlav.s16 lr, q0, q7
190+
191+
# CHECK: vmlalv.s16 lr, r1, q4, q1 @ encoding: [0x88,0xee,0x02,0xee]
192+
vmlaldav.s16 lr, r1, q4, q1
193+
194+
# CHECK: vmlalv.s32 lr, r11, q4, q1 @ encoding: [0xd9,0xee,0x02,0xee]
195+
vmlaldav.s32 lr, r11, q4, q1
196+
197+
# CHECK: vmlalv.s32 r0, r1, q7, q6 @ encoding: [0x8f,0xee,0x0c,0x0e]
198+
vmlalv.s32 r0, r1, q7, q6
199+
200+
# CHECK: vmlalv.u16 lr, r11, q5, q4 @ encoding: [0xda,0xfe,0x08,0xee]
201+
vmlalv.u16 lr, r11, q5, q4

‎llvm/test/MC/Disassembler/ARM/mve-reductions.txt

+212
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,215 @@
2525
[0xa2 0xfe 0x07 0x0f]
2626
# CHECK: vabav.u32 r0, q1, q3
2727
# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
28+
29+
# CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]
30+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
31+
[0xf5,0xee,0x00,0xef]
32+
33+
# CHECK: vaddva.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
34+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
35+
[0xf5,0xee,0x20,0xef]
36+
37+
# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
38+
# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
39+
# CHECK: vaddvat.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
40+
# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
41+
# CHECK: vaddvae.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
42+
# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
43+
[0x41,0xfe,0x00,0x8f]
44+
[0xf5,0xee,0x20,0xef]
45+
[0xf5,0xee,0x20,0xef]
46+
47+
# CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]
48+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
49+
[0xc9,0xee,0x04,0x0f]
50+
51+
# CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]
52+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
53+
[0x89,0xfe,0x02,0x0f]
54+
55+
# CHECK: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
56+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
57+
[0xee,0xfe,0x86,0xef]
58+
59+
# CHECK: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
60+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
61+
[0xee,0xee,0x82,0xef]
62+
63+
# CHECK: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
64+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
65+
[0xec,0xfe,0x80,0xef]
66+
67+
# CHECK: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
68+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
69+
[0xec,0xee,0x86,0xef]
70+
71+
# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
72+
# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
73+
# CHECK: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
74+
# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
75+
# CHECK: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
76+
# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
77+
[0x41,0xfe,0x00,0x8f]
78+
[0xec,0xee,0x86,0xef]
79+
[0xec,0xee,0x86,0xef]
80+
81+
# CHECK: vminv.s8 lr, q0 @ encoding: [0xe2,0xee,0x80,0xef]
82+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
83+
[0xe2,0xee,0x80,0xef]
84+
85+
# CHECK: vminv.s16 lr, q0 @ encoding: [0xe6,0xee,0x80,0xef]
86+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
87+
[0xe6,0xee,0x80,0xef]
88+
89+
# CHECK: vminv.s32 lr, q2 @ encoding: [0xea,0xee,0x84,0xef]
90+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
91+
[0xea,0xee,0x84,0xef]
92+
93+
# CHECK: vminv.u8 r0, q0 @ encoding: [0xe2,0xfe,0x80,0x0f]
94+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
95+
[0xe2,0xfe,0x80,0x0f]
96+
97+
# CHECK: vminv.u32 r10, q3 @ encoding: [0xea,0xfe,0x86,0xaf]
98+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
99+
[0xea,0xfe,0x86,0xaf]
100+
101+
# CHECK: vminav.s16 r0, q0 @ encoding: [0xe4,0xee,0x80,0x0f]
102+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
103+
[0xe4,0xee,0x80,0x0f]
104+
105+
# CHECK: vminav.s8 r0, q1 @ encoding: [0xe0,0xee,0x82,0x0f]
106+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
107+
[0xe0,0xee,0x82,0x0f]
108+
109+
# CHECK: vminav.s32 lr, q1 @ encoding: [0xe8,0xee,0x82,0xef]
110+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
111+
[0xe8,0xee,0x82,0xef]
112+
113+
# CHECK: vmaxnmv.f16 lr, q1 @ encoding: [0xee,0xfe,0x02,0xef]
114+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
115+
[0xee,0xfe,0x02,0xef]
116+
117+
# CHECK: vmaxnmv.f32 r10, q1 @ encoding: [0xee,0xee,0x02,0xaf]
118+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
119+
[0xee,0xee,0x02,0xaf]
120+
121+
# CHECK: vmaxv.s8 lr, q4 @ encoding: [0xe2,0xee,0x08,0xef]
122+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
123+
[0xe2,0xee,0x08,0xef]
124+
125+
# CHECK: vmaxv.s16 lr, q0 @ encoding: [0xe6,0xee,0x00,0xef]
126+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
127+
[0xe6,0xee,0x00,0xef]
128+
129+
# CHECK: vmaxv.s32 r1, q1 @ encoding: [0xea,0xee,0x02,0x1f]
130+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
131+
[0xea,0xee,0x02,0x1f]
132+
133+
# CHECK: vmaxv.u8 r0, q4 @ encoding: [0xe2,0xfe,0x08,0x0f]
134+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
135+
[0xe2,0xfe,0x08,0x0f]
136+
137+
# CHECK: vmaxv.u16 r0, q1 @ encoding: [0xe6,0xfe,0x02,0x0f]
138+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
139+
[0xe6,0xfe,0x02,0x0f]
140+
141+
# CHECK: vmaxv.u32 r1, q0 @ encoding: [0xea,0xfe,0x00,0x1f]
142+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
143+
[0xea,0xfe,0x00,0x1f]
144+
145+
# CHECK: vmaxav.s8 lr, q6 @ encoding: [0xe0,0xee,0x0c,0xef]
146+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
147+
[0xe0,0xee,0x0c,0xef]
148+
149+
# CHECK: vmaxav.s16 r0, q6 @ encoding: [0xe4,0xee,0x0c,0x0f]
150+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
151+
[0xe4,0xee,0x0c,0x0f]
152+
153+
# CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]
154+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
155+
[0xe8,0xee,0x0e,0xaf]
156+
157+
# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
158+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
159+
[0xf0,0xee,0x0e,0xee]
160+
161+
# CHECK: vmlav.s32 lr, q0, q4 @ encoding: [0xf1,0xee,0x08,0xee]
162+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
163+
[0xf1,0xee,0x08,0xee]
164+
165+
# CHECK: vmlav.u16 lr, q0, q7 @ encoding: [0xf0,0xfe,0x0e,0xee]
166+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
167+
[0xf0,0xfe,0x0e,0xee]
168+
169+
# CHECK: vmlav.u32 lr, q0, q0 @ encoding: [0xf1,0xfe,0x00,0xee]
170+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
171+
[0xf1,0xfe,0x00,0xee]
172+
173+
# CHECK: vmlava.s16 lr, q0, q4 @ encoding: [0xf0,0xee,0x28,0xee]
174+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
175+
[0xf0,0xee,0x28,0xee]
176+
177+
# CHECK: vmladavx.s16 r0, q0, q7 @ encoding: [0xf0,0xee,0x0e,0x1e]
178+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
179+
[0xf0,0xee,0x0e,0x1e]
180+
181+
# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
182+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
183+
[0xf0,0xee,0x2e,0xfe]
184+
185+
# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
186+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
187+
[0xf6,0xee,0x00,0xef]
188+
189+
# CHECK: vmlav.u8 lr, q1, q7 @ encoding: [0xf2,0xfe,0x0e,0xef]
190+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
191+
[0xf2,0xfe,0x0e,0xef]
192+
193+
# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
194+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
195+
[0x8c,0xee,0x04,0xef]
196+
197+
# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
198+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
199+
[0x8a,0xfe,0x04,0xef]
200+
201+
# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
202+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
203+
[0x8a,0xfe,0x04,0xef]
204+
205+
# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]
206+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
207+
[0x86,0xee,0x20,0xff]
208+
209+
# CHECK: vrmlsldavh.s32 lr, r11, q6, q5 @ encoding: [0xdc,0xfe,0x0b,0xee]
210+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
211+
[0xdc,0xfe,0x0b,0xee]
212+
213+
# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
214+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
215+
[0xf0,0xee,0x07,0xee]
216+
217+
# CHECK: vrmlalvha.u32 lr, r1, q7, q1 @ encoding: [0x8e,0xfe,0x22,0xef]
218+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
219+
[0x8e,0xfe,0x22,0xef]
220+
221+
# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
222+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
223+
[0xf0,0xee,0x07,0xee]
224+
225+
# CHECK: vmlalv.s16 lr, r1, q4, q1 @ encoding: [0x88,0xee,0x02,0xee]
226+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
227+
[0x88,0xee,0x02,0xee]
228+
229+
# CHECK: vmlalv.s32 lr, r11, q4, q1 @ encoding: [0xd9,0xee,0x02,0xee]
230+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
231+
[0xd9,0xee,0x02,0xee]
232+
233+
# CHECK: vmlalv.s32 r0, r1, q7, q6 @ encoding: [0x8f,0xee,0x0c,0x0e]
234+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
235+
[0x8f,0xee,0x0c,0x0e]
236+
237+
# CHECK: vmlalv.u16 lr, r11, q5, q4 @ encoding: [0xda,0xfe,0x08,0xee]
238+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
239+
[0xda,0xfe,0x08,0xee]

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