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Differential D154258

[RISCV] Refactor vfcvt_rm pseudo insertion case statements. NFC
ClosedPublic

Authored by luke on Jun 30 2023, 1:56 PM.

Details

Reviewers
fakepaper56
craig.topper
reames
frasercrmck
Commits
rG49899cd4cecd: [RISCV] Refactor vfcvt_rm pseudo insertion case statements. NFC

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Event Timeline

luke created this revision.Jun 30 2023, 1:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 30 2023, 1:56 PM
Herald added subscribers: jobnoorman, asb, pmatos and 27 others. · View Herald Transcript
luke requested review of this revision.Jun 30 2023, 1:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 30 2023, 1:56 PM
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay. · View Herald Transcript
luke updated this revision to Diff 536434.Jun 30 2023, 2:35 PM

Add another macro, to prepare for a future patch that adds a non-mask
variant of PseudoVFCVT

luke added a child revision: D154266: [RISCV] Add VFCVT pseudos with no mask.Jun 30 2023, 2:53 PM
Harbormaster completed remote builds in B242563: Diff 536434.Jun 30 2023, 4:24 PM
asb added a comment.Jul 3 2023, 3:35 AM

Soft LGTM as this should get a LGTM from someone working more on the vector side. But the change seems mechanically correct, and I get the motivation. I'm not the biggest fan in general of #define to remove repetitive code but I think it pays off here.

craig.topper accepted this revision.Jul 3 2023, 9:55 AM

LGTM

This revision is now accepted and ready to land.Jul 3 2023, 9:55 AM
This revision was landed with ongoing or failed builds.Jul 3 2023, 3:52 PM
Closed by commit rG49899cd4cecd: [RISCV] Refactor vfcvt_rm pseudo insertion case statements. NFC (authored by luke). · Explain Why
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG49899cd4cecd: [RISCV] Refactor vfcvt_rm pseudo insertion case statements. NFC.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
195 lines

Diff 536912

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 14,029 Lines • ▼ Show 20 LinesRISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case RISCV::PseudoQuietFLT_D: case RISCV::PseudoQuietFLT_D:
return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget); return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget);
case RISCV::PseudoQuietFLT_D_INX: case RISCV::PseudoQuietFLT_D_INX:
return emitQuietFCMP(MI, BB, RISCV::FLT_D_INX, RISCV::FEQ_D_INX, Subtarget); return emitQuietFCMP(MI, BB, RISCV::FLT_D_INX, RISCV::FEQ_D_INX, Subtarget);
case RISCV::PseudoQuietFLT_D_IN32X: case RISCV::PseudoQuietFLT_D_IN32X:
return emitQuietFCMP(MI, BB, RISCV::FLT_D_IN32X, RISCV::FEQ_D_IN32X, return emitQuietFCMP(MI, BB, RISCV::FLT_D_IN32X, RISCV::FEQ_D_IN32X,
Subtarget); Subtarget);
// ========================================================================= #define PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, LMUL) \
// VFCVT case RISCV::RMOpc##_##LMUL##_MASK: \
// ========================================================================= return emitVFCVT_RM_MASK(MI, BB, RISCV::Opc##_##LMUL##_MASK);
#define PseudoVFCVT_RM_CASE(RMOpc, Opc) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, M1) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, M2) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, M4) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, MF2) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, MF4)
#define PseudoVFCVT_RM_CASE_M8(RMOpc, Opc) \
PseudoVFCVT_RM_CASE(RMOpc, Opc) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, M8)
#define PseudoVFCVT_RM_CASE_MF8(RMOpc, Opc) \
PseudoVFCVT_RM_CASE(RMOpc, Opc) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, MF8)
case RISCV::PseudoVFCVT_RM_X_F_V_M1_MASK: // VFCVT
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK); PseudoVFCVT_RM_CASE_M8(PseudoVFCVT_RM_X_F_V, PseudoVFCVT_X_F_V)
case RISCV::PseudoVFCVT_RM_X_F_V_M2_MASK: PseudoVFCVT_RM_CASE_M8(PseudoVFCVT_RM_XU_F_V, PseudoVFCVT_XU_F_V)
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M2_MASK); PseudoVFCVT_RM_CASE_M8(PseudoVFCVT_RM_F_XU_V, PseudoVFCVT_F_XU_V)
case RISCV::PseudoVFCVT_RM_X_F_V_M4_MASK: PseudoVFCVT_RM_CASE_M8(PseudoVFCVT_RM_F_X_V, PseudoVFCVT_F_X_V)
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M4_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_M8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M8_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF2_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF4_MASK);
case RISCV::PseudoVFCVT_RM_XU_F_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_M1_MASK);
case RISCV::PseudoVFCVT_RM_XU_F_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_M2_MASK);
case RISCV::PseudoVFCVT_RM_XU_F_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_M4_MASK);
case RISCV::PseudoVFCVT_RM_XU_F_V_M8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_M8_MASK);
case RISCV::PseudoVFCVT_RM_XU_F_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_MF2_MASK);
case RISCV::PseudoVFCVT_RM_XU_F_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_XU_F_V_MF4_MASK);
case RISCV::PseudoVFCVT_RM_F_XU_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_M1_MASK);
case RISCV::PseudoVFCVT_RM_F_XU_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_M2_MASK);
case RISCV::PseudoVFCVT_RM_F_XU_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_M4_MASK);
case RISCV::PseudoVFCVT_RM_F_XU_V_M8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_M8_MASK);
case RISCV::PseudoVFCVT_RM_F_XU_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_MF2_MASK);
case RISCV::PseudoVFCVT_RM_F_XU_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_XU_V_MF4_MASK);
case RISCV::PseudoVFCVT_RM_F_X_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M1_MASK);
case RISCV::PseudoVFCVT_RM_F_X_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M2_MASK);
case RISCV::PseudoVFCVT_RM_F_X_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M4_MASK);
case RISCV::PseudoVFCVT_RM_F_X_V_M8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_M8_MASK);
case RISCV::PseudoVFCVT_RM_F_X_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_MF2_MASK);
case RISCV::PseudoVFCVT_RM_F_X_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_F_X_V_MF4_MASK);
// =========================================================================
// VFWCVT // VFWCVT
// ========================================================================= PseudoVFCVT_RM_CASE(PseudoVFWCVT_RM_XU_F_V, PseudoVFWCVT_XU_F_V);
PseudoVFCVT_RM_CASE(PseudoVFWCVT_RM_X_F_V, PseudoVFWCVT_X_F_V);
PseudoVFCVT_RM_CASE_MF8(PseudoVFWCVT_RM_F_XU_V, PseudoVFWCVT_F_XU_V);
PseudoVFCVT_RM_CASE_MF8(PseudoVFWCVT_RM_F_X_V, PseudoVFWCVT_F_X_V);
case RISCV::PseudoVFWCVT_RM_XU_F_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M1_MASK);
case RISCV::PseudoVFWCVT_RM_XU_F_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M2_MASK);
case RISCV::PseudoVFWCVT_RM_XU_F_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M4_MASK);
case RISCV::PseudoVFWCVT_RM_XU_F_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_MF2_MASK);
case RISCV::PseudoVFWCVT_RM_XU_F_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_MF4_MASK);
case RISCV::PseudoVFWCVT_RM_X_F_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK);
case RISCV::PseudoVFWCVT_RM_X_F_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M2_MASK);
case RISCV::PseudoVFWCVT_RM_X_F_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M4_MASK);
case RISCV::PseudoVFWCVT_RM_X_F_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF2_MASK);
case RISCV::PseudoVFWCVT_RM_X_F_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF4_MASK);
case RISCV::PseudoVFWCVT_RM_F_XU_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M1_MASK);
case RISCV::PseudoVFWCVT_RM_F_XU_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M2_MASK);
case RISCV::PseudoVFWCVT_RM_F_XU_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M4_MASK);
case RISCV::PseudoVFWCVT_RM_F_XU_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF2_MASK);
case RISCV::PseudoVFWCVT_RM_F_XU_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF4_MASK);
case RISCV::PseudoVFWCVT_RM_F_XU_V_MF8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK);
case RISCV::PseudoVFWCVT_RM_F_X_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M1_MASK);
case RISCV::PseudoVFWCVT_RM_F_X_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M2_MASK);
case RISCV::PseudoVFWCVT_RM_F_X_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M4_MASK);
case RISCV::PseudoVFWCVT_RM_F_X_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF2_MASK);
case RISCV::PseudoVFWCVT_RM_F_X_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF4_MASK);
case RISCV::PseudoVFWCVT_RM_F_X_V_MF8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF8_MASK);
// =========================================================================
// VFNCVT // VFNCVT
// ========================================================================= PseudoVFCVT_RM_CASE_MF8(PseudoVFNCVT_RM_XU_F_W, PseudoVFNCVT_XU_F_W);
PseudoVFCVT_RM_CASE_MF8(PseudoVFNCVT_RM_X_F_W, PseudoVFNCVT_X_F_W);
case RISCV::PseudoVFNCVT_RM_XU_F_W_M1_MASK: PseudoVFCVT_RM_CASE(PseudoVFNCVT_RM_F_XU_W, PseudoVFNCVT_F_XU_W);
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M1_MASK); PseudoVFCVT_RM_CASE(PseudoVFNCVT_RM_F_X_W, PseudoVFNCVT_F_X_W);
case RISCV::PseudoVFNCVT_RM_XU_F_W_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M2_MASK);
case RISCV::PseudoVFNCVT_RM_XU_F_W_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M4_MASK);
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF2_MASK);
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF4_MASK);
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF8_MASK);
case RISCV::PseudoVFNCVT_RM_X_F_W_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M1_MASK);
case RISCV::PseudoVFNCVT_RM_X_F_W_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M2_MASK);
case RISCV::PseudoVFNCVT_RM_X_F_W_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M4_MASK);
case RISCV::PseudoVFNCVT_RM_X_F_W_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF2_MASK);
case RISCV::PseudoVFNCVT_RM_X_F_W_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF4_MASK);
case RISCV::PseudoVFNCVT_RM_X_F_W_MF8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF8_MASK);
case RISCV::PseudoVFNCVT_RM_F_XU_W_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M1_MASK);
case RISCV::PseudoVFNCVT_RM_F_XU_W_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M2_MASK);
case RISCV::PseudoVFNCVT_RM_F_XU_W_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M4_MASK);
case RISCV::PseudoVFNCVT_RM_F_XU_W_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF2_MASK);
case RISCV::PseudoVFNCVT_RM_F_XU_W_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK);
case RISCV::PseudoVFNCVT_RM_F_X_W_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M1_MASK);
case RISCV::PseudoVFNCVT_RM_F_X_W_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M2_MASK);
case RISCV::PseudoVFNCVT_RM_F_X_W_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M4_MASK);
case RISCV::PseudoVFNCVT_RM_F_X_W_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_MF2_MASK);
case RISCV::PseudoVFNCVT_RM_F_X_W_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_MF4_MASK);
case RISCV::PseudoVFROUND_NOEXCEPT_V_M1_MASK: case RISCV::PseudoVFROUND_NOEXCEPT_V_M1_MASK:
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK, return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK,
RISCV::PseudoVFCVT_F_X_V_M1_MASK); RISCV::PseudoVFCVT_F_X_V_M1_MASK);
case RISCV::PseudoVFROUND_NOEXCEPT_V_M2_MASK: case RISCV::PseudoVFROUND_NOEXCEPT_V_M2_MASK:
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M2_MASK, return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M2_MASK,
RISCV::PseudoVFCVT_F_X_V_M2_MASK); RISCV::PseudoVFCVT_F_X_V_M2_MASK);
case RISCV::PseudoVFROUND_NOEXCEPT_V_M4_MASK: case RISCV::PseudoVFROUND_NOEXCEPT_V_M4_MASK:
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