[RISCV] Add support for XCVbitmanip extension in CV32E40P

[melonedo]

Summary

Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj.

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[melonedo]

Add usage, merge tests and ensure 80-char limit

[melonedo]

Fix typo

[melonedo]

Remove excessive test header

[melonedo]

[RISCV] Add support for XCVbitmanip extension in CV32E40P

Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1926

I think we're doing one file per vendor

[melonedo]

Switch to one file per vendor

[melonedo]

Add contributor

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

16

I think you can use RVInstI and a let imm12 = {funct2, is3, is2};

35

I think you can use RVInstR?

52

I think you can use RVInstR and a let rs2 = 0b00000

71

I think you can use RVInstR and merge the remaining fields of RVInstBitManipRR here?

86

Is the only difference between this and CVBitManipRII the uimm2 for $is3? Maybe you could make that a template argument to CVBitManipRII that defaults to uimm5, but can be changed.

94

I think it's usual to put $rd first in ins?

97

Same here

[melonedo]

Reuse RVInstI/R and enable test for disassembler

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

 ``XTHeadVdot``
   LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
 ``XSfvcp``
   LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
+
+``XCVbitmanip``
+  LLVM implements `version 1.3.1 of the Core-V bit manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
                           "XTHeadMemPair custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
                           DecoderTableTHeadSync32,
                           "XTHeadSync custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableTHeadV32,
                           "XTHeadVdot custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
                           "SiFive VCIX custom opcode table");
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
+                          DecoderTableXCVbitmanip32,
+                          "CORE-V Bit Manipulation custom opcode table");
     TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
     return MCDisassembler::Fail;
   }
 
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCVFeatures.td

 def FeatureVendorXSfvcp
     : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
                        "XSfvcp (SiFive Custom Vector Coprocessor Interface Instructions)",
                        [FeatureStdExtZve32x]>;
 def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
                                 AssemblerPredicate<(all_of FeatureVendorXSfvcp),
                                 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
 
+
+def FeatureVendorXCVbitmanip
+    : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
+                       "'XCVbitmanip' (Bit Manipulation)">;
+def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
+                                AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
+                                "'XCVbitmanip' (Bit Manipulation)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoXVentana.td"
 include "RISCVInstrInfoXTHead.td"
 include "RISCVInstrInfoXSf.td"
+include "RISCVInstrInfoXCV.td"

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

+//===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Core-V extensions.
+//
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XCVbitmanip" in {
+  class RVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr>
+      : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
+    bits<5> is3;
+    bits<5> is2;
+    let imm12 = {funct2, is3, is2};
+  }
+
+  class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr, 
+                      Operand i3type = uimm5>
+      : RVInstBitManipRII<funct2, funct3, (outs GPR:$rd), 
+                          (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
+                          opcodestr, "$rd, $rs1, $is3, $is2">;
+
+  class CVBitManipRR<bits<7> funct7, string opcodestr>
+      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd), 
+                (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+  class CVBitManipR<bits<7> funct7, string opcodestr>
+      : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd), 
+                (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1"> {
+    let rs2 = 0b00000;
+  }
+}
+
+let Predicates = [HasVendorXCVbitmanip, IsRV32], 
+    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
+  def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
+
+  def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
+  def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
+  def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
+
+  def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
+  def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
+
+  let Constraints = "$rd = $rd_wb" in {
+    def CV_INSERT : RVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
+                             (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
+                             "cv.insert", "$rd, $rs1, $is3, $is2">;
+    def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb), 
+                             (ins GPR:$rd, GPR:$rs1, GPR:$rs2), 
+                             "cv.insertr", "$rd, $rs1, $rs2">;
+  }
+
+  def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
+  def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
+
+  def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
+  def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
+  def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
+  def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
+  def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;
+}

llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvbitmanip %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.extract t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.extract t0, t1, 0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extract t0, t1, t2
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extract t0, t1, t2, t3
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extract t0, t1, 0, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extract t0, t1, 0, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extract t0, t1, 32, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extract t0, t1, -1, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extractu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.extractu t0, t1, 0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extractu t0, t1, t2
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extractu t0, t1, t2, t3
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extractu t0, t1, 0, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extractu t0, t1, 0, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extractu t0, t1, 32, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.extractu t0, t1, -1, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.insert t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.insert t0, t1, 0
+# CHECK-ERROR: too few operands for instruction
+
+cv.insert t0, t1, t2
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.insert t0, t1, t2, t3
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.insert t0, t1, 0, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.insert t0, t1, 0, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.insert t0, t1, 32, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.insert t0, t1, -1, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bclr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.bclr t0, t1, 0
+# CHECK-ERROR: too few operands for instruction
+
+cv.bclr t0, t1, t2
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bclr t0, t1, t2, t3
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bclr t0, t1, 0, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bclr t0, t1, 0, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bclr t0, t1, 32, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bclr t0, t1, -1, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bset t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.bset t0, t1, 0
+# CHECK-ERROR: too few operands for instruction
+
+cv.bset t0, t1, t2
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bset t0, t1, t2, t3
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bset t0, t1, 0, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bset t0, t1, 0, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bset t0, t1, 32, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bset t0, t1, -1, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bitrev t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.bitrev t0, t1, 0
+# CHECK-ERROR: too few operands for instruction
+
+cv.bitrev t0, t1, t2
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+cv.bitrev t0, t1, t2, t3
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+cv.bitrev t0, t1, 0, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bitrev t0, t1, 0, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.bitrev t0, t1, 32, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+cv.bitrev t0, t1, -1, 0
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+
+cv.extractr t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extractr t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extractr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extractr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.extractur t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extractur t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extractur t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extractur t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.insertr t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.insertr t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.insertr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.insertr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.bclrr t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.bclrr t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.bclrr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.bclrr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.bsetr t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.bsetr t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.bsetr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.bsetr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.ror t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.ror t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.ror t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.ror t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.ff1 t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.ff1 t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.ff1 t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.ff1 t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction 
+
+cv.fl1 t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.fl1 t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.fl1 t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.fl1 t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction 
+
+cv.clb t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.clb t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clb t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clb t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction 
+
+cv.cnt t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.cnt t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.cnt t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.cnt t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction 
+

llvm/test/MC/RISCV/corev/XCVbitmanip.s

+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvbitmanip -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvbitmanip < %s \
+# RUN:     | llvm-objdump --mattr=+xcvbitmanip -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.extract t0, t1, 0, 1
+# CHECK-INSTR: cv.extract t0, t1, 0, 1
+# CHECK-ENCODING: [0xdb,0x02,0x13,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extract a0, a1, 17, 18
+# CHECK-INSTR: cv.extract a0, a1, 17, 18
+# CHECK-ENCODING: [0x5b,0x85,0x25,0x23]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extract s0, s1, 30, 31
+# CHECK-INSTR: cv.extract s0, s1, 30, 31
+# CHECK-ENCODING: [0x5b,0x84,0xf4,0x3d]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractu t0, t1, 0, 1
+# CHECK-INSTR: cv.extractu t0, t1, 0, 1
+# CHECK-ENCODING: [0xdb,0x02,0x13,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractu a0, a1, 17, 18
+# CHECK-INSTR: cv.extractu a0, a1, 17, 18
+# CHECK-ENCODING: [0x5b,0x85,0x25,0x63]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractu s0, s1, 30, 31
+# CHECK-INSTR: cv.extractu s0, s1, 30, 31
+# CHECK-ENCODING: [0x5b,0x84,0xf4,0x7d]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.insert t0, t1, 0, 1
+# CHECK-INSTR: cv.insert t0, t1, 0, 1
+# CHECK-ENCODING: [0xdb,0x02,0x13,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.insert a0, a1, 17, 18
+# CHECK-INSTR: cv.insert a0, a1, 17, 18
+# CHECK-ENCODING: [0x5b,0x85,0x25,0xa3]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.insert s0, s1, 30, 31
+# CHECK-INSTR: cv.insert s0, s1, 30, 31
+# CHECK-ENCODING: [0x5b,0x84,0xf4,0xbd]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bclr t0, t1, 0, 1
+# CHECK-INSTR: cv.bclr t0, t1, 0, 1
+# CHECK-ENCODING: [0xdb,0x12,0x13,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bclr a0, a1, 17, 18
+# CHECK-INSTR: cv.bclr a0, a1, 17, 18
+# CHECK-ENCODING: [0x5b,0x95,0x25,0x23]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bclr s0, s1, 30, 31
+# CHECK-INSTR: cv.bclr s0, s1, 30, 31
+# CHECK-ENCODING: [0x5b,0x94,0xf4,0x3d]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bset t0, t1, 0, 1
+# CHECK-INSTR: cv.bset t0, t1, 0, 1
+# CHECK-ENCODING: [0xdb,0x12,0x13,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bset a0, a1, 17, 18
+# CHECK-INSTR: cv.bset a0, a1, 17, 18
+# CHECK-ENCODING: [0x5b,0x95,0x25,0x63]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bset s0, s1, 30, 31
+# CHECK-INSTR: cv.bset s0, s1, 30, 31
+# CHECK-ENCODING: [0x5b,0x94,0xf4,0x7d]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bitrev t0, t1, 0, 1
+# CHECK-INSTR: cv.bitrev t0, t1, 0, 1
+# CHECK-ENCODING: [0xdb,0x12,0x13,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bitrev a0, a1, 1, 18
+# CHECK-INSTR: cv.bitrev a0, a1, 1, 18
+# CHECK-ENCODING: [0x5b,0x95,0x25,0xc3]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bitrev s0, s1, 2, 31
+# CHECK-INSTR: cv.bitrev s0, s1, 2, 31
+# CHECK-ENCODING: [0x5b,0x94,0xf4,0xc5]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractr t0, t1, t2
+# CHECK-INSTR: cv.extractr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x30]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractr a0, a1, a2
+# CHECK-INSTR: cv.extractr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x30]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractr s0, s1, s2
+# CHECK-INSTR: cv.extractr s0, s1, s2
+# CHECK-ENCODING: [0x2b,0xb4,0x24,0x31]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractur t0, t1, t2
+# CHECK-INSTR: cv.extractur t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x32]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractur a0, a1, a2
+# CHECK-INSTR: cv.extractur a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x32]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.extractur s0, s1, s2
+# CHECK-INSTR: cv.extractur s0, s1, s2
+# CHECK-ENCODING: [0x2b,0xb4,0x24,0x33]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.insertr t0, t1, t2
+# CHECK-INSTR: cv.insertr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x34]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.insertr a0, a1, a2
+# CHECK-INSTR: cv.insertr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x34]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.insertr s0, s1, s2
+# CHECK-INSTR: cv.insertr s0, s1, s2
+# CHECK-ENCODING: [0x2b,0xb4,0x24,0x35]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bclrr t0, t1, t2
+# CHECK-INSTR: cv.bclrr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x38]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bclrr a0, a1, a2
+# CHECK-INSTR: cv.bclrr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x38]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bclrr s0, s1, s2
+# CHECK-INSTR: cv.bclrr s0, s1, s2
+# CHECK-ENCODING: [0x2b,0xb4,0x24,0x39]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bsetr t0, t1, t2
+# CHECK-INSTR: cv.bsetr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x3a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bsetr a0, a1, a2
+# CHECK-INSTR: cv.bsetr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x3a]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.bsetr s0, s1, s2
+# CHECK-INSTR: cv.bsetr s0, s1, s2
+# CHECK-ENCODING: [0x2b,0xb4,0x24,0x3b]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.ror t0, t1, t2
+# CHECK-INSTR: cv.ror t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.ror a0, a1, a2
+# CHECK-INSTR: cv.ror a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.ror s0, s1, s2
+# CHECK-INSTR: cv.ror s0, s1, s2
+# CHECK-ENCODING: [0x2b,0xb4,0x24,0x41]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.ff1 t0, t1
+# CHECK-INSTR: cv.ff1 t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x42]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.ff1 a0, a1
+# CHECK-INSTR: cv.ff1 a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x42]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.ff1 s0, s1
+# CHECK-INSTR: cv.ff1 s0, s1
+# CHECK-ENCODING: [0x2b,0xb4,0x04,0x42]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.fl1 t0, t1
+# CHECK-INSTR: cv.fl1 t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x44]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.fl1 a0, a1
+# CHECK-INSTR: cv.fl1 a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x44]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.fl1 s0, s1
+# CHECK-INSTR: cv.fl1 s0, s1
+# CHECK-ENCODING: [0x2b,0xb4,0x04,0x44]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.clb t0, t1
+# CHECK-INSTR: cv.clb t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x46]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.clb a0, a1
+# CHECK-INSTR: cv.clb a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x46]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.clb s0, s1
+# CHECK-INSTR: cv.clb s0, s1
+# CHECK-ENCODING: [0x2b,0xb4,0x04,0x46]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.cnt t0, t1
+# CHECK-INSTR: cv.cnt t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x48]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.cnt a0, a1
+# CHECK-INSTR: cv.cnt a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x48]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+
+cv.cnt s0, s1
+# CHECK-INSTR: cv.cnt s0, s1
+# CHECK-ENCODING: [0x2b,0xb4,0x04,0x48]
+# CHECK-NO-EXT: instruction requires the following: 'XCVbitmanip' (Bit Manipulation){{$}}
+