[RISCV] Add MC layer support for Zicfiss.

[fakepaper56]

Summary

The patch adds the instructions in Zicfiss extension. Zicfisslp extension is
to support shadow stack for control flow integrity.

[fakepaper56]

The patch might be too early to be posted. The idea is to make people easier to develop shadow-stack/landing-pads, although it will land for long time.

[fakepaper56]

Update instruction information and mark ssp as reserved register.

[fakepaper56]

Make the patch only focus on Zicfiss.

[fakepaper56]

Fix bugs.

[craig.topper]

clang/test/Preprocessor/riscv-target-features.c

75

This needs to be renamed to remove lp

725

This needs to be renamed to remove lp

llvm/lib/Target/RISCV/RISCVFeatures.td

84

Zicfiss

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1921

This needs to be rebased, the files here were moved into groups.

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

1 ↗

(On Diff #543857)

Filename doesn't match

35 ↗

(On Diff #543857)

Can we use RVInstI by adding let imm12 = 0b100000011100 to the body?

66 ↗

(On Diff #543857)

Can this use RVInstI with lets for imm12, rs1, and rd?

75 ↗

(On Diff #543857)

Can this use RVInstR?

87 ↗

(On Diff #543857)

Can this use RVInstR?

98 ↗

(On Diff #543857)

RVInstR

[fakepaper56]

This comment was removed by fakepaper56.

[fakepaper56]

This comment was removed by fakepaper56.

[fakepaper56]

Address Craig's comment.

[craig.topper]

Please update llvm/docs/RISCVUsage.rst

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

233

Is this used?

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

35 ↗

(On Diff #544228)

Why are there ins and outs here that aren't encoded?

56 ↗

(On Diff #544228)

Need to be able to parse with ra instead of x1 and t0 instead of x5.

I think you might need a new Operand type so the parse can parse it as a register.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1923

Put this with the other RISCVInstrInfoZi* files under "Integer"

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

92 ↗

(On Diff #544228)

Can we merge the X1 and X5 instructions? Looks like the register is encoded?

[Jim]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

33 ↗

(On Diff #544228)

Two let lines can be merged?

58 ↗

(On Diff #544228)

Add a blank line before this line.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

56 ↗

(On Diff #544228)

Need to be able to parse with ra instead of x1 and t0 instead of x5.

Actually, we can parse ssload ra in llvm/test/MC/RISCV/zicfiss-valid.s, but the code indeed can not print ssload ra. I have tried to define ssload and sspopchk separately, but it caused decode conflict.

[fakepaper56]

Bump to 0.2 and address part of comments.

[fakepaper56]

Make asmprinter capable to print alias register name for ssload/sspopchk/c.sspush/c.sspopchk.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

56 ↗

(On Diff #544228)

The problem is fixed in latest update.

[craig.topper]

Please update docs/RISCVUsage.rst

[fakepaper56]

Update docs/RISCVUsage.rst.

[fakepaper56]

This comment was removed by fakepaper56.

[fakepaper56]

Update docs/RISCVUsage.rst to move zicfiss to experimental extension.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

88 ↗

(On Diff #550083)

Is it compatible with Zca?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

32 ↗

(On Diff #550083)

Can you call this rs1val instead of rs1 since $rs1 is part of the ins.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

88 ↗

(On Diff #550083)

The spec does not mention it is incompatible with Zca. I think I need to enable c.push/c.popchk for Zca.

[fakepaper56]

Address comments.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

37 ↗

(On Diff #550578)

Do we need the rs1 variable or can we use rs1val here? We usually have the rs1 field because the encoder maps ins/outs operand names to the field name. In this case we have an explicit immediate passed as rs1val. Is the encoding value coming from the operand or from the immediate? I can't tell with the name conflict.

[fakepaper56]

Address comment.

[craig.topper]

LGTM

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

1 ↗

(On Diff #550987)

CFG?

48–49 ↗

(On Diff #550987)

This is some strange wrapping; normally we'd put RVInstI on the same line and wrap some of the arguments, but if you really want to wrap then indent by 4 spaces and put the colon on the lower line, that's what the predominant style is

62 ↗

(On Diff #550987)

This is how I'd expect the earlier instructions to be formatted, FWIW... please be consistent

94 ↗

(On Diff #550987)

Missing space

[fakepaper56]

Address jrtc27's comment.

[fakepaper56]

This comment was removed by fakepaper56.

[SuH]

llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

76 ↗

(On Diff #550998)

After v0.2 SSPUSH encoding already changed from 0b1000101 to 0b1000001

[fakepaper56]

Closed it and create a PR https://github.com/llvm/llvm-project/pull/66043 for version 0.3.1.

clang/test/Preprocessor/riscv-target-features.c

 // CHECK-NOT: __riscv_zvksh {{.*$}}
 // CHECK-NOT: __riscv_zvkt {{.*$}}
 // CHECK-NOT: __riscv_zicond {{.*$}}
 // CHECK-NOT: __riscv_smaia {{.*$}}
 // CHECK-NOT: __riscv_ssaia {{.*$}}
 // CHECK-NOT: __riscv_zfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfmin {{.*$}}
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zicfisslp {{.*$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 // CHECK: __riscv_i 2001000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \

 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN: -march=rv32ifzvfbfwma0p6 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
 // RUN: -march=rv64ifzvfbfwma0p6 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
 // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 6000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfisslp0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISSLP-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfisslp0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISSLP-EXT %s
+// CHECK-ZICFISSLP-EXT: __riscv_zicfisslp 1000{{$}}

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"smaia", RISCVExtensionVersion{1, 0}},
     {"ssaia", RISCVExtensionVersion{1, 0}},
 
     {"zihintntl", RISCVExtensionVersion{0, 2}},
+    {"zicfisslp", RISCVExtensionVersion{0, 1}},
 
     {"zca", RISCVExtensionVersion{1, 0}},
     {"zcb", RISCVExtensionVersion{1, 0}},
     {"zcd", RISCVExtensionVersion{1, 0}},
     {"zcf", RISCVExtensionVersion{1, 0}},
+    {"zicfsslp", RISCVExtensionVersion{1, 0}},
     {"zcmp", RISCVExtensionVersion{1, 0}},
     {"zcmt", RISCVExtensionVersion{1, 0}},
     {"zfa", RISCVExtensionVersion{0, 2}},
     {"zfbfmin", RISCVExtensionVersion{0, 6}},
     {"zicond", RISCVExtensionVersion{1, 0}},
     {"zvfbfmin", RISCVExtensionVersion{0, 6}},
     {"zvfbfwma", RISCVExtensionVersion{0, 6}},
     {"zvfh", RISCVExtensionVersion{0, 1}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

public:
   bool isUImm1() const { return IsUImm<1>(); }
   bool isUImm2() const { return IsUImm<2>(); }
   bool isUImm3() const { return IsUImm<3>(); }
   bool isUImm4() const { return IsUImm<4>(); }
   bool isUImm5() const { return IsUImm<5>(); }
   bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
   bool isUImm8() const { return IsUImm<8>(); }
+  bool isUImm10() const { return IsUImm<10>(); }
+
+  bool isUImm5NonZero() const {
+    if (!isImm())
+      return false;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && Imm != 0 &&
+           isUInt<5>(fixImmediateForRV32(Imm, isRV64Imm())) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
 
   bool isUImm8GE32() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<8>(Imm) && Imm >= 32 &&
case Match_InvalidUImm2Lsb0:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2,
                                       "immediate must be one of");
   case Match_InvalidUImm3:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
   case Match_InvalidUImm4:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
   case Match_InvalidUImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
+  case Match_InvalidUImm5NonZero:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
   case Match_InvalidUImm6:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
   case Match_InvalidUImm7:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1);
   case Match_InvalidUImm8:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 1);
+  case Match_InvalidUImm10:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 10) - 1);
   case Match_InvalidUImm8GE32:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 32, (1 << 8) - 1);
   case Match_InvalidSImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4),
                                       (1 << 4) - 1);
   case Match_InvalidSImm6:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5),
                                       (1 << 5) - 1);

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
   if (RegNo >= 32 || (IsRVE && RegNo >= 16))
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::X0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
+  MCRegister Reg = RISCV::X0 + RegNo;
+  if (Reg != RISCV::X1 && Reg != RISCV::X5)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::F0_H + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM2,
   OPERAND_UIMM2_LSB0,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
+  OPERAND_UIMM5_NONZERO,
   OPERAND_UIMM6,
   OPERAND_UIMM7,
   OPERAND_UIMM7_LSB00,
   OPERAND_UIMM8_LSB00,
   OPERAND_UIMM8,
   OPERAND_UIMM8_LSB000,
   OPERAND_UIMM8_GE32,
   OPERAND_UIMM9_LSB000,
+  OPERAND_UIMM10,
   OPERAND_UIMM10_LSB00_NONZERO,
   OPERAND_UIMM12,
   OPERAND_ZERO,
   OPERAND_SIMM5,
   OPERAND_SIMM5_PLUS1,
   OPERAND_SIMM6,
   OPERAND_SIMM6_NONZERO,
   OPERAND_SIMM10_LSB0000_NONZERO,

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureStdExtZihintntl
     : SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
                        "'zihintntl' (Non-Temporal Locality Hints)">;
 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
                                     AssemblerPredicate<(all_of FeatureStdExtZihintntl),
                                     "'Zihintntl' (Non-Temporal Locality Hints)">;
 
+def FeatureStdExtZicfisslp
+    : SubtargetFeature<"experimental-zicfisslp", "HasStdExtZicfisslp", "true",
+                       "'zicfisslp' (Shadow-stack and Landing-pads)">;
+def HasStdExtZicfisslp : Predicate<"Subtarget->hasStdExtZicfisslp()">,
+                                    AssemblerPredicate<(all_of FeatureStdExtZicfisslp),
+                                    "'Zicfisslp' (Shadow-stack and Landing-pads)">;
+
 def FeatureStdExtZifencei
     : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
                        "'zifencei' (fence.i)">;
 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
                                    AssemblerPredicate<(all_of FeatureStdExtZifencei),
                                    "'Zifencei' (fence.i)">;
 
 def FeatureStdExtZicntr

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<5>;
   let DecoderMethod = "decodeUImmOperand<5>";
   let OperandType = "OPERAND_UIMM5";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm10 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<10>;
+  let DecoderMethod = "decodeUImmOperand<10>";
+  let OperandType = "OPERAND_UIMM10";
+  let OperandNamespace = "RISCVOp";
+}
+
 def InsnDirectiveOpcode : AsmOperandClass {
   let Name = "InsnDirectiveOpcode";
   let ParserMethod = "parseInsnDirectiveOpcode";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isImm";
 }
 
 def uimm6 : Operand<XLenVT> {

 include "RISCVInstrInfoZc.td"
 include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfa.td"
 include "RISCVInstrInfoZfbfmin.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
 include "RISCVInstrInfoZicond.td"
+include "RISCVInstrInfoZicfisslp.td"
 
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoXVentana.td"
 include "RISCVInstrInfoXTHead.td"
 include "RISCVInstrInfoXSf.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZicfisslp.td

+//===-- RISCVInstrInfoZ.td - RISC-V CFG -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm5nonzero : Operand<XLenVT>,
+                   ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmNonZeroOperand<5>";
+  let OperandType = "OPERAND_UIMM5_NONZERO";
+  let OperandNamespace = "RISCVOp";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (MCOp.evaluateAsConstantImm(Imm))
+      return (Imm != 0) && isUInt<5>(Imm);
+    return MCOp.isBareSymbolRef();
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let Uses = [SSP] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class RV_SSPop<bits<5> rd, bits<5> rs1, string opcodestr, string argstr> :
+  RVInst<(outs GPR:$rd), (ins GPR:$rs1), opcodestr, argstr, [], InstFormatI> {
+  let Inst{31-20} = 0b100000011100;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = OPC_SYSTEM.Value;
+}
+} // Uses = [SSP]
+
+class RVC_SSInst<bits<5> rs1, string opcodestr, string argstr> :
+  RVInst16<(outs), (ins:$rs1), opcodestr, argstr, [], InstFormatOther> {
+  let Inst{15-13} = 0b011;
+  let Inst{12} = 0;
+  let Inst{11-7} = rs1;
+  let Inst{6-2} = 0b00000;
+  let Inst{1-0} = 0b01;
+}
+
+let Uses = [X7], hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class RV_LPInst<bits<7> funct7, string opcodestr> :
+  RVInst<(outs), (ins uimm10:$uimm10), opcodestr, "$uimm10", [], InstFormatOther> {
+  bits<10> uimm10;
+  let Inst{31-25} = funct7;
+  let Inst{24-15} = uimm10;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = 0b00000;
+  let Inst{6-0} = OPC_SYSTEM.Value;
+}
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZicfisslp] in {
+def SSLoadX1: RV_SSPop<0b00000, 0b00001, "ssload", "x1">;
+def SSLoadX5: RV_SSPop<0b00000, 0b00101, "ssload", "x5">;
+let Defs = [SSP] in {
+def SSPopChkX1: RV_SSPop<0b00001, 0b00000, "sspopchk", "x1">;
+def SSPopChkX5: RV_SSPop<0b00101, 0b00000, "sspopchk", "x5">;
+} // Defs = [SSP]
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSPINC : RVInst<(outs), (ins uimm5nonzero:$imm), "sspinc", "$imm", [], InstFormatI> {
+  bits<5> imm;
+  let Inst{31-20} = 0b100000011101;
+  let Inst{19-15} = imm;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = 0b00000;
+  let Inst{6-0} = OPC_SYSTEM.Value;
+}
+
+def SSPRR : RVInst<(outs GPRNoX0:$rd), (ins), "ssprr", "$rd", [], InstFormatR> {
+  bits<5> rd;
+  let Inst{31-25} = 0b1000011;
+  let Inst{24-20} = 0b00000;
+  let Inst{19-15} = 0b00000;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = OPC_SYSTEM.Value;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+def SSPUSH : RVInst<(outs), (ins GPRRA:$rs2), "sspush", "$rs2", [], InstFormatR> {
+  bits<5> rs2;
+  let Inst{31-25} = 0b1000101;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = 0b00000;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = 0b00000;
+  let Inst{6-0} = OPC_SYSTEM.Value;
+}
+
+def SSAMOSWAP :
+  RVInst<(outs GPRNoX0:$dest), (ins GPR:$addr, GPR:$src),
+         "ssamoswap", "$dest, $src, (${addr})", [], InstFormatR> {
+  bits<5> dest;
+  bits<5> src;
+  bits<5> addr;
+  let Inst{31-25} = 0b1000001;
+  let Inst{24-20} = src;
+  let Inst{19-15} = addr;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = dest;
+  let Inst{6-0} = OPC_SYSTEM.Value;
+}
+} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
+} // Predicates = [HasStdExtZicfisslp]
+
+let Predicates = [HasStdExtZicfisslp, HasStdExtC] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def C_SSPUSHX1 : RVC_SSInst<0b00001, "c.sspush", "x1">;
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def C_SSPopChkX5 : RVC_SSInst<0b00101, "c.sspopchk", "x5">;
+}// Predicates = [HasStdExtZicfisslp, HasStdExtC]
+
+let Predicates = [HasStdExtZicfisslp] in {
+def LPCLL : RV_LPInst<0b1000001, "lpcll">;
+def LPCNL : RV_LPInst<0b1000011, "lpcnl">;
+} // Predicates = [HasStdExtZicfisslp]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
   markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
 
   // Floating point environment registers.
   markSuperRegs(Reserved, RISCV::FRM);
   markSuperRegs(Reserved, RISCV::FFLAGS);
 
+  // Shadow stack pointer.
+  markSuperRegs(Reserved, RISCV::SSP);
+
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                          MCRegister PhysReg) const {
   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
 }

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 // Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension
 def SR07 : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 23)
   )> {
   let RegInfos = XLenRI;
 }
 
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
+  let RegInfos = XLenRI;
+}
+
 // Floating point registers
 let RegAltNameIndices = [ABIRegAltName] in {
   def F0_H  : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
   def F1_H  : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
   def F2_H  : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
   def F3_H  : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
   def F4_H  : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
   def F5_H  : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
def "VRN" # nf # "M" # m: VReg<[untyped],
                                     !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
                                     !mul(nf, m)>;
   }
 }
 
 // Special registers
 def FFLAGS : RISCVReg<0, "fflags">;
 def FRM    : RISCVReg<0, "frm">;
+
+// Shadow Stack register
+def SSP    : RISCVReg<0, "ssp">;

llvm/test/MC/RISCV/attribute-arch.s

 .attribute arch, "rv32i_zfbfmin0p6"
 # CHECK: .attribute     5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
 
 .attribute arch, "rv32i_zvfbfmin0p6"
 # CHECK: .attribute     5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
 
 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute     5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv32i_zicfisslp0p1"
+# CHECK: .attribute     5, "rv32i2p1_zicfisslp0p1"

llvm/test/MC/RISCV/zicfisslp-invalid.s

+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN:     2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+
+# CHECK-ERR: error: invalid operand for instruction
+ssload a0
+
+# CHECK-ERR: error: invalid operand for instruction
+sspopchk a1
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspush t0
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspopchk ra
+
+# CHECK-ERR: error: immediate must be an integer in the range [1, 31]
+sspinc 32
+
+# CHECK-ERR: error: invalid operand for instruction
+sspush a0
+
+# CHECK-ERR: error: invalid operand for instruction
+ssprr zero
+
+# CHECK-ERR: error: invalid operand for instruction
+ssamoswap zero, x0, (a0)
+
+# CHECK-ERR: error: immediate must be an integer in the range [0, 1023]
+lpcll 0x4AA
+
+# CHECK-ERR: error: immediate must be an integer in the range [0, 1023]
+lpcnl 0x4AA

llvm/test/MC/RISCV/zicfisslp-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspush ra
+
+# CHECK-ASM-AND-OBJ: c.sspopchk x5
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspopchk x5
+
+# CHECK-ASM-AND-OBJ: c.sspopchk x5
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspopchk t0
+
+# CHECK-ASM-AND-OBJ: lpcll 682
+# CHECK-ASM: encoding: [0x73,0x40,0x55,0x83]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+lpcll 0x2AA
+
+# CHECK-ASM-AND-OBJ: lpcnl 955
+# CHECK-ASM: encoding: [0x73,0xc0,0xdd,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+lpcnl 0x3BB