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Differential D152750

[RISCV] Enable SLP by default (when vectors are available)
ClosedPublic

Authored by reames on Jun 12 2023, 1:45 PM.

Details

Reviewers
craig.topper
luke
ABataev
kito-cheng
frasercrmck
Commits
rG7f26c27e03f1: [RISCV] Enable SLP by default (when vectors are available)
Summary

I propose that we go ahead and enabled SLP by default. Over the last few weeks, @luke and I have been working through codegen issues seen at small VLs from a couple of SPEC workloads. We still have a ways to go to get optimal codegen, but we're at the point where having a single configuration we're all tuning against is probably the right default.

As a bit of history, I introduced this TTI hook back in a310637132 back in August of last year to unblock enabling LoopVectorizer. At the time, we had a couple known issues: constant materialization, address generation, and a general lack of maturity of small fixed vector codegen. By now, each of these has had significant investment. I can't say any of them are completely fixed, but we're no longer seeing instances of them every place we look.

What we're mostly seeing at this point is a long tail of code gen opportunities, many involving build vectors, shuffles, and extract patterns. I have a couple patches up to continue iterating on those issues, but I don't think they need to be blockers for enabling SLP. The only debateable one is D152001 , and I'm prepared to leave it up to which gets approved first. :)

Diff Detail

Event Timeline

reames created this revision.Jun 12 2023, 1:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 12 2023, 1:45 PM
Herald added subscribers: jobnoorman, vporpo, VincentWu and 28 others. · View Herald Transcript
reames requested review of this revision.Jun 12 2023, 1:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 12 2023, 1:45 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
ABataev accepted this revision.Jun 12 2023, 1:51 PM

I can try to provide a better fix for D152001 after vacation (2 weeks)

This revision is now accepted and ready to land.Jun 12 2023, 1:51 PM
Harbormaster completed remote builds in B238300: Diff 530657.Jun 12 2023, 3:10 PM
zlxu-rivai added a subscriber: zlxu-rivai.Jun 13 2023, 2:41 AM
This revision was landed with ongoing or failed builds.Jun 14 2023, 9:58 AM
Closed by commit rG7f26c27e03f1: [RISCV] Enable SLP by default (when vectors are available) (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG7f26c27e03f1: [RISCV] Enable SLP by default (when vectors are available).
leonardchan added a subscriber: leonardchan.Jun 14 2023, 12:23 PM

Hi. It looks like this is failing to build for us on windows host https://logs.chromium.org/logs/fuchsia/buildbucket/cr-buildbucket/8778294144728066337/+/u/clang/build/stdout?format=raw with:

FAILED: lib/Target/RISCV/CMakeFiles/LLVMRISCVCodeGen.dir/RISCVTargetTransformInfo.cpp.obj 
C:\b\s\w\ir\x\w\cipd\bin\clang-cl.exe  /nologo -TP -DGTEST_HAS_RTTI=0 -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_ASSERTIONS -D_HAS_EXCEPTIONS=0 -D_LIBCPP_ENABLE_ASSERTIONS -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -IC:\b\s\w\ir\x\w\staging\llvm_build\lib\Target\RISCV -IC:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV -IC:\b\s\w\ir\x\w\recipe_cleanup\tensorflow-venv\store\python_venv-b2t7sq1hdmljg9g7sc6p05hel8\contents\Lib\site-packages\tensorflow\include -IC:\b\s\w\ir\x\w\staging\llvm_build\include -IC:\b\s\w\ir\x\w\llvm-llvm-project\llvm\include -imsvcC:\b\s\w\ir\x\w\staging\zlib_install_target\include -imsvcC:\b\s\w\ir\x\w\staging\zstd_install\include /DWIN32 /D_WINDOWS   /Zc:inline /Zc:__cplusplus /Oi /Brepro /bigobj /permissive- /W4  -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported /Gw -no-canonical-prefixes /MT /O2 /Ob2 -std:c++17  /EHs-c- /GR- -UNDEBUG /showIncludes /Folib\Target\RISCV\CMakeFiles\LLVMRISCVCodeGen.dir\RISCVTargetTransformInfo.cpp.obj /Fdlib\Target\RISCV\CMakeFiles\LLVMRISCVCodeGen.dir\LLVMRISCVCodeGen.pdb -c -- C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\RISCVTargetTransformInfo.cpp
C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\RISCVTargetTransformInfo.cpp(1759,10): error: no matching function for call to 'max'
 1759 |   return std::max(1UL, RegWidth.getFixedValue() / ElemWidth);
      |          ^~~~~~~~
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\utility(41,6): note: candidate template ignored: deduced conflicting types for parameter '_Ty' ('unsigned long' vs. 'ScalarTy' (aka 'unsigned long long'))
   41 |     (max) (const _Ty& _Left, const _Ty& _Right) noexcept(noexcept(_Left < _Right)) /* strengthened */ {
      |      ^
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\algorithm(9868,26): note: candidate template ignored: could not match 'initializer_list<_Ty>' against 'unsigned long'
 9868 | _NODISCARD constexpr _Ty(max)(initializer_list<_Ty> _Ilist, _Pr _Pred) {
      |                          ^
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\algorithm(9875,26): note: candidate function template not viable: requires single argument '_Ilist', but 2 arguments were provided
 9875 | _NODISCARD constexpr _Ty(max)(initializer_list<_Ty> _Ilist) {
      |                          ^
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\utility(31,33): note: candidate function template not viable: requires 3 arguments, but 2 were provided
   31 | _NODISCARD constexpr const _Ty&(max) (const _Ty& _Left, const _Ty& _Right, _Pr _Pred) noexcept(
      |                                 ^
1 error generated.

Would you be able to send out a fix or revert? Thanks.

jrtc27 added a comment.Jun 14 2023, 12:24 PM
In D152750#4422232, @leonardchan wrote:

Hi. It looks like this is failing to build for us on windows host https://logs.chromium.org/logs/fuchsia/buildbucket/cr-buildbucket/8778294144728066337/+/u/clang/build/stdout?format=raw with:

FAILED: lib/Target/RISCV/CMakeFiles/LLVMRISCVCodeGen.dir/RISCVTargetTransformInfo.cpp.obj 
C:\b\s\w\ir\x\w\cipd\bin\clang-cl.exe  /nologo -TP -DGTEST_HAS_RTTI=0 -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_ASSERTIONS -D_HAS_EXCEPTIONS=0 -D_LIBCPP_ENABLE_ASSERTIONS -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -IC:\b\s\w\ir\x\w\staging\llvm_build\lib\Target\RISCV -IC:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV -IC:\b\s\w\ir\x\w\recipe_cleanup\tensorflow-venv\store\python_venv-b2t7sq1hdmljg9g7sc6p05hel8\contents\Lib\site-packages\tensorflow\include -IC:\b\s\w\ir\x\w\staging\llvm_build\include -IC:\b\s\w\ir\x\w\llvm-llvm-project\llvm\include -imsvcC:\b\s\w\ir\x\w\staging\zlib_install_target\include -imsvcC:\b\s\w\ir\x\w\staging\zstd_install\include /DWIN32 /D_WINDOWS   /Zc:inline /Zc:__cplusplus /Oi /Brepro /bigobj /permissive- /W4  -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported /Gw -no-canonical-prefixes /MT /O2 /Ob2 -std:c++17  /EHs-c- /GR- -UNDEBUG /showIncludes /Folib\Target\RISCV\CMakeFiles\LLVMRISCVCodeGen.dir\RISCVTargetTransformInfo.cpp.obj /Fdlib\Target\RISCV\CMakeFiles\LLVMRISCVCodeGen.dir\LLVMRISCVCodeGen.pdb -c -- C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\RISCVTargetTransformInfo.cpp
C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\RISCVTargetTransformInfo.cpp(1759,10): error: no matching function for call to 'max'
 1759 |   return std::max(1UL, RegWidth.getFixedValue() / ElemWidth);
      |          ^~~~~~~~
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\utility(41,6): note: candidate template ignored: deduced conflicting types for parameter '_Ty' ('unsigned long' vs. 'ScalarTy' (aka 'unsigned long long'))
   41 |     (max) (const _Ty& _Left, const _Ty& _Right) noexcept(noexcept(_Left < _Right)) /* strengthened */ {
      |      ^
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\algorithm(9868,26): note: candidate template ignored: could not match 'initializer_list<_Ty>' against 'unsigned long'
 9868 | _NODISCARD constexpr _Ty(max)(initializer_list<_Ty> _Ilist, _Pr _Pred) {
      |                          ^
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\algorithm(9875,26): note: candidate function template not viable: requires single argument '_Ilist', but 2 arguments were provided
 9875 | _NODISCARD constexpr _Ty(max)(initializer_list<_Ty> _Ilist) {
      |                          ^
C:\b\s\w\ir\cache\windows_sdk\VC\Tools\MSVC\14.34.31933\include\utility(31,33): note: candidate function template not viable: requires 3 arguments, but 2 were provided
   31 | _NODISCARD constexpr const _Ty&(max) (const _Ty& _Left, const _Ty& _Right, _Pr _Pred) noexcept(
      |                                 ^
1 error generated.

Would you be able to send out a fix or revert? Thanks.

defb5cd783e1

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
25 lines
test/
Transforms/
SLPVectorizer/
RISCV/
171 lines
130 lines
35 lines
132 lines

Diff 531403

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show All 24 Linesstatic cl::opt<unsigned> RVVRegisterWidthLMUL(
cl::desc( cl::desc(
"The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
"by autovectorized code. Fractional LMULs are not supported."), "by autovectorized code. Fractional LMULs are not supported."),
cl::init(2), cl::Hidden); cl::init(2), cl::Hidden);
static cl::opt<unsigned> SLPMaxVF( static cl::opt<unsigned> SLPMaxVF(
"riscv-v-slp-max-vf", "riscv-v-slp-max-vf",
cl::desc( cl::desc(
"Result used for getMaximumVF query which is used exclusively by " "Overrides result used for getMaximumVF query which is used "
"SLP vectorizer. Defaults to 1 which disables SLP."), "exclusively by SLP vectorizer."),
cl::init(1), cl::Hidden); cl::Hidden);
InstructionCost RISCVTTIImpl::getLMULCost(MVT VT) { InstructionCost RISCVTTIImpl::getLMULCost(MVT VT) {
// TODO: Here assume reciprocal throughput is 1 for LMUL_1, it is // TODO: Here assume reciprocal throughput is 1 for LMUL_1, it is
// implementation-defined. // implementation-defined.
if (!VT.isVector()) if (!VT.isVector())
return InstructionCost::getInvalid(); return InstructionCost::getInvalid();
unsigned DLenFactor = ST->getDLenFactor(); unsigned DLenFactor = ST->getDLenFactor();
unsigned Cost; unsigned Cost;
▲ Show 20 Lines • Show All 1,695 Lines • ▼ Show 20 Lines if (Ty->isVectorTy()) {
if (ST->useRVVForFixedLengthVectors()) if (ST->useRVVForFixedLengthVectors())
return divideCeil(Size, ST->getRealMinVLen()); return divideCeil(Size, ST->getRealMinVLen());
} }
return BaseT::getRegUsageForType(Ty); return BaseT::getRegUsageForType(Ty);
} }
unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
// This interface is currently only used by SLP. Returning 1 (which is the if (SLPMaxVF.getNumOccurrences())
// default value for SLPMaxVF) disables SLP. We currently have a cost modeling
// problem w/ constant materialization which causes SLP to perform majorly
// unprofitable transformations.
// TODO: Figure out constant materialization cost modeling and remove.
return SLPMaxVF; return SLPMaxVF;
// Return how many elements can fit in getRegisterBitwidth. This is the
// same routine as used in LoopVectorizer. We should probably be
// accounting for whether we actually have instructions with the right
// lane type, but we don't have enough information to do that without
// some additional plumbing which hasn't been justified yet.
TypeSize RegWidth =
getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector);
// If no vector registers, or absurd element widths, disable
// vectorization by returning 1.
return std::max(1UL, RegWidth.getFixedValue() / ElemWidth);
} }
bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1, bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
const TargetTransformInfo::LSRCost &C2) { const TargetTransformInfo::LSRCost &C2) {
// RISC-V specific here are "instruction number 1st priority". // RISC-V specific here are "instruction number 1st priority".
return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
C1.NumIVMuls, C1.NumBaseAdds, C1.NumIVMuls, C1.NumBaseAdds,
C1.ScaleCost, C1.ImmCost, C1.SetupCost) < C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
C2.NumIVMuls, C2.NumBaseAdds, C2.NumIVMuls, C2.NumBaseAdds,
C2.ScaleCost, C2.ImmCost, C2.SetupCost); C2.ScaleCost, C2.ImmCost, C2.SetupCost);
} }

llvm/test/Transforms/SLPVectorizer/RISCV/floating-point.ll

Show All 12 Lines
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[TMP0]], [[TMP1]]
; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_add ; DEFAULT-LABEL: define void @fp_add
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]], ptr [[Q:%.*]]) #[[ATTR0:[0-9]+]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]], ptr [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[TMP0]], [[TMP1]]
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2 ; DEFAULT-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[F0:%.*]] = load float, ptr [[Q]], align 4
; DEFAULT-NEXT: [[PF1:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load float, ptr [[PF1]], align 4
; DEFAULT-NEXT: [[PF2:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 2
; DEFAULT-NEXT: [[F2:%.*]] = load float, ptr [[PF2]], align 4
; DEFAULT-NEXT: [[PF3:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 3
; DEFAULT-NEXT: [[F3:%.*]] = load float, ptr [[PF3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = fadd float [[E0]], [[F0]]
; DEFAULT-NEXT: [[A1:%.*]] = fadd float [[E1]], [[F1]]
; DEFAULT-NEXT: [[A2:%.*]] = fadd float [[E2]], [[F2]]
; DEFAULT-NEXT: [[A3:%.*]] = fadd float [[E3]], [[F3]]
; DEFAULT-NEXT: store float [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 1
; DEFAULT-NEXT: store float [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 2
; DEFAULT-NEXT: store float [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 3
; DEFAULT-NEXT: store float [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
Show All 31 Lines
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> [[TMP0]], <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00> ; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x float> [[TMP0]], <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_sub ; DEFAULT-LABEL: define void @fp_sub
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = fsub <4 x float> [[TMP0]], <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = fsub float [[E0]], 3.000000e+00
; DEFAULT-NEXT: [[A1:%.*]] = fsub float [[E1]], 3.000000e+00
; DEFAULT-NEXT: [[A2:%.*]] = fsub float [[E2]], 3.000000e+00
; DEFAULT-NEXT: [[A3:%.*]] = fsub float [[E3]], 3.000000e+00
; DEFAULT-NEXT: store float [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 1
; DEFAULT-NEXT: store float [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 2
; DEFAULT-NEXT: store float [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 3
; DEFAULT-NEXT: store float [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
Show All 24 Lines
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x float> [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x float> [[TMP0]], [[TMP1]]
; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_mul ; DEFAULT-LABEL: define void @fp_mul
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: [[TMP2:%.*]] = fmul <4 x float> [[TMP0]], [[TMP1]]
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2 ; DEFAULT-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[F0:%.*]] = load float, ptr [[Q]], align 4
; DEFAULT-NEXT: [[PF1:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load float, ptr [[PF1]], align 4
; DEFAULT-NEXT: [[PF2:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 2
; DEFAULT-NEXT: [[F2:%.*]] = load float, ptr [[PF2]], align 4
; DEFAULT-NEXT: [[PF3:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 3
; DEFAULT-NEXT: [[F3:%.*]] = load float, ptr [[PF3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = fmul float [[E0]], [[F0]]
; DEFAULT-NEXT: [[A1:%.*]] = fmul float [[E1]], [[F1]]
; DEFAULT-NEXT: [[A2:%.*]] = fmul float [[E2]], [[F2]]
; DEFAULT-NEXT: [[A3:%.*]] = fmul float [[E3]], [[F3]]
; DEFAULT-NEXT: store float [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 1
; DEFAULT-NEXT: store float [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 2
; DEFAULT-NEXT: store float [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 3
; DEFAULT-NEXT: store float [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
Show All 31 Lines
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <4 x float> [[TMP0]], <float 1.050000e+01, float 1.050000e+01, float 1.050000e+01, float 1.050000e+01> ; CHECK-NEXT: [[TMP1:%.*]] = fdiv <4 x float> [[TMP0]], <float 1.050000e+01, float 1.050000e+01, float 1.050000e+01, float 1.050000e+01>
; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_div ; DEFAULT-LABEL: define void @fp_div
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = fdiv <4 x float> [[TMP0]], <float 1.050000e+01, float 1.050000e+01, float 1.050000e+01, float 1.050000e+01>
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = fdiv float [[E0]], 1.050000e+01
; DEFAULT-NEXT: [[A1:%.*]] = fdiv float [[E1]], 1.050000e+01
; DEFAULT-NEXT: [[A2:%.*]] = fdiv float [[E2]], 1.050000e+01
; DEFAULT-NEXT: [[A3:%.*]] = fdiv float [[E3]], 1.050000e+01
; DEFAULT-NEXT: store float [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 1
; DEFAULT-NEXT: store float [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 2
; DEFAULT-NEXT: store float [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 3
; DEFAULT-NEXT: store float [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP0]], <4 x float> [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP0]], <4 x float> [[TMP1]])
; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_max ; DEFAULT-LABEL: define void @fp_max
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]], ptr [[Q:%.*]]) #[[ATTR0]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[Q]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP0]], <4 x float> [[TMP1]])
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2 ; DEFAULT-NEXT: store <4 x float> [[TMP2]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[F0:%.*]] = load float, ptr [[Q]], align 4
; DEFAULT-NEXT: [[PF1:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load float, ptr [[PF1]], align 4
; DEFAULT-NEXT: [[PF2:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 2
; DEFAULT-NEXT: [[F2:%.*]] = load float, ptr [[PF2]], align 4
; DEFAULT-NEXT: [[PF3:%.*]] = getelementptr inbounds float, ptr [[Q]], i64 3
; DEFAULT-NEXT: [[F3:%.*]] = load float, ptr [[PF3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = tail call float @llvm.maxnum.f32(float [[E0]], float [[F0]])
; DEFAULT-NEXT: [[A1:%.*]] = tail call float @llvm.maxnum.f32(float [[E1]], float [[F1]])
; DEFAULT-NEXT: [[A2:%.*]] = tail call float @llvm.maxnum.f32(float [[E2]], float [[F2]])
; DEFAULT-NEXT: [[A3:%.*]] = tail call float @llvm.maxnum.f32(float [[E3]], float [[F3]])
; DEFAULT-NEXT: store float [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 1
; DEFAULT-NEXT: store float [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 2
; DEFAULT-NEXT: store float [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 3
; DEFAULT-NEXT: store float [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
Show All 33 Lines
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP0]], <4 x float> <float 1.250000e+00, float 1.250000e+00, float 1.250000e+00, float 1.250000e+00>) ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP0]], <4 x float> <float 1.250000e+00, float 1.250000e+00, float 1.250000e+00, float 1.250000e+00>)
; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_min ; DEFAULT-LABEL: define void @fp_min
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP0]], <4 x float> <float 1.250000e+00, float 1.250000e+00, float 1.250000e+00, float 1.250000e+00>)
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: store <4 x float> [[TMP1]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = tail call float @llvm.minnum.f32(float [[E0]], float 1.250000e+00)
; DEFAULT-NEXT: [[A1:%.*]] = tail call float @llvm.minnum.f32(float [[E1]], float 1.250000e+00)
; DEFAULT-NEXT: [[A2:%.*]] = tail call float @llvm.minnum.f32(float [[E2]], float 1.250000e+00)
; DEFAULT-NEXT: [[A3:%.*]] = tail call float @llvm.minnum.f32(float [[E3]], float 1.250000e+00)
; DEFAULT-NEXT: store float [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 1
; DEFAULT-NEXT: store float [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 2
; DEFAULT-NEXT: store float [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds float, ptr [[DST]], i64 3
; DEFAULT-NEXT: store float [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> [[TMP0]])
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[DST]], align 4 ; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[DST]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: define void @fp_convert ; DEFAULT-LABEL: define void @fp_convert
; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] { ; DEFAULT-SAME: (ptr [[DST:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load float, ptr [[P]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[P]], align 4
; DEFAULT-NEXT: [[PE1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> [[TMP0]])
; DEFAULT-NEXT: [[E1:%.*]] = load float, ptr [[PE1]], align 4 ; DEFAULT-NEXT: store <4 x i32> [[TMP1]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PE2:%.*]] = getelementptr inbounds float, ptr [[P]], i64 2
; DEFAULT-NEXT: [[E2:%.*]] = load float, ptr [[PE2]], align 4
; DEFAULT-NEXT: [[PE3:%.*]] = getelementptr inbounds float, ptr [[P]], i64 3
; DEFAULT-NEXT: [[E3:%.*]] = load float, ptr [[PE3]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = tail call i32 @llvm.fptosi.sat.i32.f32(float [[E0]])
; DEFAULT-NEXT: [[A1:%.*]] = tail call i32 @llvm.fptosi.sat.i32.f32(float [[E1]])
; DEFAULT-NEXT: [[A2:%.*]] = tail call i32 @llvm.fptosi.sat.i32.f32(float [[E2]])
; DEFAULT-NEXT: [[A3:%.*]] = tail call i32 @llvm.fptosi.sat.i32.f32(float [[E3]])
; DEFAULT-NEXT: store i32 [[A0]], ptr [[DST]], align 4
; DEFAULT-NEXT: [[PA1:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 1
; DEFAULT-NEXT: store i32 [[A1]], ptr [[PA1]], align 4
; DEFAULT-NEXT: [[PA2:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 2
; DEFAULT-NEXT: store i32 [[A2]], ptr [[PA2]], align 4
; DEFAULT-NEXT: [[PA3:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 3
; DEFAULT-NEXT: store i32 [[A3]], ptr [[PA3]], align 4
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load float, ptr %p, align 4 %e0 = load float, ptr %p, align 4
%pe1 = getelementptr inbounds float, ptr %p, i64 1 %pe1 = getelementptr inbounds float, ptr %p, i64 1
%e1 = load float, ptr %pe1, align 4 %e1 = load float, ptr %pe1, align 4
%pe2 = getelementptr inbounds float, ptr %p, i64 2 %pe2 = getelementptr inbounds float, ptr %p, i64 2
%e2 = load float, ptr %pe2, align 4 %e2 = load float, ptr %pe2, align 4
Show All 18 Lines

llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \ ; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \
; RUN: -riscv-v-vector-bits-min=-1 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK ; RUN: -riscv-v-vector-bits-min=-1 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK
; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v -S | FileCheck %s --check-prefixes=DEFAULT ; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v -S | FileCheck %s --check-prefixes=DEFAULT
define void @vec_add(ptr %dest, ptr %p) { define void @vec_add(ptr %dest, ptr %p) {
; CHECK-LABEL: @vec_add( ; CHECK-LABEL: @vec_add(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1> ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1>
; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_add( ; DEFAULT-LABEL: @vec_add(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1>
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = add i16 [[E0]], 1
; DEFAULT-NEXT: [[A1:%.*]] = add i16 [[E1]], 1
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%a0 = add i16 %e0, 1 %a0 = add i16 %e0, 1
Show All 10 Lines
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i16> [[TMP0]], <i16 17, i16 17> ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i16> [[TMP0]], <i16 17, i16 17>
; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_sub( ; DEFAULT-LABEL: @vec_sub(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = sub <2 x i16> [[TMP0]], <i16 17, i16 17>
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = sub i16 [[E0]], 17
; DEFAULT-NEXT: [[A1:%.*]] = sub i16 [[E1]], 17
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%a0 = sub i16 %e0, 17 %a0 = sub i16 %e0, 17
Show All 10 Lines
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i16> <i16 29, i16 29>, [[TMP0]] ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i16> <i16 29, i16 29>, [[TMP0]]
; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_rsub( ; DEFAULT-LABEL: @vec_rsub(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = sub <2 x i16> <i16 29, i16 29>, [[TMP0]]
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = sub i16 29, [[E0]]
; DEFAULT-NEXT: [[A1:%.*]] = sub i16 29, [[E1]]
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%a0 = sub i16 29, %e0 %a0 = sub i16 29, %e0
Show All 10 Lines
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i16> [[TMP0]], <i16 7, i16 7> ; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i16> [[TMP0]], <i16 7, i16 7>
; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_mul( ; DEFAULT-LABEL: @vec_mul(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = mul <2 x i16> [[TMP0]], <i16 7, i16 7>
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = mul i16 [[E0]], 7
; DEFAULT-NEXT: [[A1:%.*]] = mul i16 [[E1]], 7
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%a0 = mul i16 %e0, 7 %a0 = mul i16 %e0, 7
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; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = sdiv <2 x i16> [[TMP0]], <i16 7, i16 7> ; CHECK-NEXT: [[TMP1:%.*]] = sdiv <2 x i16> [[TMP0]], <i16 7, i16 7>
; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_sdiv( ; DEFAULT-LABEL: @vec_sdiv(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = sdiv <2 x i16> [[TMP0]], <i16 7, i16 7>
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = sdiv i16 [[E0]], 7
; DEFAULT-NEXT: [[A1:%.*]] = sdiv i16 [[E1]], 7
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%a0 = sdiv i16 %e0, 7 %a0 = sdiv i16 %e0, 7
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i16> [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i16> [[TMP0]], [[TMP1]]
; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_and( ; DEFAULT-LABEL: @vec_and(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: [[TMP2:%.*]] = and <2 x i16> [[TMP0]], [[TMP1]]
; DEFAULT-NEXT: [[F0:%.*]] = load i16, ptr [[Q:%.*]], align 4 ; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INQ:%.*]] = getelementptr inbounds i16, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load i16, ptr [[INQ]], align 2
; DEFAULT-NEXT: [[A0:%.*]] = and i16 [[E0]], [[F0]]
; DEFAULT-NEXT: [[A1:%.*]] = and i16 [[E1]], [[F1]]
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%f0 = load i16, ptr %q, align 4 %f0 = load i16, ptr %q, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i16> [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i16> [[TMP0]], [[TMP1]]
; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_or( ; DEFAULT-LABEL: @vec_or(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: [[TMP2:%.*]] = or <2 x i16> [[TMP0]], [[TMP1]]
; DEFAULT-NEXT: [[F0:%.*]] = load i16, ptr [[Q:%.*]], align 4 ; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INQ:%.*]] = getelementptr inbounds i16, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load i16, ptr [[INQ]], align 2
; DEFAULT-NEXT: [[A0:%.*]] = or i16 [[E0]], [[F0]]
; DEFAULT-NEXT: [[A1:%.*]] = or i16 [[E1]], [[F1]]
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%f0 = load i16, ptr %q, align 4 %f0 = load i16, ptr %q, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i16> [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i16> [[TMP0]], [[TMP1]]
; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_sll( ; DEFAULT-LABEL: @vec_sll(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: [[TMP2:%.*]] = shl <2 x i16> [[TMP0]], [[TMP1]]
; DEFAULT-NEXT: [[F0:%.*]] = load i16, ptr [[Q:%.*]], align 4 ; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INQ:%.*]] = getelementptr inbounds i16, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load i16, ptr [[INQ]], align 2
; DEFAULT-NEXT: [[A0:%.*]] = shl i16 [[E0]], [[F0]]
; DEFAULT-NEXT: [[A1:%.*]] = shl i16 [[E1]], [[F1]]
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%f0 = load i16, ptr %q, align 4 %f0 = load i16, ptr %q, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_smin( ; DEFAULT-LABEL: @vec_smin(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
; DEFAULT-NEXT: [[F0:%.*]] = load i16, ptr [[Q:%.*]], align 4 ; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INQ:%.*]] = getelementptr inbounds i16, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load i16, ptr [[INQ]], align 2
; DEFAULT-NEXT: [[A0:%.*]] = tail call i16 @llvm.smin.i16(i16 [[E0]], i16 [[F0]])
; DEFAULT-NEXT: [[A1:%.*]] = tail call i16 @llvm.smin.i16(i16 [[E1]], i16 [[F1]])
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%f0 = load i16, ptr %q, align 4 %f0 = load i16, ptr %q, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_umax( ; DEFAULT-LABEL: @vec_umax(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[Q:%.*]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
; DEFAULT-NEXT: [[F0:%.*]] = load i16, ptr [[Q:%.*]], align 4 ; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INQ:%.*]] = getelementptr inbounds i16, ptr [[Q]], i64 1
; DEFAULT-NEXT: [[F1:%.*]] = load i16, ptr [[INQ]], align 2
; DEFAULT-NEXT: [[A0:%.*]] = tail call i16 @llvm.umax.i16(i16 [[E0]], i16 [[F0]])
; DEFAULT-NEXT: [[A1:%.*]] = tail call i16 @llvm.umax.i16(i16 [[E1]], i16 [[F1]])
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%f0 = load i16, ptr %q, align 4 %f0 = load i16, ptr %q, align 4
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llvm/test/Transforms/SLPVectorizer/RISCV/load-store.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \ ; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \
; RUN: -riscv-v-vector-bits-min=-1 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK ; RUN: -riscv-v-vector-bits-min=-1 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK
; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v -S | FileCheck %s --check-prefixes=DEFAULT ; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v -S | FileCheck %s --check-prefixes=DEFAULT
define void @simple_copy(ptr %dest, ptr %p) { define void @simple_copy(ptr %dest, ptr %p) {
; CHECK-LABEL: @simple_copy( ; CHECK-LABEL: @simple_copy(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: store <2 x i16> [[TMP0]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP0]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @simple_copy( ; DEFAULT-LABEL: @simple_copy(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: store <2 x i16> [[TMP0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2
; DEFAULT-NEXT: store i16 [[E0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[E1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
store i16 %e0, ptr %dest, align 4 store i16 %e0, ptr %dest, align 4
%inc2 = getelementptr inbounds i16, ptr %dest, i64 1 %inc2 = getelementptr inbounds i16, ptr %dest, i64 1
store i16 %e1, ptr %inc2, align 2 store i16 %e1, ptr %inc2, align 2
ret void ret void
} }
define void @vec_add(ptr %dest, ptr %p) { define void @vec_add(ptr %dest, ptr %p) {
; CHECK-LABEL: @vec_add( ; CHECK-LABEL: @vec_add(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1> ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1>
; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @vec_add( ; DEFAULT-LABEL: @vec_add(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
; DEFAULT-NEXT: [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1 ; DEFAULT-NEXT: [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1>
; DEFAULT-NEXT: [[E1:%.*]] = load i16, ptr [[INC]], align 2 ; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[A0:%.*]] = add i16 [[E0]], 1
; DEFAULT-NEXT: [[A1:%.*]] = add i16 [[E1]], 1
; DEFAULT-NEXT: store i16 [[A0]], ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i16 [[A1]], ptr [[INC2]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
%e0 = load i16, ptr %p, align 4 %e0 = load i16, ptr %p, align 4
%inc = getelementptr inbounds i16, ptr %p, i64 1 %inc = getelementptr inbounds i16, ptr %p, i64 1
%e1 = load i16, ptr %inc, align 2 %e1 = load i16, ptr %inc, align 2
%a0 = add i16 %e0, 1 %a0 = add i16 %e0, 1
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define void @splat_store_i32_zero(ptr %dest) { define void @splat_store_i32_zero(ptr %dest) {
; CHECK-LABEL: @splat_store_i32_zero( ; CHECK-LABEL: @splat_store_i32_zero(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @splat_store_i32_zero( ; DEFAULT-LABEL: @splat_store_i32_zero(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: store i32 0, ptr [[DEST:%.*]], align 4 ; DEFAULT-NEXT: store <4 x i32> zeroinitializer, ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC1:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i32 0, ptr [[INC1]], align 2
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 2
; DEFAULT-NEXT: store i32 0, ptr [[INC2]], align 2
; DEFAULT-NEXT: [[INC3:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 3
; DEFAULT-NEXT: store i32 0, ptr [[INC3]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
store i32 0, ptr %dest, align 4 store i32 0, ptr %dest, align 4
%inc1 = getelementptr inbounds i32, ptr %dest, i64 1 %inc1 = getelementptr inbounds i32, ptr %dest, i64 1
store i32 0, ptr %inc1, align 2 store i32 0, ptr %inc1, align 2
%inc2 = getelementptr inbounds i32, ptr %dest, i64 2 %inc2 = getelementptr inbounds i32, ptr %dest, i64 2
store i32 0, ptr %inc2, align 2 store i32 0, ptr %inc2, align 2
%inc3 = getelementptr inbounds i32, ptr %dest, i64 3 %inc3 = getelementptr inbounds i32, ptr %dest, i64 3
store i32 0, ptr %inc3, align 2 store i32 0, ptr %inc3, align 2
ret void ret void
} }
define void @splat_store_i32_one(ptr %dest) { define void @splat_store_i32_one(ptr %dest) {
; CHECK-LABEL: @splat_store_i32_one( ; CHECK-LABEL: @splat_store_i32_one(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[DEST:%.*]], align 4 ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[DEST:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; DEFAULT-LABEL: @splat_store_i32_one( ; DEFAULT-LABEL: @splat_store_i32_one(
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: store i32 1, ptr [[DEST:%.*]], align 4 ; DEFAULT-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[DEST:%.*]], align 4
; DEFAULT-NEXT: [[INC1:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 1
; DEFAULT-NEXT: store i32 1, ptr [[INC1]], align 2
; DEFAULT-NEXT: [[INC2:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 2
; DEFAULT-NEXT: store i32 1, ptr [[INC2]], align 2
; DEFAULT-NEXT: [[INC3:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 3
; DEFAULT-NEXT: store i32 1, ptr [[INC3]], align 2
; DEFAULT-NEXT: ret void ; DEFAULT-NEXT: ret void
; ;
entry: entry:
store i32 1, ptr %dest, align 4 store i32 1, ptr %dest, align 4
%inc1 = getelementptr inbounds i32, ptr %dest, i64 1 %inc1 = getelementptr inbounds i32, ptr %dest, i64 1
store i32 1, ptr %inc1, align 2 store i32 1, ptr %inc1, align 2
%inc2 = getelementptr inbounds i32, ptr %dest, i64 2 %inc2 = getelementptr inbounds i32, ptr %dest, i64 2
store i32 1, ptr %inc2, align 2 store i32 1, ptr %inc2, align 2
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll

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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
; DEFAULT-LABEL: define <4 x float> @fabs_4x ; DEFAULT-LABEL: define <4 x float> @fabs_4x
; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1:[0-9]+]] { ; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1:[0-9]+]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @fabsf(float [[VECEXT]]) ; DEFAULT-NEXT: ret <4 x float> [[TMP1]]
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @fabsf(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @fabsf(float [[VECEXT_2]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @fabsf(float [[VECEXT_3]])
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @fabsf(float %vecext) %1 = tail call fast float @fabsf(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @fabsf(float %vecext.1) %2 = tail call fast float @fabsf(float %vecext.1)
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
; DEFAULT-LABEL: define <4 x float> @int_fabs_4x ; DEFAULT-LABEL: define <4 x float> @int_fabs_4x
; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1]] { ; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.fabs.f32(float [[VECEXT]]) ; DEFAULT-NEXT: ret <4 x float> [[TMP1]]
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.fabs.f32(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.fabs.f32(float [[VECEXT_2]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.fabs.f32(float [[VECEXT_3]])
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @llvm.fabs.f32(float %vecext) %1 = tail call fast float @llvm.fabs.f32(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @llvm.fabs.f32(float %vecext.1) %2 = tail call fast float @llvm.fabs.f32(float %vecext.1)
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
; DEFAULT-LABEL: define <4 x float> @sqrt_4x ; DEFAULT-LABEL: define <4 x float> @sqrt_4x
; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1]] { ; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @sqrtf(float [[VECEXT]]) ; DEFAULT-NEXT: ret <4 x float> [[TMP1]]
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @sqrtf(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @sqrtf(float [[VECEXT_2]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @sqrtf(float [[VECEXT_3]])
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @sqrtf(float %vecext) %1 = tail call fast float @sqrtf(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @sqrtf(float %vecext.1) %2 = tail call fast float @sqrtf(float %vecext.1)
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
; DEFAULT-LABEL: define <4 x float> @int_sqrt_4x ; DEFAULT-LABEL: define <4 x float> @int_sqrt_4x
; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1]] { ; DEFAULT-SAME: (ptr [[A:%.*]]) #[[ATTR1]] {
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.sqrt.f32(float [[VECEXT]]) ; DEFAULT-NEXT: ret <4 x float> [[TMP1]]
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.sqrt.f32(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.sqrt.f32(float [[VECEXT_2]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.sqrt.f32(float [[VECEXT_3]])
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @llvm.sqrt.f32(float %vecext) %1 = tail call fast float @llvm.sqrt.f32(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @llvm.sqrt.f32(float %vecext.1) %2 = tail call fast float @llvm.sqrt.f32(float %vecext.1)
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; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @expf(float [[VECEXT]]) ; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @expf(float [[VECEXT]])
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0 ; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1 ; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @expf(float [[VECEXT_1]]) ; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @expf(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1 ; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2 ; DEFAULT-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @expf(float [[VECEXT_2]]) ; DEFAULT-NEXT: [[TMP4:%.*]] = call fast <2 x float> @llvm.exp.v2f32(<2 x float> [[TMP3]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2 ; DEFAULT-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3 ; DEFAULT-NEXT: [[VECINS_31:%.*]] = shufflevector <4 x float> [[VECINS_1]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @expf(float [[VECEXT_3]]) ; DEFAULT-NEXT: ret <4 x float> [[VECINS_31]]
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @expf(float %vecext) %1 = tail call fast float @expf(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @expf(float %vecext.1) %2 = tail call fast float @expf(float %vecext.1)
Show All 32 Lines
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.exp.f32(float [[VECEXT]]) ; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.exp.f32(float [[VECEXT]])
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0 ; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1 ; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.exp.f32(float [[VECEXT_1]]) ; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.exp.f32(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1 ; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2 ; DEFAULT-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.exp.f32(float [[VECEXT_2]]) ; DEFAULT-NEXT: [[TMP4:%.*]] = call fast <2 x float> @llvm.exp.v2f32(<2 x float> [[TMP3]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2 ; DEFAULT-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3 ; DEFAULT-NEXT: [[VECINS_31:%.*]] = shufflevector <4 x float> [[VECINS_1]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.exp.f32(float [[VECEXT_3]]) ; DEFAULT-NEXT: ret <4 x float> [[VECINS_31]]
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @llvm.exp.f32(float %vecext) %1 = tail call fast float @llvm.exp.f32(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @llvm.exp.f32(float %vecext.1) %2 = tail call fast float @llvm.exp.f32(float %vecext.1)
Show All 32 Lines
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @logf(float [[VECEXT]]) ; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @logf(float [[VECEXT]])
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0 ; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1 ; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @logf(float [[VECEXT_1]]) ; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @logf(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1 ; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2 ; DEFAULT-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @logf(float [[VECEXT_2]]) ; DEFAULT-NEXT: [[TMP4:%.*]] = call fast <2 x float> @llvm.log.v2f32(<2 x float> [[TMP3]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2 ; DEFAULT-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3 ; DEFAULT-NEXT: [[VECINS_31:%.*]] = shufflevector <4 x float> [[VECINS_1]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @logf(float [[VECEXT_3]]) ; DEFAULT-NEXT: ret <4 x float> [[VECINS_31]]
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @logf(float %vecext) %1 = tail call fast float @logf(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @logf(float %vecext.1) %2 = tail call fast float @logf(float %vecext.1)
Show All 32 Lines
; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.log.f32(float [[VECEXT]]) ; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.log.f32(float [[VECEXT]])
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0 ; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1 ; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.log.f32(float [[VECEXT_1]]) ; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.log.f32(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1 ; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2 ; DEFAULT-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.log.f32(float [[VECEXT_2]]) ; DEFAULT-NEXT: [[TMP4:%.*]] = call fast <2 x float> @llvm.log.v2f32(<2 x float> [[TMP3]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2 ; DEFAULT-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3 ; DEFAULT-NEXT: [[VECINS_31:%.*]] = shufflevector <4 x float> [[VECINS_1]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.log.f32(float [[VECEXT_3]]) ; DEFAULT-NEXT: ret <4 x float> [[VECINS_31]]
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @llvm.log.f32(float %vecext) %1 = tail call fast float @llvm.log.f32(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @llvm.log.f32(float %vecext.1) %2 = tail call fast float @llvm.log.f32(float %vecext.1)
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; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @sinf(float [[VECEXT]]) ; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @sinf(float [[VECEXT]])
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0 ; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1 ; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @sinf(float [[VECEXT_1]]) ; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @sinf(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1 ; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2 ; DEFAULT-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @sinf(float [[VECEXT_2]]) ; DEFAULT-NEXT: [[TMP4:%.*]] = call fast <2 x float> @llvm.sin.v2f32(<2 x float> [[TMP3]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2 ; DEFAULT-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3 ; DEFAULT-NEXT: [[VECINS_31:%.*]] = shufflevector <4 x float> [[VECINS_1]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @sinf(float [[VECEXT_3]]) ; DEFAULT-NEXT: ret <4 x float> [[VECINS_31]]
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @sinf(float %vecext) %1 = tail call fast float @sinf(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @sinf(float %vecext.1) %2 = tail call fast float @sinf(float %vecext.1)
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; DEFAULT-NEXT: entry: ; DEFAULT-NEXT: entry:
; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16 ; DEFAULT-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 16
; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 ; DEFAULT-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT]]) ; DEFAULT-NEXT: [[TMP1:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT]])
; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0 ; DEFAULT-NEXT: [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1 ; DEFAULT-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_1]]) ; DEFAULT-NEXT: [[TMP2:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_1]])
; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1 ; DEFAULT-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
; DEFAULT-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2 ; DEFAULT-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; DEFAULT-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_2]]) ; DEFAULT-NEXT: [[TMP4:%.*]] = call fast <2 x float> @llvm.sin.v2f32(<2 x float> [[TMP3]])
; DEFAULT-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2 ; DEFAULT-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; DEFAULT-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3 ; DEFAULT-NEXT: [[VECINS_31:%.*]] = shufflevector <4 x float> [[VECINS_1]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; DEFAULT-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_3]]) ; DEFAULT-NEXT: ret <4 x float> [[VECINS_31]]
; DEFAULT-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
; DEFAULT-NEXT: ret <4 x float> [[VECINS_3]]
; ;
entry: entry:
%0 = load <4 x float>, ptr %a, align 16 %0 = load <4 x float>, ptr %a, align 16
%vecext = extractelement <4 x float> %0, i32 0 %vecext = extractelement <4 x float> %0, i32 0
%1 = tail call fast float @llvm.sin.f32(float %vecext) %1 = tail call fast float @llvm.sin.f32(float %vecext)
%vecins = insertelement <4 x float> undef, float %1, i32 0 %vecins = insertelement <4 x float> undef, float %1, i32 0
%vecext.1 = extractelement <4 x float> %0, i32 1 %vecext.1 = extractelement <4 x float> %0, i32 1
%2 = tail call fast float @llvm.sin.f32(float %vecext.1) %2 = tail call fast float @llvm.sin.f32(float %vecext.1)
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