[RISCV] Improve selection for vector fpclass.

[jacquesguan]

Summary

Since vfclass intruction will only set one single bit in the result, so if we only want to check 1 fp class, we could use vmseq to do it.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4465

bool IsOneBitMask = isPowerOf2_32(TDCMask)

[jacquesguan]

Address comment.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Check & fcPosSubnormal)
     TDCMask |= RISCV::FPMASK_Positive_Subnormal;
   if (Check & fcNegSubnormal)
     TDCMask |= RISCV::FPMASK_Negative_Subnormal;
   if (Check & fcPosZero)
     TDCMask |= RISCV::FPMASK_Positive_Zero;
   if (Check & fcNegZero)
     TDCMask |= RISCV::FPMASK_Negative_Zero;
 
+  bool IsOneBitMask = isPowerOf2_32(TDCMask);
+
   SDValue TDCMaskV = DAG.getConstant(TDCMask, DL, XLenVT);
 
   if (VT.isVector()) {
     SDValue Op0 = Op.getOperand(0);
     MVT VT0 = Op.getOperand(0).getSimpleValueType();
 
     if (VT.isScalableVector()) {
       MVT DstVT = VT0.changeVectorElementTypeToInteger();
       auto [Mask, VL] = getDefaultScalableVLOps(VT0, DL, DAG, Subtarget);
       SDValue FPCLASS = DAG.getNode(RISCVISD::FCLASS_VL, DL, DstVT, Op0, Mask,
                                     VL, Op->getFlags());
+      if (IsOneBitMask)
+        return DAG.getSetCC(DL, VT, FPCLASS,
+                            DAG.getConstant(TDCMask, DL, DstVT),
+                            ISD::CondCode::SETEQ);
       SDValue AND = DAG.getNode(ISD::AND, DL, DstVT, FPCLASS,
                                 DAG.getConstant(TDCMask, DL, DstVT));
       return DAG.getSetCC(DL, VT, AND, DAG.getConstant(0, DL, DstVT),
                           ISD::SETNE);
     }
 
     MVT ContainerVT0 = getContainerForFixedLengthVector(VT0);
     MVT ContainerVT = getContainerForFixedLengthVector(VT);
     MVT ContainerDstVT = ContainerVT0.changeVectorElementTypeToInteger();
     auto [Mask, VL] = getDefaultVLOps(VT0, ContainerVT0, DL, DAG, Subtarget);
 
     Op0 = convertToScalableVector(ContainerVT0, Op0, DAG, Subtarget);
 
     SDValue FPCLASS = DAG.getNode(RISCVISD::FCLASS_VL, DL, ContainerDstVT, Op0,
                                   Mask, VL, Op->getFlags());
 
     TDCMaskV = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerDstVT,
                            DAG.getUNDEF(ContainerDstVT), TDCMaskV, VL);
+    if (IsOneBitMask) {
+      SDValue VMSEQ =
+          DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
+                      {FPCLASS, TDCMaskV, DAG.getCondCode(ISD::SETEQ),
+                       DAG.getUNDEF(ContainerVT), Mask, VL});
+      return convertFromScalableVector(VT, VMSEQ, DAG, Subtarget);
+    }
     SDValue AND = DAG.getNode(RISCVISD::AND_VL, DL, ContainerDstVT, FPCLASS,
                               TDCMaskV, DAG.getUNDEF(ContainerDstVT), Mask, VL);
 
     SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
     SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerDstVT,
                             DAG.getUNDEF(ContainerDstVT), SplatZero, VL);
 
     SDValue VMSNE = DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll

 }
 
 define <8 x i1> @isnan_v8f32(<8 x float> %x) {
 ; CHECK-LABEL: isnan_v8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 512
-; CHECK-NEXT:    vand.vx v8, v8, a0
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %1 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> %x, i32 2)
   ret <8 x i1> %1
 }
 
 define <16 x i1> @isnan_v16f32(<16 x float> %x) {
 ; CHECK-LABEL: isnan_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 256
-; CHECK-NEXT:    vand.vx v8, v8, a0
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %1 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> %x, i32 1)
   ret <16 x i1> %1
 }
 
 define <2 x i1> @isnormal_v2f64(<2 x double> %x) {
 ; CHECK-LABEL: isnormal_v2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 129
 ; CHECK-NEXT:    vand.vx v8, v8, a0
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
   %1 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> %x, i32 516) ; 0x204 = "inf"
   ret <2 x i1> %1
 }
 
 define <4 x i1> @isposinf_v4f64(<4 x double> %x) {
 ; CHECK-LABEL: isposinf_v4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 128
-; CHECK-NEXT:    vand.vx v8, v8, a0
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %1 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> %x, i32 512) ; 0x200 = "+inf"
   ret <4 x i1> %1
 }
 
 define <8 x i1> @isneginf_v8f64(<8 x double> %x) {
 ; CHECK-LABEL: isneginf_v8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
-; CHECK-NEXT:    vand.vi v8, v8, 1
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vi v0, v8, 1
 ; CHECK-NEXT:    ret
   %1 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> %x, i32 4) ; "-inf"
   ret <8 x i1> %1
 }
 
 define <16 x i1> @isfinite_v16f64(<16 x double> %x) {
 ; CHECK-LABEL: isfinite_v16f64:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll

 }
 
 define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x) {
 ; CHECK-LABEL: isnan_nxv8f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 512
-; CHECK-NEXT:    vand.vx v8, v8, a0
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2)
   ret <vscale x 8 x i1> %1
 }
 
 define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x) {
 ; CHECK-LABEL: isnan_nxv16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 256
-; CHECK-NEXT:    vand.vx v8, v8, a0
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1)
   ret <vscale x 16 x i1> %1
 }
 
 define <vscale x 2 x i1> @isnormal_nxv2f64(<vscale x 2 x double> %x) {
 ; CHECK-LABEL: isnormal_nxv2f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 129
 ; CHECK-NEXT:    vand.vx v8, v8, a0
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
   %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516) ; 0x204 = "inf"
   ret <vscale x 2 x i1> %1
 }
 
 define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x) {
 ; CHECK-LABEL: isposinf_nxv4f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
 ; CHECK-NEXT:    li a0, 128
-; CHECK-NEXT:    vand.vx v8, v8, a0
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512) ; 0x200 = "+inf"
   ret <vscale x 4 x i1> %1
 }
 
 define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x) {
 ; CHECK-LABEL: isneginf_nxv8f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
 ; CHECK-NEXT:    vfclass.v v8, v8
-; CHECK-NEXT:    vand.vi v8, v8, 1
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vmseq.vi v0, v8, 1
 ; CHECK-NEXT:    ret
   %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4) ; "-inf"
   ret <vscale x 8 x i1> %1
 }
 
 define <vscale x 16 x i1> @isfinite_nxv16f32(<vscale x 16 x float> %x) {
 ; CHECK-LABEL: isfinite_nxv16f32:
 ; CHECK:       # %bb.0: