[RISCV] Don't scalarize vector stores if volatile

[luke]

Summary

As noted by @reames in https://reviews.llvm.org/D151211#4373404, we shouldn't
scalarize vector stores of constants if the store is volatile, or vector copies
if either the store or load are volatile.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case ISD::STORE: {
     auto *Store = cast<StoreSDNode>(N);
     SDValue Chain = Store->getChain();
     EVT MemVT = Store->getMemoryVT();
     SDValue Val = Store->getValue();
     SDLoc DL(N);
 
     bool IsScalarizable =
         MemVT.isFixedLengthVector() && ISD::isNormalStore(Store) &&
+        Store->isSimple() &&
         MemVT.getVectorElementType().bitsLE(Subtarget.getXLenVT()) &&
         isPowerOf2_64(MemVT.getSizeInBits()) &&
         MemVT.getSizeInBits() <= Subtarget.getXLen();
 
     // If sufficiently aligned we can scalarize stores of constant vectors of
     // any power-of-two size up to XLen bits, provided that they aren't too
     // expensive to materialize.
     //   vsetivli   zero, 2, e8, m1, ta, ma
if (DCI.isBeforeLegalize() && IsScalarizable &&
       }
     }
 
     // Similarly, if sufficiently aligned we can scalarize vector copies, e.g.
     //   vsetivli   zero, 2, e16, m1, ta, ma
     //   vle16.v    v8, (a0)
     //   vse16.v    v8, (a1)
     if (auto *L = dyn_cast<LoadSDNode>(Val);
-        L && DCI.isBeforeLegalize() && IsScalarizable &&
+        L && DCI.isBeforeLegalize() && IsScalarizable && L->isSimple() &&
         L->hasNUsesOfValue(1, 0) && L->hasNUsesOfValue(1, 1) &&
         Store->getChain() == SDValue(L, 1) && ISD::isNormalLoad(L) &&
         L->getMemoryVT() == MemVT) {
       MVT NewVT = MVT::getIntegerVT(MemVT.getSizeInBits());
       if (allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
                                          NewVT, *Store->getMemOperand()) &&
           allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
                                          NewVT, *L->getMemOperand())) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll

; CHECK-NEXT:    ret
   ret void
 }
 
 define void @v2i8_volatile_load(ptr %p, ptr %q) {
 ; CHECK-LABEL: v2i8_volatile_load:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    lh a0, 0(a0)
-; CHECK-NEXT:    sh a0, 0(a1)
+; CHECK-NEXT:    vse8.v v8, (a1)
 ; CHECK-NEXT:    ret
   %v = load volatile <2 x i8>, ptr %p
   store <2 x i8> %v, ptr %q
   ret void
 }
 
 define void @v2i8_volatile_store(ptr %p, ptr %q) {
 ; CHECK-LABEL: v2i8_volatile_store:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lh a0, 0(a0)
-; CHECK-NEXT:    sh a0, 0(a1)
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vse8.v v8, (a1)
 ; CHECK-NEXT:    ret
   %v = load <2 x i8>, ptr %p
   store volatile <2 x i8> %v, ptr %q
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

 ; CHECK-LABEL: store_constant_undef_v2i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 768
 ; CHECK-NEXT:    sh a1, 0(a0)
 ; CHECK-NEXT:    ret
   store <2 x i8> <i8 undef, i8 3>, ptr %p
   ret void
 }
+
+define void @store_constant_v2i8_volatile(ptr %p) {
+; CHECK-LABEL: store_constant_v2i8_volatile:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 1
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    ret
+  store volatile <2 x i8> <i8 1, i8 1>, ptr %p
+  ret void
+}